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SDMMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

RESPONSE0

RESPONSE2

RESPONSE4

RESPONSE6

DATA_BUFFER

PRESENT_STATE

HOST_CTRL

POWER_CTRL

BLOCK_GAP_CTRL

WAKEUP_CTRL

CLOCK_CTRL

TIMEOUT_CTRL

SW_RESET

INT_STATUS_NORM

INT_STATUS_ERR

EN_INT_STATUS_NORM

EN_INT_STATUS_ERR

EN_INT_SIGNAL_NORM

EN_INT_SIGNAL_ERR

ACMD_ERR_STATUS

BLOCK_SIZE

CAPABILITIES

CAPABILITIES_HI

MAX_CURRENT_CAP

FORCE_EVENT_ACMD_ERR_STATUS

FORCE_EVENT_ERR_STATUS

BLOCK_COUNT

DEBUG_SEL

ARGUMENT1

TRANSFER_MODE

COMMAND

SLOT_INT_STATUS


RESPONSE0

Response 0 Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESPONSE0 RESPONSE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESPONSE0 RESPONSE1

RESPONSE0 : Response0
bits : 0 - 14 (15 bit)
access : read-only

RESPONSE1 : Response1
bits : 16 - 30 (15 bit)
access : read-only


RESPONSE2

Response 2 Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESPONSE2 RESPONSE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESPONSE2 RESPONSE3

RESPONSE2 : Response2
bits : 0 - 14 (15 bit)
access : read-only

RESPONSE3 : Response3
bits : 16 - 30 (15 bit)
access : read-only


RESPONSE4

Response 4 Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESPONSE4 RESPONSE4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESPONSE4 RESPONSE5

RESPONSE4 : Response4
bits : 0 - 14 (15 bit)
access : read-only

RESPONSE5 : Response5
bits : 16 - 30 (15 bit)
access : read-only


RESPONSE6

Response 6 Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESPONSE6 RESPONSE6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESPONSE6 RESPONSE7

RESPONSE6 : Response6
bits : 0 - 14 (15 bit)
access : read-only

RESPONSE7 : Response7
bits : 16 - 30 (15 bit)
access : read-only


DATA_BUFFER

Data Buffer Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA_BUFFER DATA_BUFFER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA_BUFFER

DATA_BUFFER : Data Buffer
bits : 0 - 30 (31 bit)
access : read-write


PRESENT_STATE

Present State Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRESENT_STATE PRESENT_STATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMAND_INHIBIT_CMD COMMAND_INHIBIT_DAT DAT_LINE_ACTIVE WRITE_TRANSFER_ACTIVE READ_TRANSFER_ACTIVE BUFFER_WRITE_ENABLE BUFFER_READ_ENABLE CARD_INSERTED CARD_STATE_STABLE CARD_DETECT_PIN_LEVEL WRITE_PROTECT_PIN_LEVEL DAT_3_0_PIN_LEVEL CMD_LINE_LEVEL DAT_7_4_PIN_LEVEL

COMMAND_INHIBIT_CMD : Command Inhibit (CMD)
bits : 0 - -1 (0 bit)
access : read-only

COMMAND_INHIBIT_DAT : Command Inhibit (DAT)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : value1

Can issue command which uses the DAT line

#1 : value2

Cannot issue command which uses the DAT line

End of enumeration elements list.

DAT_LINE_ACTIVE : DAT Line Active
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : value1

DAT line inactive

#1 : value2

DAT line active

End of enumeration elements list.

WRITE_TRANSFER_ACTIVE : Write Transfer Active
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : value1

No valid data

#1 : value2

Transferring data

End of enumeration elements list.

READ_TRANSFER_ACTIVE : Read Transfer Active
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

#0 : value1

No valid data

#1 : value2

Transferring data

End of enumeration elements list.

BUFFER_WRITE_ENABLE : Buffer Write Enable
bits : 10 - 9 (0 bit)
access : read-only

Enumeration:

#0 : value1

Write Disable

#1 : value2

Write Enable.

End of enumeration elements list.

BUFFER_READ_ENABLE : Buffer Read Enable
bits : 11 - 10 (0 bit)
access : read-only

Enumeration:

#0 : value1

Read Disable

#1 : value2

Read Enable.

End of enumeration elements list.

CARD_INSERTED : Card Inserted
bits : 16 - 15 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset or Debouncing or No Card

#1 : value2

Card Inserted

End of enumeration elements list.

CARD_STATE_STABLE : Card State Stable
bits : 17 - 16 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset of Debouncing

#1 : value2

No Card or Inserted

End of enumeration elements list.

CARD_DETECT_PIN_LEVEL : Card Detect Pin Level
bits : 18 - 17 (0 bit)
access : read-only

Enumeration:

#0 : value1

No Card present (SDCD = 1)

#1 : value2

Card present (SDCD = 0)

End of enumeration elements list.

WRITE_PROTECT_PIN_LEVEL : Write Protect Switch Pin Level
bits : 19 - 18 (0 bit)
access : read-only

Enumeration:

#0 : value1

Write protected (SDWP = 1)

#1 : value2

Write enabled (SDWP = 0)

End of enumeration elements list.

DAT_3_0_PIN_LEVEL : Line Signal Level
bits : 20 - 22 (3 bit)
access : read-only

CMD_LINE_LEVEL : CMD Line Signal Level
bits : 24 - 23 (0 bit)
access : read-only

DAT_7_4_PIN_LEVEL : Line Signal Level
bits : 25 - 27 (3 bit)
access : read-only


HOST_CTRL

Host Control Register
address_offset : 0x28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_CTRL HOST_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LED_CTRL DATA_TX_WIDTH HIGH_SPEED_EN SD_8BIT_MODE CARD_DETECT_TEST_LEVEL CARD_DET_SIGNAL_DETECT

LED_CTRL : LED Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

LED off

#1 : value2

LED on

End of enumeration elements list.

DATA_TX_WIDTH : Data Transfer Width (SD1 or SD4)
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

1 bit mode

#1 : value2

4-bit mode

End of enumeration elements list.

HIGH_SPEED_EN : High Speed Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Normal Speed Mode

#1 : value2

High Speed Mode

End of enumeration elements list.

SD_8BIT_MODE : Extended Data Transfer Width
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

Bus Width is selected by Data Transfer Width

#1 : value2

8-bit Bus Width

End of enumeration elements list.

CARD_DETECT_TEST_LEVEL : Card Detect Test Level
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

No Card

#1 : value2

Card Inserted

End of enumeration elements list.

CARD_DET_SIGNAL_DETECT : Card detect signal detetction
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

SDCD is selected (for normal use)

#1 : value2

The card detect test level is selected

End of enumeration elements list.


POWER_CTRL

Power Control Register
address_offset : 0x29 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POWER_CTRL POWER_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SD_BUS_POWER SD_BUS_VOLTAGE_SEL HARDWARE_RESET

SD_BUS_POWER : SD Bus Power
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Power off

#1 : value2

Power on

End of enumeration elements list.

SD_BUS_VOLTAGE_SEL : SD Bus Voltage Select
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#111 : value1

3.3V (Flattop.)

End of enumeration elements list.

HARDWARE_RESET : Hardware reset
bits : 4 - 3 (0 bit)
access : read-write


BLOCK_GAP_CTRL

Block Gap Control Register
address_offset : 0x2A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLOCK_GAP_CTRL BLOCK_GAP_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 STOP_AT_BLOCK_GAP CONTINUE_REQ READ_WAIT_CTRL INT_AT_BLOCK_GAP

STOP_AT_BLOCK_GAP : Stop At Block Gap Request
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Transfer

#1 : value2

Stop

End of enumeration elements list.

CONTINUE_REQ : Continue Request
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Ignored

#1 : value2

Restart

End of enumeration elements list.

READ_WAIT_CTRL : Read Wait Control
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Disable Read Wait Control

#1 : value2

Enable Read Wait Control

End of enumeration elements list.

INT_AT_BLOCK_GAP : Interrupt At Block Gap
bits : 3 - 2 (0 bit)
access : read-write


WAKEUP_CTRL

Wake-up Control Register
address_offset : 0x2B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAKEUP_CTRL WAKEUP_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 WAKEUP_EVENT_EN_INT WAKEUP_EVENT_EN_INS WAKEUP_EVENT_EN_REM

WAKEUP_EVENT_EN_INT : Wakeup Event Enable On Card Interrupt
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Disable

#1 : value2

Enable

End of enumeration elements list.

WAKEUP_EVENT_EN_INS : Wakeup Event Enable On SD Card Insertion
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Disable

#1 : value2

Enable

End of enumeration elements list.

WAKEUP_EVENT_EN_REM : Wakeup Event Enable On SD Card Removal
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Disable

#1 : value2

Enable

End of enumeration elements list.


CLOCK_CTRL

Clock Control Register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLOCK_CTRL CLOCK_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTERNAL_CLOCK_EN INTERNAL_CLOCK_STABLE SDCLOCK_EN SDCLK_FREQ_SEL

INTERNAL_CLOCK_EN : Internal Clock Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Stop

#1 : value2

Oscillate

End of enumeration elements list.

INTERNAL_CLOCK_STABLE : Internal Clock Stable
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : value1

Not Ready

#1 : value2

Ready

End of enumeration elements list.

SDCLOCK_EN : SD Clock Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Disable

#1 : value2

Enable

End of enumeration elements list.

SDCLK_FREQ_SEL : SDCLK Frequency Select
bits : 8 - 14 (7 bit)
access : read-write

Enumeration:

0x00 : value1

base clock(10MHz-63MHz)

0x01 : value2

base clock divided by 2

0x10 : value3

base clock divided by 32

0x02 : value4

base clock divided by 4

0x04 : value5

base clock divided by 8

0x08 : value6

base clock divided by 16

0x20 : value7

base clock divided by 64

0x40 : value8

base clock divided by 128

0x80 : value9

base clock divided by 256

End of enumeration elements list.


TIMEOUT_CTRL

Timeout Control Register
address_offset : 0x2E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMEOUT_CTRL TIMEOUT_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DAT_TIMEOUT_CNT_VAL

DAT_TIMEOUT_CNT_VAL : Data Timeout Counter Value
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : value1

TMCLK * 2^13

#0001 : value2

TMCLK * 2^14

#1110 : value3

TMCLK * 2^27

End of enumeration elements list.


SW_RESET

Software Reset Register
address_offset : 0x2F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_RESET SW_RESET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SW_RST_ALL SW_RST_CMD_LINE SW_RST_DAT_LINE

SW_RST_ALL : Software Reset for All
bits : 0 - -1 (0 bit)
access : read-write

SW_RST_CMD_LINE : Software Reset for CMD Line
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Work

#1 : value2

Reset

End of enumeration elements list.

SW_RST_DAT_LINE : Software Reset for DAT Line
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Work

#1 : value2

Reset

End of enumeration elements list.


INT_STATUS_NORM

Normal Interrupt Status Register
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_STATUS_NORM INT_STATUS_NORM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_COMPLETE TX_COMPLETE BLOCK_GAP_EVENT BUFF_WRITE_READY BUFF_READ_READY CARD_INS CARD_REMOVAL CARD_INT ERR_INT

CMD_COMPLETE : Command Complete
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

No Command Complete

#1 : value2

Command Complete

End of enumeration elements list.

TX_COMPLETE : Transfer Complete
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

No Data Transfer Complete

#1 : value2

Data Transfer Complete

End of enumeration elements list.

BLOCK_GAP_EVENT : Block Gap Event
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

No Block Gap Event

#1 : value2

Transaction stopped at Block Gap

End of enumeration elements list.

BUFF_WRITE_READY : Buffer Write Ready
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

Not Ready to Write Buffer.

#1 : value2

Ready to Write Buffer.

End of enumeration elements list.

BUFF_READ_READY : Buffer Read Ready
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

Not Ready to read Buffer.

#1 : value2

Ready to read Buffer.

End of enumeration elements list.

CARD_INS : Card Insertion
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

Card State Stable or Debouncing

#1 : value2

Card Inserted

End of enumeration elements list.

CARD_REMOVAL : Card Removal
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

Card State Stable or Debouncing

#1 : value2

Card Removed

End of enumeration elements list.

CARD_INT : Card Interrupt
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : value1

No Card Interrupt

#1 : value2

Generate Card Interrupt

End of enumeration elements list.

ERR_INT : Error Interrupt
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : value1

No Error.

#1 : value2

Error.

End of enumeration elements list.


INT_STATUS_ERR

Error Interrupt Status Register
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_STATUS_ERR INT_STATUS_ERR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_TIMEOUT_ERR CMD_CRC_ERR CMD_END_BIT_ERR CMD_IND_ERR DATA_TIMEOUT_ERR DATA_CRC_ERR DATA_END_BIT_ERR CURRENT_LIMIT_ERR ACMD_ERR CEATA_ERR

CMD_TIMEOUT_ERR : Command Timeout Error
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

No Error

#1 : value2

Timeout

End of enumeration elements list.

CMD_CRC_ERR : Command CRC Error
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

No Error

#1 : value2

CRC Error Generated

End of enumeration elements list.

CMD_END_BIT_ERR : Command End Bit Error
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

No Error

#1 : value2

End Bit Error Generated

End of enumeration elements list.

CMD_IND_ERR : Command Index Error
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

No Error

#1 : value2

Error

End of enumeration elements list.

DATA_TIMEOUT_ERR : Data Timeout Error
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

No Error

#1 : value2

Timeout

End of enumeration elements list.

DATA_CRC_ERR : Data CRC Error
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

No Error

#1 : value2

Error

End of enumeration elements list.

DATA_END_BIT_ERR : Data End Bit Error
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

No Error

#1 : value2

Error

End of enumeration elements list.

CURRENT_LIMIT_ERR : Current Limit Error
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

No Error

#1 : value2

Power Fail

End of enumeration elements list.

ACMD_ERR : Auto CMD Error
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : value1

No Error

#1 : value2

Error

End of enumeration elements list.

CEATA_ERR : Ceata Error Status
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : value1

no error

#1 : value2

error

End of enumeration elements list.


EN_INT_STATUS_NORM

Normal Interrupt Status Enable Register
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN_INT_STATUS_NORM EN_INT_STATUS_NORM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_COMPLETE_EN TX_COMPLETE_EN BLOCK_GAP_EVENT_EN BUFF_WRITE_READY_EN BUFF_READ_READY_EN CARD_INS_EN CARD_REMOVAL_EN CARD_INT_EN FIXED_TO_0

CMD_COMPLETE_EN : Command Complete Status Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

TX_COMPLETE_EN : Transfer Complete Status Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

BLOCK_GAP_EVENT_EN : Block Gap Event Status Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

BUFF_WRITE_READY_EN : Buffer Write Ready Status Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

BUFF_READ_READY_EN : Buffer Read Ready Status Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

CARD_INS_EN : Card Insertion Status Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

CARD_REMOVAL_EN : Card Removal Status Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

CARD_INT_EN : Card Interrupt Status Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

FIXED_TO_0 : Fixed to 0
bits : 15 - 14 (0 bit)
access : read-only


EN_INT_STATUS_ERR

Error Interrupt Status Enable Register
address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN_INT_STATUS_ERR EN_INT_STATUS_ERR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_TIMEOUT_ERR_EN CMD_CRC_ERR_EN CMD_END_BIT_ERR_EN CMD_IND_ERR_EN DATA_TIMEOUT_ERR_EN DATA_CRC_ERR_EN DATA_END_BIT_ERR_EN CURRENT_LIMIT_ERR_EN ACMD_ERR_EN TARGET_RESP_ERR_EN CEATA_ERR_EN

CMD_TIMEOUT_ERR_EN : Command Timeout Error Status Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

CMD_CRC_ERR_EN : Command CRC Error Status Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

CMD_END_BIT_ERR_EN : Command End Bit Error Status Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

CMD_IND_ERR_EN : Command Index Error Status Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

DATA_TIMEOUT_ERR_EN : Data Timeout Error Status Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

DATA_CRC_ERR_EN : Data CRC Error Status Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

DATA_END_BIT_ERR_EN : Data End Bit Error Status Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

CURRENT_LIMIT_ERR_EN : Current Limit Error Status Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

ACMD_ERR_EN : Auto CMD12 Error Status Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

TARGET_RESP_ERR_EN : Target Response Error Status Enable
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

CEATA_ERR_EN : Ceata Error Status Enable
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.


EN_INT_SIGNAL_NORM

Normal Interrupt Signal Enable Register
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN_INT_SIGNAL_NORM EN_INT_SIGNAL_NORM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_COMPLETE_EN TX_COMPLETE_EN BLOCK_GAP_EVENT_EN BUFF_WRITE_READY_EN BUFF_READ_READY_EN CARD_INS_EN CARD_REMOVAL_EN CARD_INT_EN FIXED_TO_0

CMD_COMPLETE_EN : Command Complete Signal Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

TX_COMPLETE_EN : Transfer Complete Signal Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

BLOCK_GAP_EVENT_EN : Block Gap Event Signal Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

BUFF_WRITE_READY_EN : Buffer Write Ready Signal Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

BUFF_READ_READY_EN : Buffer Read Ready Signal Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

CARD_INS_EN : Card Insertion Signal Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

CARD_REMOVAL_EN : Card Removal Signal Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

CARD_INT_EN : Card Interrupt Signal Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

FIXED_TO_0 : Fixed to 0
bits : 15 - 14 (0 bit)
access : read-only


EN_INT_SIGNAL_ERR

Error Interrupt Signal Enable Register
address_offset : 0x3A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN_INT_SIGNAL_ERR EN_INT_SIGNAL_ERR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_TIMEOUT_ERR_EN CMD_CRC_ERR_EN CMD_END_BIT_ERR_EN CMD_IND_ERR_EN DATA_TIMEOUT_ERR_EN DATA_CRC_ERR_EN DATA_END_BIT_ERR_EN CURRENT_LIMIT_ERR_EN ACMD_ERR_EN TARGET_RESP_ERR_EN CEATA_ERR_EN

CMD_TIMEOUT_ERR_EN : Command Timeout Error Signal Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

CMD_CRC_ERR_EN : Command CRC Error Signal Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

CMD_END_BIT_ERR_EN : Command End Bit Error Signal Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

CMD_IND_ERR_EN : Command Index Error Signal Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

DATA_TIMEOUT_ERR_EN : Data Timeout Error Signal Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

DATA_CRC_ERR_EN : Data CRC Error Signal Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

DATA_END_BIT_ERR_EN : Data End Bit Error Signal Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

CURRENT_LIMIT_ERR_EN : Current Limit Error Signal Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

ACMD_ERR_EN : Auto CMD12 Error Signal Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

TARGET_RESP_ERR_EN : Target Response Error Signal Enable
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.

CEATA_ERR_EN : Ceata Error Signal Enable
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : value1

Masked

#1 : value2

Enabled

End of enumeration elements list.


ACMD_ERR_STATUS

Auto CMD Error Status Register
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACMD_ERR_STATUS ACMD_ERR_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACMD12_NOT_EXEC_ERR ACMD_TIMEOUT_ERR ACMD_CRC_ERR ACMD_END_BIT_ERR ACMD_IND_ERR CMD_NOT_ISSUED_BY_ACMD12_ERR

ACMD12_NOT_EXEC_ERR : Auto CMD12 Not Executed
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : value1

Executed

#1 : value2

Not Executed

End of enumeration elements list.

ACMD_TIMEOUT_ERR : Auto CMD Timeout Error
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : value1

No Error

#1 : value2

Timeout

End of enumeration elements list.

ACMD_CRC_ERR : Auto CMD CRC Error
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : value1

No Error

#1 : value2

CRC Error Generated

End of enumeration elements list.

ACMD_END_BIT_ERR : Auto CMD End Bit Error
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : value1

No Error

#1 : value2

End Bit Error Generated

End of enumeration elements list.

ACMD_IND_ERR : Auto CMD Index Error
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : value1

No Error

#1 : value2

Error

End of enumeration elements list.

CMD_NOT_ISSUED_BY_ACMD12_ERR : Command Not Issued By Auto CMD12 Error
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : value1

No Error

#1 : value2

Not Issued

End of enumeration elements list.


BLOCK_SIZE

Block Size Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLOCK_SIZE BLOCK_SIZE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_BLOCK_SIZE TX_BLOCK_SIZE_12

TX_BLOCK_SIZE : Transfer Block Size
bits : 0 - 10 (11 bit)
access : read-write

TX_BLOCK_SIZE_12 : Transfer Block Size 12th bit.
bits : 15 - 14 (0 bit)
access : read-write


CAPABILITIES

Capabilities Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPABILITIES CAPABILITIES read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMEOUT_CLOCK_FREQ TIMEOUT_CLOCK_UNIT BASE_SD_CLOCK_FREQ MAX_BLOCK_LENGTH EXT_MEDIA_BUS_SUPPORT ADMA2_SUPPORT HIGH_SPEED_SUPPORT SDMA_SUPPORT SUSPEND_RESUME_SUPPORT VOLTAGE_SUPPORT_3_3V VOLTAGE_SUPPORT_3V VOLTAGE_SUPPORT_1_8V SYSBUS_64_SUPPORT ASYNC_INT_SUPPORT SLOT_TYPE

TIMEOUT_CLOCK_FREQ : Timeout Clock Frequency
bits : 0 - 4 (5 bit)
access : read-only

Enumeration:

#110000 : value1

48 MHz

End of enumeration elements list.

TIMEOUT_CLOCK_UNIT : Timeout Clock Unit
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#1 : value1

MHz

End of enumeration elements list.

BASE_SD_CLOCK_FREQ : Base Clock Frequency for SD Clock
bits : 8 - 14 (7 bit)
access : read-only

Enumeration:

0x30 : value1

48 MHz

End of enumeration elements list.

MAX_BLOCK_LENGTH : Max Block Length
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

#00 : value1

512 byte

End of enumeration elements list.

EXT_MEDIA_BUS_SUPPORT : Extended Media Bus Support
bits : 18 - 17 (0 bit)
access : read-only

Enumeration:

#0 : value1

Extended Media Bus not supported

End of enumeration elements list.

ADMA2_SUPPORT : ADMA2 Support
bits : 19 - 18 (0 bit)
access : read-only

Enumeration:

#0 : value1

ADMA not supported

End of enumeration elements list.

HIGH_SPEED_SUPPORT : High Speed Support
bits : 21 - 20 (0 bit)
access : read-only

Enumeration:

#1 : value1

High Speed supported

End of enumeration elements list.

SDMA_SUPPORT : SDMA Support
bits : 22 - 21 (0 bit)
access : read-only

Enumeration:

#0 : value1

SDMA not supported

End of enumeration elements list.

SUSPEND_RESUME_SUPPORT : Suspend / Resume Support
bits : 23 - 22 (0 bit)
access : read-only

Enumeration:

#1 : value1

Supported

End of enumeration elements list.

VOLTAGE_SUPPORT_3_3V : Voltage Support 3.3V
bits : 24 - 23 (0 bit)
access : read-only

Enumeration:

#1 : value1

3.3V supported

End of enumeration elements list.

VOLTAGE_SUPPORT_3V : Voltage Support 3.0V
bits : 25 - 24 (0 bit)
access : read-only

Enumeration:

#0 : value1

3.0V not supported

End of enumeration elements list.

VOLTAGE_SUPPORT_1_8V : Voltage Support 1.8V
bits : 26 - 25 (0 bit)
access : read-only

Enumeration:

#0 : value1

1.8V not supported

End of enumeration elements list.

SYSBUS_64_SUPPORT : 64-bit System Bus Support
bits : 28 - 27 (0 bit)
access : read-only

Enumeration:

#0 : value1

Does not support 64-bit system address

End of enumeration elements list.

ASYNC_INT_SUPPORT : Asynchronous Interrupt Support
bits : 29 - 28 (0 bit)
access : read-only

Enumeration:

#0 : value1

Asynchronous Interrupt not supported

End of enumeration elements list.

SLOT_TYPE : Slot Type
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

#00 : value1

Removable Card Slot

End of enumeration elements list.


CAPABILITIES_HI

Capabilities Register High
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPABILITIES_HI CAPABILITIES_HI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDR50_SUPPORT SDR104_SUPPORT DDR50_SUPPORT DRV_A_SUPPORT DRV_C_SUPPORT DRV_D_SUPPORT TIM_CNT_RETUNE USE_TUNING_SDR50 RE_TUNING_MODES CLK_MULT

SDR50_SUPPORT : SDR50 Support
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : value1

SDR50 is not supported

End of enumeration elements list.

SDR104_SUPPORT : SDR104 Support
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : value1

SDR104 is not supported

End of enumeration elements list.

DDR50_SUPPORT : DDR50 Support
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : value1

DDR50 is not supported

End of enumeration elements list.

DRV_A_SUPPORT : Driver Type A Support
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : value1

Driver Type A is not supported

End of enumeration elements list.

DRV_C_SUPPORT : Driver Type C Support
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : value1

Driver Type C is not supported

End of enumeration elements list.

DRV_D_SUPPORT : Driver Type D Support
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : value1

Driver Type D is not supported

End of enumeration elements list.

TIM_CNT_RETUNE : Timer count for Re-Tuning
bits : 8 - 10 (3 bit)
access : read-only

Enumeration:

0x0 : value1

Get information via other source

End of enumeration elements list.

USE_TUNING_SDR50 : Use Tuning for SDR50
bits : 13 - 12 (0 bit)
access : read-only

Enumeration:

#0 : value1

SDR50 does not require tuning

End of enumeration elements list.

RE_TUNING_MODES : Re-tuning modes
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

#00 : value1

Mode 1

End of enumeration elements list.

CLK_MULT : Clock Multiplier
bits : 16 - 22 (7 bit)
access : read-only

Enumeration:

0x00 : value1

Clock Multiplier not supported

End of enumeration elements list.


MAX_CURRENT_CAP

Maximum Current Capabilities Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAX_CURRENT_CAP MAX_CURRENT_CAP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAX_CURRENT_FOR_3_3V

MAX_CURRENT_FOR_3_3V : Maximum Current for 3.3V
bits : 0 - 6 (7 bit)
access : read-only


FORCE_EVENT_ACMD_ERR_STATUS

Force Event Register for Auto CMD Error Status
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FORCE_EVENT_ACMD_ERR_STATUS FORCE_EVENT_ACMD_ERR_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FE_ACMD_NOT_EXEC FE_ACMD_TIMEOUT_ERR FE_ACMD_CRC_ERR FE_ACMD_END_BIT_ERR FE_ACMD_IND_ERR FE_CMD_NOT_ISSUED_ACMD12_ERR

FE_ACMD_NOT_EXEC : Force Event for Auto CMD12 NOT Executed
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No interrupt

#1 : value2

Interrupt is generated

End of enumeration elements list.

FE_ACMD_TIMEOUT_ERR : Force Event for Auto CMD timeout Error
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : value1

No interrupt

#1 : value2

Interrupt is generated

End of enumeration elements list.

FE_ACMD_CRC_ERR : Force Event for Auto CMD CRC Error
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No interrupt

#1 : value2

Interrupt is generated

End of enumeration elements list.

FE_ACMD_END_BIT_ERR : Force Event for Auto CMD End bit Error
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : value1

No interrupt

#1 : value2

Interrupt is generated

End of enumeration elements list.

FE_ACMD_IND_ERR : Force Event for Auto CMD Index Error
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : value1

No interrupt

#1 : value2

Interrupt is generated

End of enumeration elements list.

FE_CMD_NOT_ISSUED_ACMD12_ERR : Force Event for CMD not issued by Auto CMD12 Error
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : value1

No interrupt

#1 : value2

Interrupt is generated

End of enumeration elements list.


FORCE_EVENT_ERR_STATUS

Force Event Register for Error Interrupt Status
address_offset : 0x52 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FORCE_EVENT_ERR_STATUS FORCE_EVENT_ERR_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FE_CMD_TIMEOUT_ERR FE_CMD_CRC_ERR FE_CMD_END_BIT_ERR FE_CMD_IND_ERR FE_DATA_TIMEOUT_ERR FE_DATA_CRC_ERR FE_DATA_END_BIT_ERR FE_CURRENT_LIMIT_ERR FE_ACMD12_ERR FE_TARGET_RESPONSE_ERR FE_CEATA_ERR

FE_CMD_TIMEOUT_ERR : Force Event for Command Timeout Error
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No interrupt

#1 : value2

Interrupt is generated

End of enumeration elements list.

FE_CMD_CRC_ERR : Force Event for Command CRC Error
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : value1

No interrupt

#1 : value2

Interrupt is generated

End of enumeration elements list.

FE_CMD_END_BIT_ERR : Force Event for Command End Bit Error
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No interrupt

#1 : value2

Interrupt is generated

End of enumeration elements list.

FE_CMD_IND_ERR : Force Event for Command Index Error
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : value1

No interrupt

#1 : value2

Interrupt is generated

End of enumeration elements list.

FE_DATA_TIMEOUT_ERR : Force Event for Data Timeout Error
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : value1

No interrupt

#1 : value2

Interrupt is generated

End of enumeration elements list.

FE_DATA_CRC_ERR : Force Event for Data CRC Error
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

#0 : value1

No interrupt

#1 : value2

Interrupt is generated

End of enumeration elements list.

FE_DATA_END_BIT_ERR : Force Event for Data End Bit Error
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

#0 : value1

No interrupt

#1 : value2

Interrupt is generated

End of enumeration elements list.

FE_CURRENT_LIMIT_ERR : Force Event for Current Limit Error
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : value1

No interrupt

#1 : value2

Interrupt is generated

End of enumeration elements list.

FE_ACMD12_ERR : Force Event for Auto CMD Error
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

No interrupt

#1 : value2

Interrupt is generated

End of enumeration elements list.

FE_TARGET_RESPONSE_ERR : Force event for Target Response Error
bits : 12 - 11 (0 bit)
access : write-only

Enumeration:

#0 : value1

No interrupt

#1 : value2

Interrupt is generated

End of enumeration elements list.

FE_CEATA_ERR : Force Event for Ceata Error
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : value1

No interrupt

#1 : value2

Interrupt is generated

End of enumeration elements list.


BLOCK_COUNT

Block Count Register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLOCK_COUNT BLOCK_COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLOCK_COUNT

BLOCK_COUNT : Blocks Count for Current Transfer
bits : 0 - 14 (15 bit)
access : read-write


DEBUG_SEL

Debug Selection Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG_SEL DEBUG_SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEBUG_SEL

DEBUG_SEL : Debug_sel
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : value1

receiver module and fifo_ctrl module signals are probed out

#1 : value2

cmd register, Interrupt status, transmitter module and clk sdcard signals are probed out.

End of enumeration elements list.


ARGUMENT1

Argument1 Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARGUMENT1 ARGUMENT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARGUMENT1

ARGUMENT1 : Command Argument
bits : 0 - 30 (31 bit)
access : read-write


TRANSFER_MODE

Transfer Mode Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRANSFER_MODE TRANSFER_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLOCK_COUNT_EN ACMD_EN TX_DIR_SELECT MULTI_BLOCK_SELECT CMD_COMP_ATA

BLOCK_COUNT_EN : Block Count Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Disable

#1 : value2

Enable

End of enumeration elements list.

ACMD_EN : Auto CMD Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : value1

Auto Command Disabled

#01 : value2

Auto CMD12 Enable

End of enumeration elements list.

TX_DIR_SELECT : Data Transfer Direction Select
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

Write (Host to Card)

#1 : value2

Read (Card to Host)

End of enumeration elements list.

MULTI_BLOCK_SELECT : Multi / Single Block Select
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

Single Block

#1 : value2

Multiple Block

End of enumeration elements list.

CMD_COMP_ATA : Command Completion Signal Enable for CE-ATA Device
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#1 : value1

Device will send command completion Signal

#0 : value2

Device will not send command completion Signal

End of enumeration elements list.


COMMAND

Command Register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMMAND COMMAND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESP_TYPE_SELECT CMD_CRC_CHECK_EN CMD_IND_CHECK_EN DATA_PRESENT_SELECT CMD_TYPE CMD_IND

RESP_TYPE_SELECT : Response Type Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : value1

No Response

#01 : value2

Response length 136

#10 : value3

Response length 48

#11 : value4

Response length 48 check Busy after response

End of enumeration elements list.

CMD_CRC_CHECK_EN : Command CRC Check Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

Disable

#1 : value2

Enable

End of enumeration elements list.

CMD_IND_CHECK_EN : Command Index Check Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

Disable

#1 : value2

Enable

End of enumeration elements list.

DATA_PRESENT_SELECT : Data Present Select
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

No Data Present

#1 : value2

Data Present

End of enumeration elements list.

CMD_TYPE : Command Type
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : value1

Normal

#01 : value2

Suspend

#10 : value3

Resume

#11 : value4

Abort

End of enumeration elements list.

CMD_IND : Command Index
bits : 8 - 12 (5 bit)
access : read-write


SLOT_INT_STATUS

Slot Interrupt Status Register
address_offset : 0xFC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLOT_INT_STATUS SLOT_INT_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_INT_STATUS

SLOT_INT_STATUS : Interrupt Signal for Card Slot
bits : 0 - 6 (7 bit)
access : read-only

Enumeration:

0x00 : value1

Slot 1

End of enumeration elements list.



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