Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10000 byte (0x0)
mem_usage : registers
protection : not protected
Type of EtherCAT Controller
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Type : Type of EtherCAT controller
bits : 0 - 6 (7 bit)
access : read-only
Revision of EtherCAT Controller
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Revision : Revision of EtherCAT controller
bits : 0 - 6 (7 bit)
access : read-only
Configured Station Address
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NODE_ADDR : Address used for node addressing (FPxx commands)
bits : 0 - 14 (15 bit)
access : read-only
ESC DL Control
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FR : Forwarding rule
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
EtherCAT frames are processed, Non-EtherCAT frames are forwarded without processing
#1 : value2
EtherCAT frames are processed, Non- EtherCAT frames are destroyed
End of enumeration elements list.
TEMP : Temporary use of settings in LP1-LP3
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : value1
permanent use
#1 : value2
use for about 1 second, then revert to previous settings
End of enumeration elements list.
LP0 : Loop Port 0
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#00 : value1
Auto
#01 : value2
Auto Close
#10 : value3
Open
#11 : value4
Closed
End of enumeration elements list.
LP1 : Loop Port 1
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#00 : value1
Auto
#01 : value2
Auto Close
#10 : value3
Open
#11 : value4
Closed
End of enumeration elements list.
LP2 : Loop Port 2
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#00 : value1
Auto
#01 : value2
Auto Close
#10 : value3
Open
#11 : value4
Closed
End of enumeration elements list.
LP3 : Loop Port 3
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#00 : value1
Auto
#01 : value2
Auto Close
#10 : value3
Open
#11 : value4
Closed
End of enumeration elements list.
RX_FIFO_SIZE : RX FIFO Size
bits : 16 - 17 (2 bit)
access : read-only
Enumeration:
0 : value1
-40 ns (-80 ns)
1 : value2
-40 ns (-80 ns)
2 : value3
-40 ns
3 : value4
-40 ns
4 : value5
no change
5 : value6
no change
6 : value7
no change
7 : value8
default
End of enumeration elements list.
LJ : EBUS Low Jitter
bits : 19 - 18 (0 bit)
access : read-only
Enumeration:
#0 : value1
Normal jitter
#1 : value2
Reduced jitter
End of enumeration elements list.
RLD_ST : EBUS remote link down signaling time
bits : 22 - 21 (0 bit)
access : read-only
Enumeration:
#0 : value1
Default (~660 ms)
#1 : value2
Reduced (~80 us)
End of enumeration elements list.
S_ALIAS : Station alias
bits : 24 - 23 (0 bit)
access : read-only
Enumeration:
#0 : value1
Ignore Station Alias
#1 : value2
Alias can be used for all configured address command types (FPRD,FPWR,...)
End of enumeration elements list.
Physical Read/Write Offset
address_offset : 0x108 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSET : Offset of R/W Commands (FPRW, APRW) between Read address and Write address
bits : 0 - 14 (15 bit)
access : read-only
ESC DL Status
address_offset : 0x110 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDI_EEPROM : PDI operational/EEPROM loaded correctly
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
EEPROM not loaded, PDI not operational (no access to Process Data RAM)
#1 : value2
EEPROM loaded correctly, PDI operational (access to Process Data RAM)
End of enumeration elements list.
PDI_WDT_S : PDI Watchdog Status
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : value1
Watchdog expired
#1 : value2
Watchdog reloaded
End of enumeration elements list.
ELD : Enhanced Link detection
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Deactivated for all ports
#1 : value2
Activated for at least one port
End of enumeration elements list.
LINK_P0 : Physical link on Port 0
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : value1
No link
#1 : value2
Link detected
End of enumeration elements list.
LINK_P1 : Physical link on Port 1
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : value1
No link
#1 : value2
Link detected
End of enumeration elements list.
LINK_P2 : Physical link on Port 2
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : value1
No link
#1 : value2
Link detected
End of enumeration elements list.
LINK_P3 : Physical link on Port 3
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : value1
No link
#1 : value2
Link detected
End of enumeration elements list.
LP0 : Loop Port 0
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : value1
Open
#1 : value2
Closed
End of enumeration elements list.
COM_P0 : Communication on Port 0
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : value1
No stable communication
#1 : value2
Communication established
End of enumeration elements list.
LP1 : Loop Port 1
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
#0 : value1
Open
#1 : value2
Closed
End of enumeration elements list.
COM_P1 : Communication on Port 1
bits : 11 - 10 (0 bit)
access : read-only
Enumeration:
#0 : value1
No stable communication
#1 : value2
Communication established
End of enumeration elements list.
LP2 : Loop Port 2
bits : 12 - 11 (0 bit)
access : read-only
Enumeration:
#0 : value1
Open
#1 : value2
Closed
End of enumeration elements list.
COM_P2 : Communication on Port 2
bits : 13 - 12 (0 bit)
access : read-only
Enumeration:
#0 : value1
No stable communication
#1 : value2
Communication established
End of enumeration elements list.
LP3 : Loop Port 3
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : value1
Open
#1 : value2
Closed
End of enumeration elements list.
COM_P3 : Communication on Port 3
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : value1
No stable communication
#1 : value2
Communication established
End of enumeration elements list.
Configured Station Alias
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALIAS_ADDR : Alias Address used for node addressing(FPxx commands)
bits : 0 - 14 (15 bit)
access : read-write
AL Control
address_offset : 0x120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IST : Initiate State Transition of the Device StateMachine
bits : 0 - 2 (3 bit)
access : read-only
Enumeration:
0x1 : value1
Request Init State
0x2 : value2
Request Pre-Operational State
0x3 : value3
Request Bootstrap State
0x4 : value4
Request Safe-Operational State
0x8 : value5
Request Operational State
End of enumeration elements list.
EIA : Error Ind Ack
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : value1
No Ack of Error Ind in AL status register
#1 : value2
Ack of Error Ind in AL status register
End of enumeration elements list.
DID : Device Identification
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : value1
No request
#1 : value2
Device Identification request
End of enumeration elements list.
System Time read access
address_offset : 0x1220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : READMode
reset_Mask : 0x0
READ_ACCESS : Read access
bits : 0 - 30 (31 bit)
access : read-only
Local time of the beginning of a frame
address_offset : 0x1230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECEIVE_TIME_PU : Local time of the beginning of a frame
bits : 0 - 30 (31 bit)
access : read-only
Difference between local time and System Time
address_offset : 0x1240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DC_SYS_TIME_OFFSET : Difference between local time and System Time
bits : 0 - 30 (31 bit)
access : read-write
AL Status
address_offset : 0x130 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATE : Actual State of the Device State Machine
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x1 : value1
Init State
0x2 : value2
Pre-Operational State
0x3 : value3
Bootstrap State
0x4 : value4
Safe-Operational State
0x8 : value5
Operational State
End of enumeration elements list.
ERRI : Error Ind
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
Device is in State as requested or Flag cleared by command
#1 : value2
Device has not entered requested State or changed State as result of a local action
End of enumeration elements list.
DID : Device Identification
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
Device Identification not valid
#1 : value2
Device Identification loaded
End of enumeration elements list.
Start Time Cyclic Operation
address_offset : 0x1320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DC_CYC_START_TIME : Start Time Cyclic Operation
bits : 0 - 30 (31 bit)
access : read-write
System time of next SYNC1 pulse in ns
address_offset : 0x1330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DC_NEXT_SYNC1_PULSE : System time of next SYNC1 pulse in ns
bits : 0 - 30 (31 bit)
access : read-only
AL Status Code
address_offset : 0x134 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AL_S_CODE : AL Status Code
bits : 0 - 14 (15 bit)
access : read-write
Register captures System time at the positive edge of the Latch0 signal
address_offset : 0x1360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DC_LATCH0_TIME_POS : Captures System time at the positive edge of the Latch0 signal
bits : 0 - 30 (31 bit)
access : read-only
Register captures System time at the negative edge of the Latch0 signal
address_offset : 0x1370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DC_LATCH0_TIME_NEG : Captures System time at the negative edge of the Latch0 signal
bits : 0 - 30 (31 bit)
access : read-only
RUN LED Override
address_offset : 0x138 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LED_CODE : LED Code
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : value1
OFF - Init State
0x1 : value2
Flash - SafeOp)
0xD : value3
Blinking - PreOp
0xE : value4
Flickering - Bootstrap
0xF : value5
On - Operational
End of enumeration elements list.
EN_OVERR : Enable Override
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
Override disable
#1 : value2
Override enable
End of enumeration elements list.
Register captures System time at the positive edge of the Latch1 signal
address_offset : 0x1380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DC_LATCH1_TIME_POS : Captures System time at the positive edge of the Latch1 signal
bits : 0 - 30 (31 bit)
access : read-only
RUN ERR Override
address_offset : 0x139 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LED_CODE : LED Code
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : value1
OFF
0xD : value2
Blinking
0xE : value3
Flickering
0xF : value4
On
End of enumeration elements list.
EN_OVERR : Enable Override
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
Override disable
#1 : value2
Override enable
End of enumeration elements list.
Register captures System time at the negative edge of the Latch1 signal
address_offset : 0x1390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DC_LATCH1_TIME_NEG : Captures System time at the negative edge of the Latch1 signal
bits : 0 - 30 (31 bit)
access : read-only
PDI Control
address_offset : 0x140 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDI : On-chip bus clock
bits : 0 - 6 (7 bit)
access : read-only
Enumeration:
0x00 : value1
Interface deactivated (no PDI)
0x80 : value2
On-chip Bus
End of enumeration elements list.
ESC Configuration
address_offset : 0x141 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMUL : Device emulation (control of AL status)
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
AL status register has to be set by PDI
#1 : value2
AL status register will be set to value written to AL control register
End of enumeration elements list.
EHLD : Enhanced Link detection all ports
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : value1
disabled (if bits [7:4]=0)
#1 : value2
enabled at all ports (overrides bits [7:4])
End of enumeration elements list.
CLKS_OUT : Distributed Clocks SYNC Out Unit
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : value1
disabled (power saving)
#1 : value2
enabled
End of enumeration elements list.
CLKS_IN : Distributed Clocks Latch In Unit
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : value1
disabled (power saving)
#1 : value2
enabled
End of enumeration elements list.
EHLD_P0 : Enhanced Link port 0
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : value1
disabled (if bit 1 = 0)
#1 : value2
enabled
End of enumeration elements list.
EHLD_P1 : Enhanced Link port 1
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : value1
disabled (if bit 1 = 0)
#1 : value2
enabled
End of enumeration elements list.
EHLD_P2 : Enhanced Link port 2
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : value1
disabled (if bit 1 = 0)
#1 : value2
enabled
End of enumeration elements list.
EHLD_P3 : Enhanced Link port 3
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : value1
disabled (if bit 1 = 0)
#1 : value2
enabled
End of enumeration elements list.
PDI Control
address_offset : 0x150 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUS_CLK : On-chip bus clock
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
0x00 : value1
asyncronous
0x01 : value2
values 1-31 is used for synchronous multiplication factor (N*25Mhz)
End of enumeration elements list.
OC_BUS : On-chip bus
bits : 5 - 6 (2 bit)
access : read-only
Enumeration:
#000 : value1
Altera Avalon
#001 : value2
AXI
#010 : value3
Xilinx PLB v4.6
#100 : value4
Xilinx OPB
End of enumeration elements list.
Sync/Latch[1:0] PDI Configuration
address_offset : 0x151 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNC0_POL : SYNC0 output driver/polarity
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#00 : value1
Push-Pull active low
#01 : value2
Open Drain (active low)
#10 : value3
Push-Pull active high
#11 : value4
Open Source (active high)
End of enumeration elements list.
SL0_CNF : SYNC0/LATCH0 configuration
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : value1
LATCH0 Input
#1 : value2
SYNC0 Output
End of enumeration elements list.
S0_MAP : SYNC0 mapped to registerECAT0_AL_EVENT_REQ. ST_S0
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
SYNC1_POL : SYNC1 output driver/polarity
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#00 : value1
Push-Pull active low
#01 : value2
Open Drain (active low)
#10 : value3
Push-Pull active high
#11 : value4
Open Source (active high)
End of enumeration elements list.
SL1_CNF : SYNC1/LATCH1 configuration
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : value1
LATCH1 Input
#1 : value2
SYNC1 Output
End of enumeration elements list.
S1_MAP : SYNC1 mapped to registerECAT0_AL_EVENT_REQ. ST_S1
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
PDI Synchronous Microcontroller extended Configuration
address_offset : 0x152 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R_Pref : Read Prefetch Size
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0b00 : value1
4 cycles
0b01 : value2
1 cycle (typical)
0b10 : value3
2 cycles
End of enumeration elements list.
SUB_TYPE : On-chip Sub Type for AXI
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0b000 : value1
AXI3
0b001 : value2
AXI4
0b010 : value3
AXI4 Lite
End of enumeration elements list.
System Time read access
address_offset : 0x1B34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : READMode
reset_Mask : 0x0
READ_ACCESS : Read access
bits : 0 - 30 (31 bit)
access : read-only
Local time of the beginning of a frame
address_offset : 0x1B4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RECEIVE_TIME_PU : Local time of the beginning of a frame
bits : 0 - 30 (31 bit)
access : read-only
Difference between local time and System Time
address_offset : 0x1B64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DC_SYS_TIME_OFFSET : Difference between local time and System Time
bits : 0 - 30 (31 bit)
access : read-write
Start Time Cyclic Operation
address_offset : 0x1CB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DC_CYC_START_TIME : Start Time Cyclic Operation
bits : 0 - 30 (31 bit)
access : read-write
System time of next SYNC1 pulse in ns
address_offset : 0x1CCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DC_NEXT_SYNC1_PULSE : System time of next SYNC1 pulse in ns
bits : 0 - 30 (31 bit)
access : read-only
Register captures System time at the positive edge of the Latch0 signal
address_offset : 0x1D14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DC_LATCH0_TIME_POS : Captures System time at the positive edge of the Latch0 signal
bits : 0 - 30 (31 bit)
access : read-only
Register captures System time at the negative edge of the Latch0 signal
address_offset : 0x1D2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DC_LATCH0_TIME_NEG : Captures System time at the negative edge of the Latch0 signal
bits : 0 - 30 (31 bit)
access : read-only
Register captures System time at the positive edge of the Latch1 signal
address_offset : 0x1D44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DC_LATCH1_TIME_POS : Captures System time at the positive edge of the Latch1 signal
bits : 0 - 30 (31 bit)
access : read-only
Register captures System time at the negative edge of the Latch1 signal
address_offset : 0x1D5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DC_LATCH1_TIME_NEG : Captures System time at the negative edge of the Latch1 signal
bits : 0 - 30 (31 bit)
access : read-only
Build Version
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUILD : Actual build of EtherCAT controller
bits : 0 - 14 (15 bit)
access : read-only
Write Register Enable
address_offset : 0x20 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR_REG_EN : Write register protection enabled
bits : 0 - -1 (0 bit)
access : read-only
ECAT Event Mask
address_offset : 0x200 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DC_LE_MASK : DC Latch event
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Corresponding ECAT Event Request register bit is not mapped
0b1 : value2
Corresponding ECAT Event Request register bit is mapped
End of enumeration elements list.
DL_SE_MASK : DL Status event
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Corresponding ECAT Event Request register bit is not mapped
0b1 : value2
Corresponding ECAT Event Request register bit is mapped
End of enumeration elements list.
AL_SE_MASK : AL Status event
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Corresponding ECAT Event Request register bit is not mapped
0b1 : value2
Corresponding ECAT Event Request register bit is mapped
End of enumeration elements list.
MIR_0_MASK : Mirrors values of each SyncManager Status
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Corresponding ECAT Event Request register bit is not mapped
0b1 : value2
Corresponding ECAT Event Request register bit is mapped
End of enumeration elements list.
MIR_1_MASK : Mirrors values of each SyncManager Status
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Corresponding ECAT Event Request register bit is not mapped
0b1 : value2
Corresponding ECAT Event Request register bit is mapped
End of enumeration elements list.
MIR_2_MASK : Mirrors values of each SyncManager Status
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Corresponding ECAT Event Request register bit is not mapped
0b1 : value2
Corresponding ECAT Event Request register bit is mapped
End of enumeration elements list.
MIR_3_MASK : Mirrors values of each SyncManager Status
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Corresponding ECAT Event Request register bit is not mapped
0b1 : value2
Corresponding ECAT Event Request register bit is mapped
End of enumeration elements list.
MIR_4_MASK : Mirrors values of each SyncManager Status
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Corresponding ECAT Event Request register bit is not mapped
0b1 : value2
Corresponding ECAT Event Request register bit is mapped
End of enumeration elements list.
MIR_5_MASK : Mirrors values of each SyncManager Status
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Corresponding ECAT Event Request register bit is not mapped
0b1 : value2
Corresponding ECAT Event Request register bit is mapped
End of enumeration elements list.
MIR_6_MASK : Mirrors values of each SyncManager Status
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Corresponding ECAT Event Request register bit is not mapped
0b1 : value2
Corresponding ECAT Event Request register bit is mapped
End of enumeration elements list.
MIR_7_MASK : Mirrors values of each SyncManager Status
bits : 11 - 10 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Corresponding ECAT Event Request register bit is not mapped
0b1 : value2
Corresponding ECAT Event Request register bit is mapped
End of enumeration elements list.
PDI AL Event Mask
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AL_CE_MASK : AL Control event
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
DC_LE_MASK : DC Latch event
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
ST_S0_MASK : State of DC SYNC0
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
ST_S1_MASK : State of DC SYNC1
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
SM_A_MASK : SyncManager activation register changed
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
EEP_E_MASK : EEPROM Emulation
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
WP_D_MASK : Watchdog Process Data
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
SMI_0_MASK : SyncManager interrupt
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
SMI_1_MASK : SyncManager interrupt
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
SMI_2_MASK : SyncManager interrupt
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
SMI_3_MASK : SyncManager interrupt
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
SMI_4_MASK : SyncManager interrupt
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
SMI_5_MASK : SyncManager interrupt
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
SMI_6_MASK : SyncManager interrupt
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
SMI_7_MASK : SyncManager interrupt
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
SMI_8_MASK : SyncManager interrupt
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
SMI_9_MASK : SyncManager interrupt
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
SMI_10_MASK : SyncManager interrupt
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
SMI_11_MASK : SyncManager interrupt
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
SMI_12_MASK : SyncManager interrupt
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
SMI_13_MASK : SyncManager interrupt
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
SMI_14_MASK : SyncManager interrupt
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
SMI_15_MASK : SyncManager interrupt
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Corresponding AL Event Request register bit is not mapped
0b1 : value2
Corresponding AL Event Request register bit is mapped
End of enumeration elements list.
Write Register Protection
address_offset : 0x21 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR_REG_P : Write register protection
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Protection disabled
#1 : value2
Protection enabled
End of enumeration elements list.
ECAT Event Request
address_offset : 0x210 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DC_LE : DC Latch event
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No change on DC Latch Inputs
0b1 : value2
At least one change on DC Latch Inputs
End of enumeration elements list.
DL_SE : DL Status event
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No change in DL Status
0b1 : value2
DL Status change
End of enumeration elements list.
AL_SE : AL Status event
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No change in AL Status
0b1 : value2
AL Status change
End of enumeration elements list.
MIR_0 : Mirrors values of each SyncManager Status
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Sync Channel 0 event
0b1 : value2
Sync Channel 0 event pending
End of enumeration elements list.
MIR_1 : Mirrors values of each SyncManager Status
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Sync Channel 1 event
0b1 : value2
Sync Channel 1 event pending
End of enumeration elements list.
MIR_2 : Mirrors values of each SyncManager Status
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Sync Channel 2 event
0b1 : value2
Sync Channel 2 event pending
End of enumeration elements list.
MIR_3 : Mirrors values of each SyncManager Status
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Sync Channel 3 event
0b1 : value2
Sync Channel 3event pending
End of enumeration elements list.
MIR_4 : Mirrors values of each SyncManager Status
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Sync Channel 4 event
0b1 : value2
Sync Channel 4 event pending
End of enumeration elements list.
MIR_5 : Mirrors values of each SyncManager Status
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Sync Channel 5 event
0b1 : value2
Sync Channel 5 event pending
End of enumeration elements list.
MIR_6 : Mirrors values of each SyncManager Status
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Sync Channel 6 event
0b1 : value2
Sync Channel 6 event pending
End of enumeration elements list.
MIR_7 : Mirrors values of each SyncManager Status
bits : 11 - 10 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Sync Channel 7 event
0b1 : value2
Sync Channel 7 event pending
End of enumeration elements list.
AL Event Request
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AL_CE : AL Control event
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No AL Control Register change
0b1 : value2
AL Control Register has been written
End of enumeration elements list.
DC_LE : DC Latch event
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No change on DC Latch Inputs
0b1 : value2
At least one change on DC Latch Inputs
End of enumeration elements list.
ST_S0 : State of DC SYNC0
bits : 2 - 1 (0 bit)
access : read-only
ST_S1 : State of DC SYNC1
bits : 3 - 2 (0 bit)
access : read-only
SM_A : SyncManager activation register changed
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No change in any SyncManager
0b1 : value2
At least one change on DC Latch Inputs
End of enumeration elements list.
EEP_E : EEPROM Emulation
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No command pending
0b1 : value2
EEPROM command pending
End of enumeration elements list.
WP_D : Watchdog Process Data
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Has not expired
0b1 : value2
Has expired
End of enumeration elements list.
SMI_0 : SyncManager interrupt
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No SyncManager 0 interrupt
0b1 : value2
SyncManager 0 interrupt pending
End of enumeration elements list.
SMI_1 : SyncManager interrupt
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No SyncManager 0 interrupt
0b1 : value2
SyncManager 0 interrupt pending
End of enumeration elements list.
SMI_2 : SyncManager interrupt
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No SyncManager 0 interrupt
0b1 : value2
SyncManager 0 interrupt pending
End of enumeration elements list.
SMI_3 : SyncManager interrupt
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No SyncManager 0 interrupt
0b1 : value2
SyncManager 0 interrupt pending
End of enumeration elements list.
SMI_4 : SyncManager interrupt
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No SyncManager 0 interrupt
0b1 : value2
SyncManager 0 interrupt pending
End of enumeration elements list.
SMI_5 : SyncManager interrupt
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No SyncManager 0 interrupt
0b1 : value2
SyncManager 0 interrupt pending
End of enumeration elements list.
SMI_6 : SyncManager interrupt
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No SyncManager 0 interrupt
0b1 : value2
SyncManager 0 interrupt pending
End of enumeration elements list.
SMI_7 : SyncManager interrupt
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No SyncManager 0 interrupt
0b1 : value2
SyncManager 0 interrupt pending
End of enumeration elements list.
SMI_8 : SyncManager interrupt
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No SyncManager 0 interrupt
0b1 : value2
SyncManager 0 interrupt pending
End of enumeration elements list.
SMI_9 : SyncManager interrupt
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No SyncManager 0 interrupt
0b1 : value2
SyncManager 0 interrupt pending
End of enumeration elements list.
SMI_10 : SyncManager interrupt
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No SyncManager 0 interrupt
0b1 : value2
SyncManager 0 interrupt pending
End of enumeration elements list.
SMI_11 : SyncManager interrupt
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No SyncManager 0 interrupt
0b1 : value2
SyncManager 0 interrupt pending
End of enumeration elements list.
SMI_12 : SyncManager interrupt
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No SyncManager 0 interrupt
0b1 : value2
SyncManager 0 interrupt pending
End of enumeration elements list.
SMI_13 : SyncManager interrupt
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No SyncManager 0 interrupt
0b1 : value2
SyncManager 0 interrupt pending
End of enumeration elements list.
SMI_14 : SyncManager interrupt
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No SyncManager 0 interrupt
0b1 : value2
SyncManager 0 interrupt pending
End of enumeration elements list.
SMI_15 : SyncManager interrupt
bits : 23 - 22 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No SyncManager 0 interrupt
0b1 : value2
SyncManager 0 interrupt pending
End of enumeration elements list.
ESC Write Enable
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ESC_WR_PROT : Write protection enabled
bits : 0 - -1 (0 bit)
access : read-only
RX Error Counter Port 0
address_offset : 0x300 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INVALID_FRAME : Invalid frame counter of Port y
bits : 0 - 6 (7 bit)
access : read-only
RX_ERROR : RX Error counter of Port y
bits : 8 - 14 (7 bit)
access : read-only
RX Error Counter Port 1
address_offset : 0x302 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INVALID_FRAME : Invalid frame counter of Port y
bits : 0 - 6 (7 bit)
access : read-only
RX_ERROR : RX Error counter of Port y
bits : 8 - 14 (7 bit)
access : read-only
Forwarded RX Error Counter Port 0
address_offset : 0x308 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FORW_ERROR : Forwarded error counter of Port y
bits : 0 - 6 (7 bit)
access : read-only
Forwarded RX Error Counter Port 1
address_offset : 0x309 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FORW_ERROR : Forwarded error counter of Port y
bits : 0 - 6 (7 bit)
access : read-only
ECAT Processing Unit Error Counter
address_offset : 0x30C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UNIT_ERROR : ECAT Processing Unit error counter
bits : 0 - 6 (7 bit)
access : read-only
PDI Error Counter
address_offset : 0x30D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDI_ERROR_COUNTER : PDI Error counter
bits : 0 - 6 (7 bit)
access : read-only
ESC Write Protection
address_offset : 0x31 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ESC_WR_PROT : Write protect
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Protection disabled
#1 : value2
Protection enabled
End of enumeration elements list.
Lost Link Counter Port 0
address_offset : 0x310 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LL_COUNTER : Lost Link counter of Port p
bits : 0 - 6 (7 bit)
access : read-only
Lost Link Counter Port 1
address_offset : 0x311 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LL_COUNTER : Lost Link counter of Port p
bits : 0 - 6 (7 bit)
access : read-only
FMMUs Supported
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NUM_FMMU : Number of supported FMMU channels (or entities) of the EtherCAT Slave Controller
bits : 0 - 6 (7 bit)
access : read-only
ESC Reset ECAT [WRITE Mode]
address_offset : 0x40 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : WRITEMode
reset_Mask : 0x0
RESET_CMD : Reset commands issued by EtherCAt Master
bits : 0 - 6 (7 bit)
access : read-only
Watchdog Divider
address_offset : 0x400 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WD_DIV : Watchdog divider
bits : 0 - 14 (15 bit)
access : read-write
ESC Reset PDI [WRITE Mode]
address_offset : 0x41 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : WRITEMode
reset_Mask : 0x0
RESET_CMD : Reset commands issued by XMC4700
bits : 0 - 6 (7 bit)
access : read-only
Watchdog Time PDI
address_offset : 0x410 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WD_TIME_PDI : Watchdog Time PDI
bits : 0 - 14 (15 bit)
access : read-write
Watchdog Time Process Data
address_offset : 0x420 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WD_TIME_PD : Watchdog Time Process Data
bits : 0 - 14 (15 bit)
access : read-write
Watchdog Status Process Data
address_offset : 0x440 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WD_STAT_PD : Watchdog Status of Process Data
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Watchdog Process Data expired
0b1 : value2
Watchdog Process Data is active or disabled
End of enumeration elements list.
Watchdog Counter Process Data
address_offset : 0x442 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WD_COUNTER_PD : Watchdog Counter Process Data
bits : 0 - 6 (7 bit)
access : read-only
Watchdog Counter PDI
address_offset : 0x443 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WD_COUNTER_PDI : Watchdog PDI counter
bits : 0 - 6 (7 bit)
access : read-only
SyncManagers Supported
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NUM_SM : Number of supported SyncManager channels (or entities) of the EtherCAT Slave Controller
bits : 0 - 6 (7 bit)
access : read-only
EEPROM Configuration
address_offset : 0x500 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TO_PDI : EEPROM control is offered to PDI
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No
0b1 : value2
Yes (PDI has EEPROM control)
End of enumeration elements list.
FORCE : Force ECAT access
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Do not change Bit 501.0
0b1 : value2
Reset Bit 501.0 to 0
End of enumeration elements list.
EEPROM PDI Access State
address_offset : 0x501 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACCESS : Access to EEPROM
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
PDI releases EEPROM access
0b1 : value2
PDI takes EEPROM access (PDI has EEPROM control)
End of enumeration elements list.
EEPROM Control/Status
address_offset : 0x502 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
W_EN : ECAT write enable
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Write requests are disabled
0b1 : value2
Write requests are enabled
End of enumeration elements list.
EMUL : EEPROM emulation
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Normal operation (I2C interface used)
0b1 : value2
PDI emulates EEPROM (I2C not used)
End of enumeration elements list.
BYTES : Supported number of EEPROM read bytes
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
0b0 : value1
4 Bytes
0b1 : value2
8 Bytes
End of enumeration elements list.
ALG : Selected EEPROM Algorithm
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
0b0 : value1
1 address byte (1 KBit - 16 KBit EEPROMs)
0b1 : value2
2 address bytes (32 KBit - 4 MBit EEPROMs)
End of enumeration elements list.
CMD_REG : Command register
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0b000 : value1
No command/EEPROM idle (clear error bits)
0b001 : value2
Read
0b010 : value3
Write
0b100 : value4
Reload
End of enumeration elements list.
ERROR : Checksum Error at in ESC Configuration Area
bits : 11 - 10 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Checksum OK
0b1 : value2
Checksum error
End of enumeration elements list.
L_STAT : EEPROM loading status
bits : 12 - 11 (0 bit)
access : read-only
Enumeration:
0b0 : value1
EEPROM loaded, device information OK
0b1 : value2
EEPROM not loaded, device information not available (EEPROM loading in progress or finished with a failure)
End of enumeration elements list.
ERROR_AC : Error Acknowledge/Command
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No error
0b1 : value2
Missing EEPROM acknowledge or invalid command
End of enumeration elements list.
ERROR_WE : Error Write Enable
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No error
0b1 : value2
Write Command without Write enable
End of enumeration elements list.
BUSY : Busy
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
0b0 : value1
EEPROM Interface is idle
0b1 : value2
EEPROM Interface is busy
End of enumeration elements list.
EEPROM Address
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EEPROM_ADDR : EEPROM Address
bits : 0 - 30 (31 bit)
access : read-write
Enumeration:
0b0 : value1
First word (= 16 bits)
0b1 : value2
Second word
End of enumeration elements list.
MII Management Control/Status
address_offset : 0x510 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
W_EN : Write enable
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Write disabled
0b1 : value2
Write enabled
End of enumeration elements list.
MIC_PDI : Management Interface can be controlled by PDI
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Only ECAT control
0b1 : value2
PDI control possible
End of enumeration elements list.
MI_LD : MI link detection
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Not available
0b1 : value2
MI link detection active
End of enumeration elements list.
PHY_ADDR : PHY address of port 0
bits : 3 - 6 (4 bit)
access : read-only
CMD_REG : Command register
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0b00 : value1
No command/MII idle (clear error bits)
0b01 : value2
Read
0b10 : value3
Write
End of enumeration elements list.
ERROR : Command error
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Last Command was successful
0b1 : value2
Invalid command or write command without Write Enable
End of enumeration elements list.
BUSY : Busy
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
0b0 : value1
MI control state machine is idle
0b1 : value2
MI control state machine is active
End of enumeration elements list.
PHY Address
address_offset : 0x512 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHY_ADDR : PHY Address
bits : 0 - 3 (4 bit)
access : read-write
PHY_CADDR : Show configured PHY address of port 0-3 in registerECAT0_MII_CONT_STAT[7:3]. Select port x with bits [4:0] of this register (valid values are 0-3)
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Show address of port 0 (offset)
0b1 : value2
Show individual address of port x
End of enumeration elements list.
PHY Register Address
address_offset : 0x513 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHY_REG_ADDR : Address of PHY Register that shall beread/written
bits : 0 - 3 (4 bit)
access : read-write
PHY Data
address_offset : 0x514 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHY_RW_DATA : PHY Read/Write Data
bits : 0 - 14 (15 bit)
access : read-write
MII ECAT ACS STATE
address_offset : 0x516 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN_ACS_MII_BY_PDI : Access to MII management
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
ECAT enables PDI takeover of MII management control
0b1 : value2
ECAT claims exclusive access to MII management
End of enumeration elements list.
MII PDI ACS STATE
address_offset : 0x517 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACS_MII_BY_PDI : Access to MII management
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
ECAT has access to MII managment
0b1 : value2
PDI has access to MII managment
End of enumeration elements list.
FORCE_PDI_ACS_S : Force PDI Access State by ECAT master
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : value1
no change
0b1 : value2
Reset Bit ACS_MII_BY_PDI
End of enumeration elements list.
RAM Size
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAM_Size : Process Data RAM size supported by the EtherCAT Slave Controller in KByte
bits : 0 - 6 (7 bit)
access : read-only
Port Descriptor
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Port0 : Port Configuration
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#00 : value1
Not implemented
#01 : value2
Not configured (SII EEPROM)
#10 : value3
EBUS
#11 : value4
MII / RMII / RGMII
End of enumeration elements list.
Port1 : Port Configuration
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#00 : value1
Not implemented
#01 : value2
Not configured (SII EEPROM)
#10 : value3
EBUS
#11 : value4
MII / RMII / RGMII
End of enumeration elements list.
Port2 : Port Configuration
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#00 : value1
Not implemented
#01 : value2
Not configured (SII EEPROM)
#10 : value3
EBUS
#11 : value4
MII / RMII / RGMII
End of enumeration elements list.
Port3 : Port Configuration
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#00 : value1
Not implemented
#01 : value2
Not configured (SII EEPROM)
#10 : value3
EBUS
#11 : value4
MII / RMII / RGMII
End of enumeration elements list.
ESC Features Supported
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FMMU : FMMU Operation
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Bit oriented
#1 : value2
Byte oriented
End of enumeration elements list.
CLKS : Distributed Clocks
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not available
#1 : value2
Available
End of enumeration elements list.
CLKS_W : Distributed Clocks (width)
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : value1
32 bits
#1 : value2
64 bits
End of enumeration elements list.
LJ_EBUS : Low Jitter EBUS
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not available, standard jitter
#1 : value2
Available, jitter minimized
End of enumeration elements list.
ELD_EBUS : Enhanced Link Detection EBUS
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not available
#1 : value2
Available
End of enumeration elements list.
ELD_MII : Enhanced Link Detection MII
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not available
#1 : value2
Available
End of enumeration elements list.
SH_FCSE : Separate Handling of FCS Errors
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not supported
#1 : value2
Supported, frames with wrong FCS and additional nibble will be counted separately in Forwarded RX Error Counter
End of enumeration elements list.
EDC_SYNCA : Enhanced DC SYNC Activation
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not available
#1 : value2
Available
End of enumeration elements list.
LRW_CS : EtherCAT LRW command support
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : value1
Supported
#1 : value2
Not supported
End of enumeration elements list.
RW_CS : EtherCAT read/write command support (BRW, APRW, FPRW)
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
#0 : value1
Supported
#1 : value2
Not supported
End of enumeration elements list.
FX_CONF : Fixed FMMU/SyncManager configuration
bits : 11 - 10 (0 bit)
access : read-only
Enumeration:
#0 : value1
Variable configuration
#1 : value2
Fixed configuration (refer to documentation of supporting ESCs)
End of enumeration elements list.
Receive Time Port 0
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCAL_TIME_P0 : Write by EtherCAT master
bits : 0 - 30 (31 bit)
access : read-only
Receive Time Port 1
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCAL_TIME_P1 : Local time of the beginning of a frame
bits : 0 - 30 (31 bit)
access : read-only
System Time [WRITE Mode]
address_offset : 0x910 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : WRITEMode
reset_Mask : 0x0
WRITE_ACCESS : Write access
bits : 0 - 30 (31 bit)
access : write-only
System Time Delay
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK_DELAY : Delay between Reference Clock and the ESC
bits : 0 - 30 (31 bit)
access : read-write
System Time Difference
address_offset : 0x92C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIME_DIF : Mean difference between local copy of System Time and received System Time values
bits : 0 - 29 (30 bit)
access : read-only
CPY : Local copy of System Time
bits : 31 - 30 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Greater than or equal received System Time
0b1 : value2
Smaller than received System Time
End of enumeration elements list.
Speed Counter Start
address_offset : 0x930 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT_START : Bandwidth for adjustment of local copy of System Time
bits : 0 - 13 (14 bit)
access : read-write
Speed Counter Diff
address_offset : 0x932 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEVIATION : Representation of the deviation between local clock period and Reference Clock's clock period
bits : 0 - 14 (15 bit)
access : read-only
System Time Difference Filter Depth
address_offset : 0x934 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTER_DEPTH : Filter depth for averaging the received System Time deviation
bits : 0 - 2 (3 bit)
access : read-write
Speed Counter Filter Depth
address_offset : 0x935 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FILTER_DEPTH : Filter depth for averaging the clock period deviation
bits : 0 - 2 (3 bit)
access : read-write
Cyclic Unit Control
address_offset : 0x980 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNC : SYNC out unit control
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
ECAT controlled
0b1 : value2
PDI controlled
End of enumeration elements list.
LATCH_U0 : Latch In unit 0
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : value1
ECAT controlled
0b1 : value2
PDI controlled
End of enumeration elements list.
LATCH_U1 : Latch In unit 1
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
0b0 : value1
ECAT controlled
0b1 : value2
PDI controlled
End of enumeration elements list.
Activation register
address_offset : 0x981 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNC_OUT : Sync Out Unit activation
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Deactivated
0b1 : value2
Activated
End of enumeration elements list.
SYNC_0 : SYNC0 generation
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Deactivated
0b1 : value2
SYNC0 pulse is generated
End of enumeration elements list.
SYNC_1 : SYNC1 generation
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Deactivated
0b1 : value2
SYNC1 pulse is generated
End of enumeration elements list.
Pulse Length of SyncSignals
address_offset : 0x982 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PULS_LENGTH : Pulse length of SyncSignals
bits : 0 - 14 (15 bit)
access : read-only
Enumeration:
0b0 : value1
Acknowledge mode: SyncSignal will be cleared by reading SYNC[1:0] Status register
End of enumeration elements list.
Activation Status
address_offset : 0x984 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
S0_ACK_STATE : SYNC0 activation state
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
First SYNC0 pulse is not pending
0b1 : value2
First SYNC0 pulse is pending
End of enumeration elements list.
S1_ACK_STATE : SYNC1 activation state
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : value1
First SYNC1 pulse is not pending
0b1 : value2
First SYNC1 pulse is pending
End of enumeration elements list.
S_TIME : Start Time Cyclic Operation
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Start Time was within near future
0b1 : value2
Start Time was out of near future (0x0981.6)
End of enumeration elements list.
SYNC0 Status
address_offset : 0x98E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
S0_STATE : SYNC0 state for Acknowledge mode
bits : 0 - -1 (0 bit)
access : read-only
SYNC1 Status
address_offset : 0x98F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
S1_STATE : SYNC1 state for Acknowledge mode
bits : 0 - -1 (0 bit)
access : read-only
SYNC0 Cycle Time
address_offset : 0x9A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIME_BETWEEN_SYNC0 : Time between two consecutive SYNC0 pulses
bits : 0 - 30 (31 bit)
access : read-write
Enumeration:
0b0 : value1
Single shot mode, generate only one SYNC0 pulse
End of enumeration elements list.
SYNC1 Cycle Time
address_offset : 0x9A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIME_SYNC1_SYNC0 : Time between SYNC1 pulses and SYNC0 pulse
bits : 0 - 30 (31 bit)
access : read-write
Latch0 Control
address_offset : 0x9A8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L0_POS : Latch0 positive edge
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Continuous Latch active
0b1 : value2
Single event (only first event active)
End of enumeration elements list.
L0_NEG : Latch0 negative edge
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Continuous Latch active
0b1 : value2
Single event (only first event active)
End of enumeration elements list.
Latch1 Control
address_offset : 0x9A9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
L1_POS : Latch1 positive edge
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Continuous Latch active
0b1 : value2
Single event (only first event active)
End of enumeration elements list.
L1_NEG : Latch1 negative edge
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Continuous Latch active
0b1 : value2
Single event (only first event active)
End of enumeration elements list.
Latch0 Status
address_offset : 0x9AE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EV_L0_POS : Event Latch0 positive edge
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Positive edge not detected or continuous mode
0b1 : value2
Positive edge detected in single event mode only
End of enumeration elements list.
EV_L0_NEG : Event Latch0 negative edge
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Negative edge not detected or continuous mode
0b1 : value2
Negative edge detected in single event mode only
End of enumeration elements list.
L0_PIN : Latch0 pin state
bits : 2 - 1 (0 bit)
access : read-only
Latch1 Status
address_offset : 0x9AF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EV_L1_POS : Event Latch1 positive edge
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Positive edge not detected or continuous mode
0b1 : value2
Positive edge detected in single event mode only
End of enumeration elements list.
EV_L1_NEG : Event Latch1 negative edge
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Negative edge not detected or continuous mode
0b1 : value2
Negative edge detected in single event mode only
End of enumeration elements list.
L1_PIN : Latch1 pin state
bits : 2 - 1 (0 bit)
access : read-only
EtherCAT Buffer Change Event Time
address_offset : 0x9F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECAT_CNG_EV_TIME : Register captures local time of the beginning of the frame which causes at least one SyncManager to assert an ECAT event
bits : 0 - 30 (31 bit)
access : read-only
PDI Buffer Start Event Time
address_offset : 0x9F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDI_START_EV_TIME : Register captures local time when at least one SyncManager asserts an PDI buffer start event
bits : 0 - 30 (31 bit)
access : read-only
PDI Buffer Change Event Time
address_offset : 0x9FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDI_CNG_EV_TIME : Register captures local time when at least one SyncManager asserts an PDI buffer change event
bits : 0 - 30 (31 bit)
access : read-only
EEPROM Read/Write data
address_offset : 0xA10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EEP_DATA : EEPROM Data
bits : 0 - 30 (31 bit)
access : read-write
ECAT0 Module ID
address_offset : 0xE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD_REV : Module Revision Number
bits : 0 - 6 (7 bit)
access : read-only
MOD_TYPE : Module Type
bits : 8 - 14 (7 bit)
access : read-only
MOD_NUMBER : Module Number Value
bits : 16 - 30 (15 bit)
access : read-only
ECAT0 Status
address_offset : 0xE08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PARERR : PARITY ERROR
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Error
0b1 : value2
Parity Error in User or Process RAM
End of enumeration elements list.
EEPROM Read/Write data
address_offset : 0xF1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EEP_DATA : EEPROM Data
bits : 0 - 30 (31 bit)
access : read-write
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