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ECAT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

Registers

FMMU_L_START_ADR

FMMU_LEN

FMMU_L_START_BIT

FMMU_L_STOP_BIT

FMMU_P_START_ADR

FMMU_P_START_BIT

FMMU_TYPE

FMMU_ACT


FMMU_L_START_ADR

Logical Start address FMMU
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMMU_L_START_ADR FMMU_L_START_ADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L_START_ADDR

L_START_ADDR : Logical start address within the EtherCAT Address Space
bits : 0 - 30 (31 bit)
access : read-only


FMMU_LEN

Length FMMU 0
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMMU_LEN FMMU_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET

OFFSET : Offset from the first logical FMMU Byte to the last FMMU Byte + 1
bits : 0 - 14 (15 bit)
access : read-only


FMMU_L_START_BIT

Start bit FMMU 0 in logical address space
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMMU_L_START_BIT FMMU_L_START_BIT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 L_START_BIT

L_START_BIT : Logical starting bit that shall be mapped
bits : 0 - 1 (2 bit)
access : read-only


FMMU_L_STOP_BIT

Stop bit FMMU 0 in logical address space
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMMU_L_STOP_BIT FMMU_L_STOP_BIT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 L_STOP_BIT

L_STOP_BIT : Last logical bit that shall be mapped
bits : 0 - 1 (2 bit)
access : read-only


FMMU_P_START_ADR

Ph0sical Start address FMMU y
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMMU_P_START_ADR FMMU_P_START_ADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_START_ADDR

P_START_ADDR : Physical Start Address
bits : 0 - 14 (15 bit)
access : read-only


FMMU_P_START_BIT

Ph0sical Start bit FMMU y
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMMU_P_START_BIT FMMU_P_START_BIT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 P_START_BIT

P_START_BIT : Physical starting bit as target of logical start bit mapping
bits : 0 - 1 (2 bit)
access : read-only


FMMU_TYPE

T0pe FMMU y
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMMU_TYPE FMMU_TYPE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R_ACC W_ACC

R_ACC : Read Access
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

0b0 : value1

Ignore mapping for read accesses

0b1 : value2

Use mapping for read accesses

End of enumeration elements list.

W_ACC : Write Access
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

0b0 : value1

Ignore mapping for write accesses

0b1 : value2

Use mapping for write accesses

End of enumeration elements list.


FMMU_ACT

Activate FMMU 0
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMMU_ACT FMMU_ACT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ACT

ACT : FMMU Activation
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

0b0 : value1

FMMU deactivated.

0b1 : value2

FMMU activated. FMMU checks logical addressed blocks to be mapped according to mapping configured

End of enumeration elements list.



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