Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Clock Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DISR : Module Disable Request Bit
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
On request: enable the module clock
#1 : value2
Off request: stop the module clock
End of enumeration elements list.
DISS : Module Disable Status Bit
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : value1
Module clock is enabled
#1 : value2
Off: module is not clocked
End of enumeration elements list.
EDIS : Sleep Mode Enable Control
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Sleep mode request is enabled and functional
#1 : value2
Module disregards the sleep mode control signal
End of enumeration elements list.
Input Class Register, Global
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STCS : Sample Time Control for Standard Conversions
bits : 0 - 3 (4 bit)
access : read-write
CMS : Conversion Mode for Standard Conversions
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#000 : value1
12-bit conversion
#001 : value2
10-bit conversion
#010 : value3
8-bit conversion
#101 : value6
10-bit fast compare mode
End of enumeration elements list.
STCE : Sample Time Control for EMUX Conversions
bits : 16 - 19 (4 bit)
access : read-write
CME : Conversion Mode for EMUX Conversions
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#000 : value1
12-bit conversion
#001 : value2
10-bit conversion
#010 : value3
8-bit conversion
#101 : value6
10-bit fast compare mode
End of enumeration elements list.
Global Event Node Pointer Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEV0NP : Service Request Node Pointer Backgr. Source
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0000 : value1
Select shared service request line 0 of common service request group 0
#0011 : value2
Select shared service request line 3 of common service request group 0
#0100 : value3
Select shared service request line 0 of common service request group 1
#0111 : value4
Select shared service request line 3 of common service request group 1
End of enumeration elements list.
REV0NP : Service Request Node Pointer Backgr. Result
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#0000 : value1
Select shared service request line 0 of common service request group 0
#0011 : value2
Select shared service request line 3 of common service request group 0
#0100 : value3
Select shared service request line 0 of common service request group 1
#0111 : value4
Select shared service request line 3 of common service request group 1
End of enumeration elements list.
Global Test Functions Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDGR : Converter Diagnostics Group
bits : 4 - 6 (3 bit)
access : read-write
CDEN : Converter Diagnostics Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
All diagnostic pull devices are disconnected
#1 : value2
Diagnostic pull devices connected as selected by bitfield CDSEL
End of enumeration elements list.
CDSEL : Converter Diagnostics Pull-Devices Select
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#00 : value1
Connected to VAREF
#01 : value2
Connected to VAGND
#10 : value3
Connected to 1/3rd VAREF
#11 : value4
Connected to 2/3rd VAREF
End of enumeration elements list.
CDWC : Write Control for Conversion Diagnostics
bits : 15 - 14 (0 bit)
access : write-only
Enumeration:
#0 : value1
No write access to parameters
#1 : value2
Bitfields CDSEL, CDEN, CDGR can be written
End of enumeration elements list.
PDD : Pull-Down Diagnostics Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disconnected
#1 : value2
The pull-down diagnostics device is active
End of enumeration elements list.
MDWC : Write Control for Multiplexer Diagnostics
bits : 23 - 22 (0 bit)
access : write-only
Enumeration:
#0 : value1
No write access to parameters
#1 : value2
Bitfield PDD can be written
End of enumeration elements list.
Input Class Register, Global
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STCS : Sample Time Control for Standard Conversions
bits : 0 - 3 (4 bit)
access : read-write
CMS : Conversion Mode for Standard Conversions
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#000 : value1
12-bit conversion
#001 : value2
10-bit conversion
#010 : value3
8-bit conversion
#101 : value6
10-bit fast compare mode
End of enumeration elements list.
STCE : Sample Time Control for EMUX Conversions
bits : 16 - 19 (4 bit)
access : read-write
CME : Conversion Mode for EMUX Conversions
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#000 : value1
12-bit conversion
#001 : value2
10-bit conversion
#010 : value3
8-bit conversion
#101 : value6
10-bit fast compare mode
End of enumeration elements list.
Background Request Source Control Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCRESREG : Source-specific Result Register
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0000 : value1
Use GxCHCTRy.RESREG to select a group result register
#0001 : value2
Store result in group result register GxRES1
#1111 : value3
Store result in group result register GxRES15
End of enumeration elements list.
XTSEL : External Trigger Input Selection
bits : 8 - 10 (3 bit)
access : read-write
XTLVL : External Trigger Level
bits : 12 - 11 (0 bit)
access : read-only
XTMODE : Trigger Operating Mode
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#00 : value1
No external trigger
#01 : value2
Trigger event upon a falling edge
#10 : value3
Trigger event upon a rising edge
#11 : value4
Trigger event upon any edge
End of enumeration elements list.
XTWC : Write Control for Trigger Configuration
bits : 15 - 14 (0 bit)
access : write-only
Enumeration:
#0 : value1
No write access to trigger configuration
#1 : value2
Bitfields XTMODE and XTSEL can be written
End of enumeration elements list.
GTSEL : Gate Input Selection
bits : 16 - 18 (3 bit)
access : read-write
GTLVL : Gate Input Level
bits : 20 - 19 (0 bit)
access : read-only
GTWC : Write Control for Gate Configuration
bits : 23 - 22 (0 bit)
access : write-only
Enumeration:
#0 : value1
No write access to gate configuration
#1 : value2
Bitfield GTSEL can be written
End of enumeration elements list.
Background Request Source Mode Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENGT : Enable Gate
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : value1
No conversion requests are issued
#01 : value2
Conversion requests are issued if at least one pending bit is set
#10 : value3
Conversion requests are issued if at least one pending bit is set and REQGTx = 1.
#11 : value4
Conversion requests are issued if at least one pending bit is set and REQGTx = 0.
End of enumeration elements list.
ENTR : Enable External Trigger
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
External trigger disabled
#1 : value2
The selected edge at the selected trigger input signal REQTR generates the load event
End of enumeration elements list.
ENSI : Enable Source Interrupt
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
No request source interrupt
#1 : value2
A request source interrupt is generated upon a request source event (last pending conversion is finished)
End of enumeration elements list.
SCAN : Autoscan Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
No autoscan
#1 : value2
Autoscan functionality enabled: a request source event automatically generates a load event
End of enumeration elements list.
LDM : Autoscan Source Load Event Mode
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
Overwrite mode: Copy all bits from the select registers to the pending registers upon a load event
#1 : value2
Combine mode: Set all pending bits that are set in the select registers upon a load event (logic OR)
End of enumeration elements list.
REQGT : Request Gate Level
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : value1
The gate input is low
#1 : value2
The gate input is high
End of enumeration elements list.
CLRPND : Clear Pending Bits
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
The bits in registers BRSPNDx are cleared
End of enumeration elements list.
LDEV : Generate Load Event
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
A load event is generated
End of enumeration elements list.
RPTDIS : Repeat Disable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
A cancelled conversion is repeated
#1 : value2
A cancelled conversion is discarded
End of enumeration elements list.
OCDS Control and Status Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TGS : Trigger Set for OTGB0/1
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : value1
No Trigger Set output
#01 : value2
Trigger Set 1: TS16_SSIG, input sample signals
End of enumeration elements list.
TGB : OTGB0/1 Bus Select
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Trigger Set is output on OTGB0
#1 : value2
Trigger Set is output on OTGB1
End of enumeration elements list.
TG_P : TGS, TGB Write Protection
bits : 3 - 2 (0 bit)
access : write-only
SUS : OCDS Suspend Control
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#0000 : value1
Will not suspend
#0001 : value2
Hard suspend: Clock is switched off immediately.
#0010 : value3
Soft suspend mode 0: Stop conversions after the currently running one is completed and its result has been stored. No change for the arbiter.
#0011 : value4
Soft suspend mode 1: Stop conversions after the currently running one is completed and its result has been stored. Stop arbiter after the current arbitration round.
End of enumeration elements list.
SUS_P : SUS Write Protection
bits : 28 - 27 (0 bit)
access : write-only
SUSSTA : Suspend State
bits : 29 - 28 (0 bit)
access : read-only
Enumeration:
#0 : value1
Module is not (yet) suspended
#1 : value2
Module is suspended
End of enumeration elements list.
Global Result Control Register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRCTR : Data Reduction Control
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#0000 : value1
Data reduction disabled
End of enumeration elements list.
WFR : Wait-for-Read Mode Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : value1
Overwrite mode
#1 : value2
Wait-for-read mode enabled for this register
End of enumeration elements list.
SRGEN : Service Request Generation Enable
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : value1
No service request
#1 : value2
Service request after a result event
End of enumeration elements list.
Background Request Source Channel Select Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHSELG0 : Channel Selection Group x
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
This channel is part of the scan sequence
End of enumeration elements list.
CHSELG1 : Channel Selection Group x
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
This channel is part of the scan sequence
End of enumeration elements list.
CHSELG2 : Channel Selection Group x
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
This channel is part of the scan sequence
End of enumeration elements list.
CHSELG3 : Channel Selection Group x
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
This channel is part of the scan sequence
End of enumeration elements list.
CHSELG4 : Channel Selection Group x
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
This channel is part of the scan sequence
End of enumeration elements list.
CHSELG5 : Channel Selection Group x
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
This channel is part of the scan sequence
End of enumeration elements list.
CHSELG6 : Channel Selection Group x
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
This channel is part of the scan sequence
End of enumeration elements list.
CHSELG7 : Channel Selection Group x
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
This channel is part of the scan sequence
End of enumeration elements list.
Global Result Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESULT : Result of most recent conversion
bits : 0 - 14 (15 bit)
access : read-write
GNR : Group Number
bits : 16 - 18 (3 bit)
access : read-only
CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only
EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only
CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only
FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only
Enumeration:
#0 : value1
Signal level was below compare value
#1 : value2
Signal level was above compare value
End of enumeration elements list.
VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : value1
Read access: No new valid data available Write access: No effect
#1 : value2
Read access: Bitfield RESULT contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and the data reduction counter (overrides a hardware set action)
End of enumeration elements list.
Background Request Source Pending Register
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPNDG0 : Channels Pending Group x
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
Request conversion of this channel
End of enumeration elements list.
CHPNDG1 : Channels Pending Group x
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
Request conversion of this channel
End of enumeration elements list.
CHPNDG2 : Channels Pending Group x
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
Request conversion of this channel
End of enumeration elements list.
CHPNDG3 : Channels Pending Group x
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
Request conversion of this channel
End of enumeration elements list.
CHPNDG4 : Channels Pending Group x
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
Request conversion of this channel
End of enumeration elements list.
CHPNDG5 : Channels Pending Group x
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
Request conversion of this channel
End of enumeration elements list.
CHPNDG6 : Channels Pending Group x
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
Request conversion of this channel
End of enumeration elements list.
CHPNDG7 : Channels Pending Group x
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
Request conversion of this channel
End of enumeration elements list.
Global Result Register, Debug
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESULT : Result of most recent conversion
bits : 0 - 14 (15 bit)
access : read-write
GNR : Group Number
bits : 16 - 18 (3 bit)
access : read-only
CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only
EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only
CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only
FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only
Enumeration:
#0 : value1
Signal level was below compare value
#1 : value2
Signal level was above compare value
End of enumeration elements list.
VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : value1
Read access: No new valid data available Write access: No effect
#1 : value2
Read access: Bitfield RESULT contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and the data reduction counter (overrides a hardware set action)
End of enumeration elements list.
External Multiplexer Select Register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EMUXGRP0 : External Multiplexer Group for Interface x
bits : 0 - 2 (3 bit)
access : read-write
EMUXGRP1 : External Multiplexer Group for Interface x
bits : 4 - 6 (3 bit)
access : read-write
Background Request Source Channel Select Register
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHSELG0 : Channel Selection Group x
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
This channel is part of the scan sequence
End of enumeration elements list.
CHSELG1 : Channel Selection Group x
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
This channel is part of the scan sequence
End of enumeration elements list.
CHSELG2 : Channel Selection Group x
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
This channel is part of the scan sequence
End of enumeration elements list.
CHSELG3 : Channel Selection Group x
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
This channel is part of the scan sequence
End of enumeration elements list.
CHSELG4 : Channel Selection Group x
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
This channel is part of the scan sequence
End of enumeration elements list.
CHSELG5 : Channel Selection Group x
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
This channel is part of the scan sequence
End of enumeration elements list.
CHSELG6 : Channel Selection Group x
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
This channel is part of the scan sequence
End of enumeration elements list.
CHSELG7 : Channel Selection Group x
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
This channel is part of the scan sequence
End of enumeration elements list.
Background Request Source Pending Register
address_offset : 0x544 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHPNDG0 : Channels Pending Group x
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
Request conversion of this channel
End of enumeration elements list.
CHPNDG1 : Channels Pending Group x
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
Request conversion of this channel
End of enumeration elements list.
CHPNDG2 : Channels Pending Group x
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
Request conversion of this channel
End of enumeration elements list.
CHPNDG3 : Channels Pending Group x
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
Request conversion of this channel
End of enumeration elements list.
CHPNDG4 : Channels Pending Group x
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
Request conversion of this channel
End of enumeration elements list.
CHPNDG5 : Channels Pending Group x
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
Request conversion of this channel
End of enumeration elements list.
CHPNDG6 : Channels Pending Group x
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
Request conversion of this channel
End of enumeration elements list.
CHPNDG7 : Channels Pending Group x
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : value1
Ignore this channel
#1 : value2
Request conversion of this channel
End of enumeration elements list.
Module Identification Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD_REV : Module Revision
bits : 0 - 6 (7 bit)
access : read-only
MOD_TYPE : Module Type
bits : 8 - 14 (7 bit)
access : read-only
MOD_NUMBER : Module Number
bits : 16 - 30 (15 bit)
access : read-only
Global Configuration Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVA : Divider Factor for the Analog Internal Clock
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x00 : value1
fADCI = fADC / 2
0x01 : value2
fADCI = fADC / 2
0x02 : value3
fADCI = fADC / 3
0x1F : value4
fADCI = fADC / 32
End of enumeration elements list.
DCMSB : Double Clock for the MSB Conversion
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : value1
1 clock cycles for the MSB (standard)
#1 : value2
2 clock cycles for the MSB (fADCI > 20 MHz)
End of enumeration elements list.
DIVD : Divider Factor for the Arbiter Clock
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : value1
fADCD = fADC
#01 : value2
fADCD = fADC / 2
#10 : value3
fADCD = fADC / 3
#11 : value4
fADCD = fADC / 4
End of enumeration elements list.
DIVWC : Write Control for Divider Parameters
bits : 15 - 14 (0 bit)
access : write-only
Enumeration:
#0 : value1
No write access to divider parameters
#1 : value2
Bitfields DIVA, DCMSB, DIVD can be written
End of enumeration elements list.
DPCAL0 : Disable Post-Calibration
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
Automatic post-calibration after each conversion of group x
#1 : value2
No post-calibration
End of enumeration elements list.
DPCAL1 : Disable Post-Calibration
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
Automatic post-calibration after each conversion of group x
#1 : value2
No post-calibration
End of enumeration elements list.
DPCAL2 : Disable Post-Calibration
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : value1
Automatic post-calibration after each conversion of group x
#1 : value2
No post-calibration
End of enumeration elements list.
DPCAL3 : Disable Post-Calibration
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : value1
Automatic post-calibration after each conversion of group x
#1 : value2
No post-calibration
End of enumeration elements list.
SUCAL : Start-Up Calibration
bits : 31 - 30 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Initiate the start-up calibration phase (indication in bit GxARBCFG.CAL)
End of enumeration elements list.
Global Boundary Select Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOUNDARY0 : Boundary Value 0 for Limit Checking
bits : 0 - 10 (11 bit)
access : read-write
BOUNDARY1 : Boundary Value 1 for Limit Checking
bits : 16 - 26 (11 bit)
access : read-write
Global Event Flag Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEVGLB : Source Event (Background)
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
No source event
#1 : value2
A source event has occurred
End of enumeration elements list.
REVGLB : Global Result Event
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
No result event
#1 : value2
New result was stored in register GLOBRES
End of enumeration elements list.
SEVGLBCLR : Clear Source Event (Background)
bits : 16 - 15 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Clear the source event flag SEVGLB
End of enumeration elements list.
REVGLBCLR : Clear Global Result Event
bits : 24 - 23 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Clear the result event flag REVGLB
End of enumeration elements list.
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