\n
address_offset : 0x0 Bytes (0x0)
size : 0x7D40 byte (0x0)
mem_usage : registers
protection : not protected
Raw IntTfr Status
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Raw Interrupt Status for channel 0
bits : 0 - -1 (0 bit)
access : read-write
CH1 : Raw Interrupt Status for channel 1
bits : 1 - 0 (0 bit)
access : read-write
CH2 : Raw Interrupt Status for channel 2
bits : 2 - 1 (0 bit)
access : read-write
CH3 : Raw Interrupt Status for channel 3
bits : 3 - 2 (0 bit)
access : read-write
Raw IntSrcTran Status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Raw Interrupt Status for channel 0
bits : 0 - -1 (0 bit)
access : read-write
CH1 : Raw Interrupt Status for channel 1
bits : 1 - 0 (0 bit)
access : read-write
CH2 : Raw Interrupt Status for channel 2
bits : 2 - 1 (0 bit)
access : read-write
CH3 : Raw Interrupt Status for channel 3
bits : 3 - 2 (0 bit)
access : read-write
GPDMA Component Type
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Component Type
bits : 0 - 30 (31 bit)
access : read-only
DMA Component Version
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Version number of the component
bits : 0 - 30 (31 bit)
access : read-only
Raw IntBlock Status
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Raw Interrupt Status for channel 0
bits : 0 - -1 (0 bit)
access : read-write
CH1 : Raw Interrupt Status for channel 1
bits : 1 - 0 (0 bit)
access : read-write
CH2 : Raw Interrupt Status for channel 2
bits : 2 - 1 (0 bit)
access : read-write
CH3 : Raw Interrupt Status for channel 3
bits : 3 - 2 (0 bit)
access : read-write
Raw IntErr Status
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Raw Interrupt Status for channel 0
bits : 0 - -1 (0 bit)
access : read-write
CH1 : Raw Interrupt Status for channel 1
bits : 1 - 0 (0 bit)
access : read-write
CH2 : Raw Interrupt Status for channel 2
bits : 2 - 1 (0 bit)
access : read-write
CH3 : Raw Interrupt Status for channel 3
bits : 3 - 2 (0 bit)
access : read-write
IntTfr Status
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Interrupt Status for channel 0
bits : 0 - -1 (0 bit)
access : read-only
CH1 : Interrupt Status for channel 1
bits : 1 - 0 (0 bit)
access : read-only
CH2 : Interrupt Status for channel 2
bits : 2 - 1 (0 bit)
access : read-only
CH3 : Interrupt Status for channel 3
bits : 3 - 2 (0 bit)
access : read-only
IntBlock Status
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Interrupt Status for channel 0
bits : 0 - -1 (0 bit)
access : read-only
CH1 : Interrupt Status for channel 1
bits : 1 - 0 (0 bit)
access : read-only
CH2 : Interrupt Status for channel 2
bits : 2 - 1 (0 bit)
access : read-only
CH3 : Interrupt Status for channel 3
bits : 3 - 2 (0 bit)
access : read-only
IntSrcTran Status
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Interrupt Status for channel 0
bits : 0 - -1 (0 bit)
access : read-only
CH1 : Interrupt Status for channel 1
bits : 1 - 0 (0 bit)
access : read-only
CH2 : Interrupt Status for channel 2
bits : 2 - 1 (0 bit)
access : read-only
CH3 : Interrupt Status for channel 3
bits : 3 - 2 (0 bit)
access : read-only
IntBlock Status
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Interrupt Status for channel 0
bits : 0 - -1 (0 bit)
access : read-only
CH1 : Interrupt Status for channel 1
bits : 1 - 0 (0 bit)
access : read-only
CH2 : Interrupt Status for channel 2
bits : 2 - 1 (0 bit)
access : read-only
CH3 : Interrupt Status for channel 3
bits : 3 - 2 (0 bit)
access : read-only
IntErr Status
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Interrupt Status for channel 0
bits : 0 - -1 (0 bit)
access : read-only
CH1 : Interrupt Status for channel 1
bits : 1 - 0 (0 bit)
access : read-only
CH2 : Interrupt Status for channel 2
bits : 2 - 1 (0 bit)
access : read-only
CH3 : Interrupt Status for channel 3
bits : 3 - 2 (0 bit)
access : read-only
Mask for Raw IntTfr Status
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Mask bit for channel 0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
masked
#1 : value2
unmasked
End of enumeration elements list.
CH1 : Mask bit for channel 1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
masked
#1 : value2
unmasked
End of enumeration elements list.
CH2 : Mask bit for channel 2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
masked
#1 : value2
unmasked
End of enumeration elements list.
CH3 : Mask bit for channel 3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
masked
#1 : value2
unmasked
End of enumeration elements list.
WE_CH0 : Write enable for mask bit of channel 0
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH1 : Write enable for mask bit of channel 1
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH2 : Write enable for mask bit of channel 2
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH3 : Write enable for mask bit of channel 3
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
Mask for Raw IntBlock Status
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Mask bit for channel 0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
masked
#1 : value2
unmasked
End of enumeration elements list.
CH1 : Mask bit for channel 1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
masked
#1 : value2
unmasked
End of enumeration elements list.
CH2 : Mask bit for channel 2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
masked
#1 : value2
unmasked
End of enumeration elements list.
CH3 : Mask bit for channel 3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
masked
#1 : value2
unmasked
End of enumeration elements list.
WE_CH0 : Write enable for mask bit of channel 0
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH1 : Write enable for mask bit of channel 1
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH2 : Write enable for mask bit of channel 2
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH3 : Write enable for mask bit of channel 3
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
Mask for Raw IntSrcTran Status
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Mask bit for channel 0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
masked
#1 : value2
unmasked
End of enumeration elements list.
CH1 : Mask bit for channel 1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
masked
#1 : value2
unmasked
End of enumeration elements list.
CH2 : Mask bit for channel 2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
masked
#1 : value2
unmasked
End of enumeration elements list.
CH3 : Mask bit for channel 3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
masked
#1 : value2
unmasked
End of enumeration elements list.
WE_CH0 : Write enable for mask bit of channel 0
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH1 : Write enable for mask bit of channel 1
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH2 : Write enable for mask bit of channel 2
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH3 : Write enable for mask bit of channel 3
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
Mask for Raw IntBlock Status
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Mask bit for channel 0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
masked
#1 : value2
unmasked
End of enumeration elements list.
CH1 : Mask bit for channel 1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
masked
#1 : value2
unmasked
End of enumeration elements list.
CH2 : Mask bit for channel 2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
masked
#1 : value2
unmasked
End of enumeration elements list.
CH3 : Mask bit for channel 3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
masked
#1 : value2
unmasked
End of enumeration elements list.
WE_CH0 : Write enable for mask bit of channel 0
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH1 : Write enable for mask bit of channel 1
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH2 : Write enable for mask bit of channel 2
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH3 : Write enable for mask bit of channel 3
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
Mask for Raw IntErr Status
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Mask bit for channel 0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
masked
#1 : value2
unmasked
End of enumeration elements list.
CH1 : Mask bit for channel 1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
masked
#1 : value2
unmasked
End of enumeration elements list.
CH2 : Mask bit for channel 2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
masked
#1 : value2
unmasked
End of enumeration elements list.
CH3 : Mask bit for channel 3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
masked
#1 : value2
unmasked
End of enumeration elements list.
WE_CH0 : Write enable for mask bit of channel 0
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH1 : Write enable for mask bit of channel 1
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH2 : Write enable for mask bit of channel 2
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH3 : Write enable for mask bit of channel 3
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
IntTfr Status
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Clear Interrupt Status and Raw Status for channel 0
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
clear status
End of enumeration elements list.
CH1 : Clear Interrupt Status and Raw Status for channel 1
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
clear status
End of enumeration elements list.
CH2 : Clear Interrupt Status and Raw Status for channel 2
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
clear status
End of enumeration elements list.
CH3 : Clear Interrupt Status and Raw Status for channel 3
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
clear status
End of enumeration elements list.
Raw IntBlock Status
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Raw Interrupt Status for channel 0
bits : 0 - -1 (0 bit)
access : read-write
CH1 : Raw Interrupt Status for channel 1
bits : 1 - 0 (0 bit)
access : read-write
CH2 : Raw Interrupt Status for channel 2
bits : 2 - 1 (0 bit)
access : read-write
CH3 : Raw Interrupt Status for channel 3
bits : 3 - 2 (0 bit)
access : read-write
IntBlock Status
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Clear Interrupt Status and Raw Status for channel 0
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
clear status
End of enumeration elements list.
CH1 : Clear Interrupt Status and Raw Status for channel 1
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
clear status
End of enumeration elements list.
CH2 : Clear Interrupt Status and Raw Status for channel 2
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
clear status
End of enumeration elements list.
CH3 : Clear Interrupt Status and Raw Status for channel 3
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
clear status
End of enumeration elements list.
IntSrcTran Status
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Clear Interrupt Status and Raw Status for channel 0
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
clear status
End of enumeration elements list.
CH1 : Clear Interrupt Status and Raw Status for channel 1
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
clear status
End of enumeration elements list.
CH2 : Clear Interrupt Status and Raw Status for channel 2
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
clear status
End of enumeration elements list.
CH3 : Clear Interrupt Status and Raw Status for channel 3
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
clear status
End of enumeration elements list.
IntBlock Status
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Clear Interrupt Status and Raw Status for channel 0
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
clear status
End of enumeration elements list.
CH1 : Clear Interrupt Status and Raw Status for channel 1
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
clear status
End of enumeration elements list.
CH2 : Clear Interrupt Status and Raw Status for channel 2
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
clear status
End of enumeration elements list.
CH3 : Clear Interrupt Status and Raw Status for channel 3
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
clear status
End of enumeration elements list.
IntErr Status
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Clear Interrupt Status and Raw Status for channel 0
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
clear status
End of enumeration elements list.
CH1 : Clear Interrupt Status and Raw Status for channel 1
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
clear status
End of enumeration elements list.
CH2 : Clear Interrupt Status and Raw Status for channel 2
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
clear status
End of enumeration elements list.
CH3 : Clear Interrupt Status and Raw Status for channel 3
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : value1
no effect
#1 : value2
clear status
End of enumeration elements list.
Combined Interrupt Status Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFR : OR of the contents of STATUSTFR register
bits : 0 - -1 (0 bit)
access : read-only
BLOCK : OR of the contents of STATUSBLOCK register
bits : 1 - 0 (0 bit)
access : read-only
SRCT : OR of the contents of STATUSSRCTRAN register
bits : 2 - 1 (0 bit)
access : read-only
DSTT : OR of the contents of STATUSDSTTRAN register
bits : 3 - 2 (0 bit)
access : read-only
ERR : OR of the contents of STATUSERR register
bits : 4 - 3 (0 bit)
access : read-only
Source Software Transaction Request Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Source request for channel 0
bits : 0 - -1 (0 bit)
access : read-write
CH1 : Source request for channel 1
bits : 1 - 0 (0 bit)
access : read-write
CH2 : Source request for channel 2
bits : 2 - 1 (0 bit)
access : read-write
CH3 : Source request for channel 3
bits : 3 - 2 (0 bit)
access : read-write
WE_CH0 : Source request write enable for channel 0
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH1 : Source request write enable for channel 1
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH2 : Source request write enable for channel 2
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH3 : Source request write enable for channel 3
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
Destination Software Transaction Request Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Source request for channel 0
bits : 0 - -1 (0 bit)
access : read-write
CH1 : Source request for channel 1
bits : 1 - 0 (0 bit)
access : read-write
CH2 : Source request for channel 2
bits : 2 - 1 (0 bit)
access : read-write
CH3 : Source request for channel 3
bits : 3 - 2 (0 bit)
access : read-write
WE_CH0 : Source request write enable for channel 0
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH1 : Source request write enable for channel 1
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH2 : Source request write enable for channel 2
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH3 : Source request write enable for channel 3
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
Single Source Transaction Request Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Source request for channel 0
bits : 0 - -1 (0 bit)
access : read-write
CH1 : Source request for channel 1
bits : 1 - 0 (0 bit)
access : read-write
CH2 : Source request for channel 2
bits : 2 - 1 (0 bit)
access : read-write
CH3 : Source request for channel 3
bits : 3 - 2 (0 bit)
access : read-write
WE_CH0 : Source request write enable for channel 0
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH1 : Source request write enable for channel 1
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH2 : Source request write enable for channel 2
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH3 : Source request write enable for channel 3
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
Single Destination Transaction Request Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Source request for channel 0
bits : 0 - -1 (0 bit)
access : read-write
CH1 : Source request for channel 1
bits : 1 - 0 (0 bit)
access : read-write
CH2 : Source request for channel 2
bits : 2 - 1 (0 bit)
access : read-write
CH3 : Source request for channel 3
bits : 3 - 2 (0 bit)
access : read-write
WE_CH0 : Source request write enable for channel 0
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH1 : Source request write enable for channel 1
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH2 : Source request write enable for channel 2
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH3 : Source request write enable for channel 3
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
Last Source Transaction Request Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Source last request for channel 0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Not last transaction in current block
#1 : value2
Last transaction in current block
End of enumeration elements list.
CH1 : Source last request for channel 1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Not last transaction in current block
#1 : value2
Last transaction in current block
End of enumeration elements list.
CH2 : Source last request for channel 2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Not last transaction in current block
#1 : value2
Last transaction in current block
End of enumeration elements list.
CH3 : Source last request for channel 3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Not last transaction in current block
#1 : value2
Last transaction in current block
End of enumeration elements list.
WE_CH0 : Source last transaction request write enable for channel 0
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH1 : Source last transaction request write enable for channel 1
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH2 : Source last transaction request write enable for channel 2
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH3 : Source last transaction request write enable for channel 3
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
Last Destination Transaction Request Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Destination last request for channel 0
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Not last transaction in current block
#1 : value2
Last transaction in current block
End of enumeration elements list.
CH1 : Destination last request for channel 1
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Not last transaction in current block
#1 : value2
Last transaction in current block
End of enumeration elements list.
CH2 : Destination last request for channel 2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Not last transaction in current block
#1 : value2
Last transaction in current block
End of enumeration elements list.
CH3 : Destination last request for channel 3
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Not last transaction in current block
#1 : value2
Last transaction in current block
End of enumeration elements list.
WE_CH0 : Destination last transaction request write enable for channel 0
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH1 : Destination last transaction request write enable for channel 1
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH2 : Destination last transaction request write enable for channel 2
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
WE_CH3 : Destination last transaction request write enable for channel 3
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
#0 : value1
write disabled
#1 : value2
write enabled
End of enumeration elements list.
GPDMA Configuration Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_EN : GPDMA Enable bit.
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
GPDMA Disabled
#1 : value2
GPDMA Enabled.
End of enumeration elements list.
GPDMA Channel Enable Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH : Enables/Disables the channel
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0 : value1
Disable the Channel
#1 : value2
Enable the Channel
End of enumeration elements list.
WE_CH : Channel enable write enable
bits : 8 - 10 (3 bit)
access : write-only
GPDMA1 ID Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Hardcoded GPDMA Peripheral ID
bits : 0 - 30 (31 bit)
access : read-only
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