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address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
Input Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IR : Input Register
bits : 0 - 30 (31 bit)
access : read-write
CRC Length Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LENGTH : Message Length Register
bits : 0 - 14 (15 bit)
access : read-write
CRC Check Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHECK : CHECK Register
bits : 0 - 30 (31 bit)
access : read-write
CRC Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC : CRC Register
bits : 0 - 30 (31 bit)
access : read-write
CRC Test Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCM : Force CRC Mismatch
bits : 0 - -1 (0 bit)
access : read-write
FRM_CFG : Force CFG Register Mismatch
bits : 1 - 0 (0 bit)
access : read-write
FRM_CHECK : Force Check Register Mismatch
bits : 2 - 1 (0 bit)
access : read-write
CRC Result Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RES : Result Register
bits : 0 - 30 (31 bit)
access : read-only
CRC Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMI : CRC Mismatch Interrupt
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
CRC Mismatch Interrupt is disabled
#1 : value2
CRC Mismatch Interrupt is enabled
End of enumeration elements list.
CEI : Configuration Error Interrupt
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Configuration Error Interrupt is disabled
#1 : value2
Configuration Error Interrupt is enabled
End of enumeration elements list.
LEI : Length Error Interrupt
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Length Error Interrupt is disabled
#1 : value2
Length Error Interrupt is enabled
End of enumeration elements list.
BEI : Bus Error Interrupt
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Bus Error Interrupt is disabled
#1 : value2
Bus Error Interrupt is enabled
End of enumeration elements list.
CCE : CRC Check Comparison
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
CRC check comparison at the end of a message is disabled
#1 : value2
CRC check comparison at the end of a message is enabled
End of enumeration elements list.
ALR : Automatic Length Reload
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disables automatic reload of the LENGTH field.
#1 : value2
Enables automatic reload of the LENGTH field at the end of a message.
End of enumeration elements list.
REFIN : IR Byte Wise Reflection
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
IR Byte Wise Reflection is disabled
#1 : value2
IR Byte Wise Reflection is enabled
End of enumeration elements list.
REFOUT : CRC 32-Bit Wise Reflection
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : value1
CRC 32-bit wise is disabled
#1 : value2
CRC 32-bit wise is enabled
End of enumeration elements list.
XSEL : Selects the value to be xored with the final CRC
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : value1
0x00000000
#1 : value2
0xFFFFFFFF
End of enumeration elements list.
CRC Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMF : CRC Mismatch Flag
bits : 0 - -1 (0 bit)
access : read-write
CEF : Configuration Error Flag
bits : 1 - 0 (0 bit)
access : read-write
LEF : Length Error Flag
bits : 2 - 1 (0 bit)
access : read-write
BEF : Bus Error Flag
bits : 3 - 2 (0 bit)
access : read-write
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