\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
SCU Module ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD_REV : Module Revision
bits : 0 - 6 (7 bit)
access : read-only
MOD_TYPE : Module Type
bits : 8 - 14 (7 bit)
access : read-only
MOD_NUMBER : Module Number
bits : 16 - 30 (15 bit)
access : read-only
Startup Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HWCON : HW Configuration
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#00 : value1
Normal mode, JTAG
#01 : value2
ASC BSL enabled
#10 : value3
BMI customized boot enabled
#11 : value4
CAN BSL enabled
End of enumeration elements list.
SWCON : SW Configuration
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#0000 : value1
Normal mode, boot from Boot ROM
#0001 : value2
ASC BSL enabled
#0010 : value3
BMI customized boot enabled
#0011 : value4
CAN BSL enabled
#0100 : value5
Boot from Code SRAM
#1000 : value6
Boot from alternate Flash Address 0
#1100 : value7
Boot from alternate Flash Address 1
#1110 : value8
Enable fallback Alternate Boot Mode (ABM)
End of enumeration elements list.
General Purpose Register 0
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAT : User Data
bits : 0 - 30 (31 bit)
access : read-write
General Purpose Register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAT : User Data
bits : 0 - 30 (31 bit)
access : read-write
Chip ID Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDCHIP : Chip ID
bits : 0 - 30 (31 bit)
access : read-only
CCU Control Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GSC40 : Global Start Control CCU40
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disable
#1 : value2
Enable
End of enumeration elements list.
GSC41 : Global Start Control CCU41
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disable
#1 : value2
Enable
End of enumeration elements list.
GSC42 : Global Start Control CCU42
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disable
#1 : value2
Enable
End of enumeration elements list.
GSC43 : Global Start Control CCU43
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disable
#1 : value2
Enable
End of enumeration elements list.
GSC80 : Global Start Control CCU80
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disable
#1 : value2
Enable
End of enumeration elements list.
GSC81 : Global Start Control CCU81
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disable
#1 : value2
Enable
End of enumeration elements list.
Manufactory ID Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEPT : Department Identification Number
bits : 0 - 3 (4 bit)
access : read-only
MANUF : Manufacturer Identification Number
bits : 5 - 14 (10 bit)
access : read-only
Die Temperature Sensor Control Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWD : Sensor Power Down
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
The DTS is powered
#1 : value2
The DTS is not powered
End of enumeration elements list.
START : Sensor Measurement Start
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
No DTS measurement is started
#1 : value2
A DTS measurement is started
End of enumeration elements list.
OFFSET : Offset Calibration Value
bits : 4 - 9 (6 bit)
access : read-write
GAIN : Gain Calibration Value
bits : 11 - 15 (5 bit)
access : read-write
REFTRIM : Reference Trim Calibration Value
bits : 17 - 18 (2 bit)
access : read-write
BGTRIM : Bandgap Trim Calibration Value
bits : 20 - 22 (3 bit)
access : read-write
Die Temperature Sensor Status Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESULT : Result of the DTS Measurement
bits : 0 - 8 (9 bit)
access : read-only
RDY : Sensor Ready Status
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : value1
The DTS is not ready
#1 : value2
The DTS is ready
End of enumeration elements list.
BUSY : Sensor Busy Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : value1
not busy
#1 : value2
busy
End of enumeration elements list.
SD-MMC Delay Control Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TAPEN : Enable delay on the CMD/DAT out lines
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
TAPDEL : Number of Delay Elements Select
bits : 4 - 6 (3 bit)
access : read-write
Out of Range Comparator Enable Register 0
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENORC6 : Enable Out of Range Comparator, Channel 6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
ENORC7 : Enable Out of Range Comparator, Channel 7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
Out of Range Comparator Enable Register 1
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENORC6 : Enable Out of Range Comparator, Channel 6
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
ENORC7 : Enable Out of Range Comparator, Channel 7
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
Mirror Write Status Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HDCLR : HDCLR Mirror Register Write Status
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : value1
Ready
#1 : value2
Busy
End of enumeration elements list.
HDSET : HDSET Mirror Register Write Status
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Ready
#1 : value2
Busy
End of enumeration elements list.
HDCR : HDCR Mirror Register Write Status
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : value1
Ready
#1 : value2
Busy
End of enumeration elements list.
OSCSICTRL : OSCSICTRL Mirror Register Write Status
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : value1
Ready
#1 : value2
Busy
End of enumeration elements list.
OSCULCTRL : OSCULCTRL Mirror Register Write Status
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : value1
Ready
#1 : value2
Busy
End of enumeration elements list.
RTC_CTR : RTC CTR Mirror Register Write Status
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : value1
Ready
#1 : value2
Busy
End of enumeration elements list.
RTC_ATIM0 : RTC ATIM0 Mirror Register Write Status
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : value1
Ready
#1 : value2
Busy
End of enumeration elements list.
RTC_ATIM1 : RTC ATIM1 Mirror Register Write Status
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
#0 : value1
Ready
#1 : value2
Busy
End of enumeration elements list.
RTC_TIM0 : RTC TIM0 Mirror Register Write Status
bits : 11 - 10 (0 bit)
access : read-only
Enumeration:
#0 : value1
Ready
#1 : value2
Busy
End of enumeration elements list.
RTC_TIM1 : RTC TIM1 Mirror Register Write Status
bits : 12 - 11 (0 bit)
access : read-only
Enumeration:
#0 : value1
Ready
#1 : value2
Busy
End of enumeration elements list.
RMX : Retention Memory Access Register Update Status
bits : 13 - 12 (0 bit)
access : read-only
Enumeration:
#0 : value1
Ready
#1 : value2
Busy
End of enumeration elements list.
RTC_MSKSR : RTC MSKSSR Mirror Register Write Status
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : value1
Ready
#1 : value2
Busy
End of enumeration elements list.
RTC_CLRSR : RTC CLRSR Mirror Register Write Status
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : value1
Ready
#1 : value2
Busy
End of enumeration elements list.
Retention Memory Access Control Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDWR : Hibernate Retention Memory Register Update Control
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
transfer data from Retention Memory in Hibernate domain to RMDATA register
#1 : value2
transfer data from RMDATA into Retention Memory in Hibernate domain
End of enumeration elements list.
ADDR : Hibernate Retention Memory Register Address Select
bits : 16 - 18 (3 bit)
access : read-write
Retention Memory Access Data Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Hibernate Retention Memory Data
bits : 0 - 30 (31 bit)
access : read-write
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