\n
address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
SCU Service Request Status
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRWARN : WDT pre-warning Interrupt Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Inactive
#1 : value2
Active
End of enumeration elements list.
PI : RTC Periodic Interrupt Status
bits : 1 - 0 (0 bit)
access : read-only
AI : Alarm Interrupt Status
bits : 2 - 1 (0 bit)
access : read-only
DLROVR : DLR Request Overrun Interrupt Status
bits : 3 - 2 (0 bit)
access : read-only
HDCLR : HDCLR Mirror Register Update Status
bits : 17 - 16 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
HDSET : HDSET Mirror Register Update Status
bits : 18 - 17 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
HDCR : HDCR Mirror Register Update Status
bits : 19 - 18 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
OSCSICTRL : OSCSICTRL Mirror Register Update Status
bits : 21 - 20 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
OSCULCTRL : OSCULCTRL Mirror Register Update Status
bits : 23 - 22 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
RTC_CTR : RTC CTR Mirror Register Update Status
bits : 24 - 23 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
RTC_ATIM0 : RTC ATIM0 Mirror Register Update Status
bits : 25 - 24 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
RTC_ATIM1 : RTC ATIM1 Mirror Register Update Status
bits : 26 - 25 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
RTC_TIM0 : RTC TIM0 Mirror Register Update Status
bits : 27 - 26 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
RTC_TIM1 : RTC TIM1 Mirror Register Update Status
bits : 28 - 27 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
RMX : Retention Memory Mirror Register Update Status
bits : 29 - 28 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
SCU Service Request Set
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRWARN : WDT pre-warning Interrupt Set
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
set the status bit
End of enumeration elements list.
PI : RTC Periodic Interrupt Set
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
set the status bit
End of enumeration elements list.
AI : RTC Alarm Interrupt Set
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
set the status bit
End of enumeration elements list.
DLROVR : DLR Request Overrun Interrupt Set
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
set the status bit
End of enumeration elements list.
HDCRCLR : HDCRCLR Mirror Register Update Set
bits : 17 - 16 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
set the status bit
End of enumeration elements list.
HDCRSET : HDCRSET Mirror Register Update Set
bits : 18 - 17 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
set the status bit
End of enumeration elements list.
HDCR : HDCR Mirror Register Update Set
bits : 19 - 18 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
set the status bit
End of enumeration elements list.
OSCSICTRL : OSCSICTRL Mirror Register Update Set
bits : 21 - 20 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
set the status bit
End of enumeration elements list.
OSCULCTRL : OSCULCTRL Mirror Register Update Set
bits : 23 - 22 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
set the status bit
End of enumeration elements list.
RTC_CTR : RTC CTR Mirror Register Update Set
bits : 24 - 23 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
set the status bit
End of enumeration elements list.
RTC_ATIM0 : RTC ATIM0 Mirror Register Update Set
bits : 25 - 24 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
set the status bit
End of enumeration elements list.
RTC_ATIM1 : RTC ATIM1 Mirror Register Update Set
bits : 26 - 25 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
set the status bit
End of enumeration elements list.
RTC_TIM0 : RTC TIM0 Mirror Register Update Set
bits : 27 - 26 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
set the status bit
End of enumeration elements list.
RTC_TIM1 : RTC TIM1 Mirror Register Update Set
bits : 28 - 27 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
set the status bit
End of enumeration elements list.
RMX : Retention Memory Mirror Register Update Set
bits : 29 - 28 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
set the status bit
End of enumeration elements list.
SCU Service Request Mask
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRWARN : Promote Pre-Warning Interrupt Request to NMI Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
PI : Promote RTC Periodic Interrupt request to NMI Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
AI : Promote RTC Alarm Interrupt Request to NMI Request
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
ERU00 : Promote Channel 0 Interrupt of ERU0 Request to NMI Request
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
ERU01 : Promote Channel 1 Interrupt of ERU0 Request to NMI Request
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
ERU02 : Promote Channel 2 Interrupt of ERU0 Request to NMI Request
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
ERU03 : Promote Channel 3 Interrupt of ERU0 Request to NMI Request
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
SCU Raw Service Request Status
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRWARN : WDT pre-warning Interrupt Status Before Masking
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Inactive
#1 : value2
Active
End of enumeration elements list.
PI : RTC Raw Periodic Interrupt Status Before Masking
bits : 1 - 0 (0 bit)
access : read-only
AI : RTC Raw Alarm Interrupt Status Before Masking
bits : 2 - 1 (0 bit)
access : read-only
DLROVR : DLR Request Overrun Interrupt Status Before Masking
bits : 3 - 2 (0 bit)
access : read-only
HDCLR : HDCLR Mirror Register Update Status Before Masking
bits : 17 - 16 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
HDSET : HDSET Mirror Register Update Status Before Masking
bits : 18 - 17 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
HDCR : HDCR Mirror Register Update Status Before Masking
bits : 19 - 18 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
OSCSICTRL : OSCSICTRL Mirror Register Update Status Before Masking
bits : 21 - 20 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
OSCULCTRL : OSCULCTRL Mirror Register Update Status Before Masking
bits : 23 - 22 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
RTC_CTR : RTC CTR Mirror Register Update Status Before Masking
bits : 24 - 23 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
RTC_ATIM0 : RTC ATIM0 Mirror Register Update Status Before Masking
bits : 25 - 24 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
RTC_ATIM1 : RTC ATIM1 Mirror Register Update Status Before Masking
bits : 26 - 25 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
RTC_TIM0 : RTC TIM0 Mirror Register Update Before Masking Status
bits : 27 - 26 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
RTC_TIM1 : RTC TIM1 Mirror Register Update Status Before Masking
bits : 28 - 27 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
RMX : Retention Memory Mirror Register Update Status Before Masking
bits : 29 - 28 (0 bit)
access : read-only
Enumeration:
#0 : value1
Not updated
#1 : value2
Update completed
End of enumeration elements list.
SCU Service Request Mask
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRWARN : WDT pre-warning Interrupt Mask
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
PI : RTC Periodic Interrupt Mask
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
AI : RTC Alarm Interrupt Mask
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
DLROVR : DLR Request Overrun Interrupt Mask
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
HDCLR : HDCLR Mirror Register Update Mask
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
HDSET : HDSET Mirror Register Update Mask
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
HDCR : HDCR Mirror Register Update Mask
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
OSCSICTRL : OSCSICTRL Mirror Register Update Mask
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
OSCULCTRL : OSCULCTRL Mirror Register Update Mask
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
RTC_CTR : RTC CTR Mirror Register Update Mask
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
RTC_ATIM0 : RTC ATIM0 Mirror Register Update Mask
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
RTC_ATIM1 : RTC ATIM1 Mirror Register Update Mask
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
RTC_TIM0 : RTC TIM0 Mirror Register Update Mask
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
RTC_TIM1 : RTC TIM1 Mirror Register Update Mask
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
RMX : Retention Memory Mirror Register Update Mask
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disabled
#1 : value2
Enabled
End of enumeration elements list.
SCU Service Request Clear
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRWARN : WDT pre-warning Interrupt Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear the status bit
End of enumeration elements list.
PI : RTC Periodic Interrupt Clear
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear the status bit
End of enumeration elements list.
AI : RTC Alarm Interrupt Clear
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear the status bit
End of enumeration elements list.
DLROVR : DLR Request Overrun Interrupt clear
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear the status bit
End of enumeration elements list.
HDCLR : HDCLR Mirror Register Update Clear
bits : 17 - 16 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear the status bit
End of enumeration elements list.
HDSET : HDSET Mirror Register Update Clear
bits : 18 - 17 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear the status bit
End of enumeration elements list.
HDCR : HDCR Mirror Register Update Clear
bits : 19 - 18 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear the status bit
End of enumeration elements list.
OSCSICTRL : OSCSICTRL Mirror Register Update Clear
bits : 21 - 20 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear the status bit
End of enumeration elements list.
OSCULCTRL : OSCULCTRL Mirror Register Update Clear
bits : 23 - 22 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear the status bit
End of enumeration elements list.
RTC_CTR : RTC CTR Mirror Register Update Clear
bits : 24 - 23 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear the status bit
End of enumeration elements list.
RTC_ATIM0 : RTC ATIM0 Mirror Register Update Clear
bits : 25 - 24 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear the status bit
End of enumeration elements list.
RTC_ATIM1 : RTC ATIM1 Mirror Register Update Clear
bits : 26 - 25 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear the status bit
End of enumeration elements list.
RTC_TIM0 : RTC TIM0 Mirror Register Update Clear
bits : 27 - 26 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear the status bit
End of enumeration elements list.
RTC_TIM1 : RTC TIM1 Mirror Register Update Clear
bits : 28 - 27 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear the status bit
End of enumeration elements list.
RMX : Retention Memory Mirror Register Update Clear
bits : 29 - 28 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear the status bit
End of enumeration elements list.
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