\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
POSIF configuration
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSEL : Function Selector
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : value1
Hall Sensor Mode enabled
#01 : value2
Quadrature Decoder Mode enabled
#10 : value3
stand-alone Multi-Channel Mode enabled
#11 : value4
Quadrature Decoder and stand-alone Multi-Channel Mode enabled
End of enumeration elements list.
QDCM : Position Decoder Mode selection
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Position encoder is in Quadrature Mode
#1 : value2
Position encoder is in Direction Count Mode.
End of enumeration elements list.
HIDG : Idle generation enable
bits : 4 - 3 (0 bit)
access : read-write
MCUE : Multi-Channel Pattern SW update enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
Multi-Channel pattern update is controlled via HW
#1 : value2
Multi-Channel pattern update is controlled via SW
End of enumeration elements list.
INSEL0 : PhaseA/Hal input 1 selector
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : value1
POSIFx.IN0A
#01 : value2
POSIFx.IN0B
#10 : value3
POSIFx.IN0C
#11 : value4
POSIFx.IN0D
End of enumeration elements list.
INSEL1 : PhaseB/Hall input 2 selector
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#00 : value1
POSIFx.IN1A
#01 : value2
POSIFx.IN1B
#10 : value3
POSIFx.IN1C
#11 : value4
POSIFx.IN1D
End of enumeration elements list.
INSEL2 : Index/Hall input 3 selector
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#00 : value1
POSIFx.IN2A
#01 : value2
POSIFx.IN2B
#10 : value3
POSIFx.IN2C
#11 : value4
POSIFx.IN2D
End of enumeration elements list.
DSEL : Delay Pin selector
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
POSIFx.HSDA
#1 : value2
POSIFx.HSDB
End of enumeration elements list.
SPES : Edge selector for the sampling trigger
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
Rising edge
#1 : value2
Falling edge
End of enumeration elements list.
MSETS : Pattern update signal select
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#000 : value1
POSIFx.MSETA
#001 : value2
POSIFx.MSETB
#010 : value3
POSIFx.MSETC
#011 : value4
POSIFx.MSETD
#100 : value5
POSIFx.MSETE
#101 : value6
POSIFx.MSETF
#110 : value7
POSIFx.MSETG
#111 : value8
POSIFx.MSETH
End of enumeration elements list.
MSES : Multi-Channel pattern update trigger edge
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : value1
The signal used to enable a pattern update is active on the rising edge
#1 : value2
The signal used to enable a pattern update is active on the falling edge
End of enumeration elements list.
MSYNS : PWM synchronization signal selector
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#00 : value1
POSIFx.MSYNCA
#01 : value2
POSIFx.MSYNCB
#10 : value3
POSIFx.MSYNCC
#11 : value4
POSIFx.MSYNCD
End of enumeration elements list.
EWIS : Wrong Hall Event selection
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#00 : value1
POSIFx.EWHEA
#01 : value2
POSIFx.EWHEB
#10 : value3
POSIFx.EWHEC
#11 : value4
POSIFx.EWHED
End of enumeration elements list.
EWIE : External Wrong Hall Event enable
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : value1
External wrong hall event emulation signal, POSIFx.EWHE[D...A], is disabled
#1 : value2
External wrong hall event emulation signal, POSIFx.EWHE[D...A], is enabled.
End of enumeration elements list.
EWIL : External Wrong Hall Event active level
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : value1
POSIFx.EWHE[D...A] signal is active HIGH
#1 : value2
POSIFx.EWHE[D...A] signal is active LOW
End of enumeration elements list.
LPC : Low Pass Filters Configuration
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#000 : value1
Low pass filter disabled
#001 : value2
Low pass of 1 clock cycle
#010 : value3
Low pass of 2 clock cycles
#011 : value4
Low pass of 4 clock cycles
#100 : value5
Low pass of 8 clock cycles
#101 : value6
Low pass of 16 clock cycles
#110 : value7
Low pass of 32 clock cycles
#111 : value8
Low pass of 64 clock cycles
End of enumeration elements list.
POSIF Run Bit Status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB : Run Bit
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
IDLE
#1 : value2
Running
End of enumeration elements list.
POSIF Debug register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QCSV : Quadrature Decoder Current state
bits : 0 - 0 (1 bit)
access : read-only
QPSV : Quadrature Decoder Previous state
bits : 2 - 2 (1 bit)
access : read-only
IVAL : Current Index Value
bits : 4 - 3 (0 bit)
access : read-only
HSP : Hall Current Sampled Pattern
bits : 5 - 6 (2 bit)
access : read-only
LPP0 : Actual count of the Low Pass Filter for POSI0
bits : 8 - 12 (5 bit)
access : read-only
LPP1 : Actual count of the Low Pass Filter for POSI1
bits : 16 - 20 (5 bit)
access : read-only
LPP2 : Actual count of the Low Pass Filter for POSI2
bits : 22 - 26 (5 bit)
access : read-only
Module Identification register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODR : Module Revision
bits : 0 - 6 (7 bit)
access : read-only
MODT : Module Type
bits : 8 - 14 (7 bit)
access : read-only
MODN : Module Number
bits : 16 - 30 (15 bit)
access : read-only
Hall Sensor Patterns
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCP : Hall Current Pattern
bits : 0 - 1 (2 bit)
access : read-only
HEP : Hall Expected Pattern
bits : 3 - 4 (2 bit)
access : read-only
Hall Sensor Shadow Patterns
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCPS : Shadow Hall Current Pattern
bits : 0 - 1 (2 bit)
access : read-write
HEPS : Shadow Hall expected Pattern
bits : 3 - 4 (2 bit)
access : read-write
POSIF Suspend Config
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
QSUS : Quadrature Mode Suspend Config
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : value1
Suspend request ignored
#01 : value2
Stop immediately
#10 : value3
Suspend in the next index occurrence
#11 : value4
Suspend in the next phase (PhaseA or PhaseB) occurrence
End of enumeration elements list.
MSUS : Multi-Channel Mode Suspend Config
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#00 : value1
Suspend request ignored
#01 : value2
Stop immediately. Multi-Channel pattern is not set to the reset value.
#10 : value3
Stop immediately. Multi-Channel pattern is set to the reset value.
#11 : value4
Suspend with the synchronization of the PWM signal. Multi-Channel pattern is set to the reset value at the same time of the synchronization.
End of enumeration elements list.
Multi-Channel Pattern
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCMP : Multi-Channel Pattern
bits : 0 - 14 (15 bit)
access : read-only
Multi-Channel Shadow Pattern
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCMPS : Shadow Multi-Channel Pattern
bits : 0 - 14 (15 bit)
access : read-write
Multi-Channel Pattern Control set
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MNPS : Multi-Channel Pattern Update Enable Set
bits : 0 - -1 (0 bit)
access : write-only
STHR : Hall Pattern Shadow Transfer Request
bits : 1 - 0 (0 bit)
access : write-only
STMR : Multi-Channel Shadow Transfer Request
bits : 2 - 1 (0 bit)
access : write-only
Multi-Channel Pattern Control clear
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MNPC : Multi-Channel Pattern Update Enable Clear
bits : 0 - -1 (0 bit)
access : write-only
MPC : Multi-Channel Pattern clear
bits : 1 - 0 (0 bit)
access : write-only
Multi-Channel Pattern Control flag
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSS : Multi-Channel Pattern update status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Update of the Multi-Channel pattern is set
#1 : value2
Update of the Multi-Channel pattern is not set
End of enumeration elements list.
Quadrature Decoder Control
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PALS : Phase A Level selector
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Phase A is active HIGH
#1 : value2
Phase A is active LOW
End of enumeration elements list.
PBLS : Phase B Level selector
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Phase B is active HIGH
#1 : value2
Phase B is active LOW
End of enumeration elements list.
PHS : Phase signals swap
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Phase A is the leading signal for clockwise rotation
#1 : value2
Phase B is the leading signal for clockwise rotation
End of enumeration elements list.
ICM : Index Marker generations control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : value1
No index marker generation on POSIFx.OUT3
#01 : value2
Only first index occurrence generated on POSIFx.OUT3
#10 : value3
All index occurrences generated on POSIFx.OUT3
End of enumeration elements list.
DVAL : Current rotation direction
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : value1
Counterclockwise rotation
#1 : value2
Clockwise rotation
End of enumeration elements list.
POSIF Interrupt Flags
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHES : Correct Hall Event Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Correct Hall Event not detected
#1 : value2
Correct Hall Event detected
End of enumeration elements list.
WHES : Wrong Hall Event Status
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : value1
Wrong Hall Event not detected
#1 : value2
Wrong Hall Event detected
End of enumeration elements list.
HIES : Hall Inputs Update Status
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Transition on the Hall Inputs not detected
#1 : value2
Transition on the Hall Inputs detected
End of enumeration elements list.
MSTS : Multi-Channel pattern shadow transfer status
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : value1
Shadow transfer not done
#1 : value2
Shadow transfer done
End of enumeration elements list.
INDXS : Quadrature Index Status
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : value1
Index event not detected
#1 : value2
Index event detected
End of enumeration elements list.
ERRS : Quadrature Phase Error Status
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : value1
Phase Error event not detected
#1 : value2
Phase Error event detected
End of enumeration elements list.
CNTS : Quadrature CLK Status
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
#0 : value1
Quadrature clock not generated
#1 : value2
Quadrature clock generated
End of enumeration elements list.
DIRS : Quadrature Direction Change
bits : 11 - 10 (0 bit)
access : read-only
Enumeration:
#0 : value1
Change on direction not detected
#1 : value2
Change on direction detected
End of enumeration elements list.
PCLKS : Quadrature Period Clk Status
bits : 12 - 11 (0 bit)
access : read-only
Enumeration:
#0 : value1
Period clock not generated
#1 : value2
Period clock generated
End of enumeration elements list.
POSIF Interrupt Enable
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECHE : Correct Hall Event Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Correct Hall Event interrupt disabled
#1 : value2
Correct Hall Event interrupt enabled
End of enumeration elements list.
EWHE : Wrong Hall Event Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Wrong Hall Event interrupt disabled
#1 : value2
Wrong Hall Event interrupt enabled
End of enumeration elements list.
EHIE : Hall Input Update Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Update of the Hall Inputs interrupt is disabled
#1 : value2
Update of the Hall Inputs interrupt is enabled
End of enumeration elements list.
EMST : Multi-Channel pattern shadow transfer enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
Shadow transfer event interrupt disabled
#1 : value2
Shadow transfer event interrupt enabled
End of enumeration elements list.
EINDX : Quadrature Index Event Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
Index event interrupt disabled
#1 : value2
Index event interrupt enabled
End of enumeration elements list.
EERR : Quadrature Phase Error Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : value1
Phase error event interrupt disabled
#1 : value2
Phase error event interrupt enabled
End of enumeration elements list.
ECNT : Quadrature CLK interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : value1
Quadrature CLK event interrupt disabled
#1 : value2
Quadrature CLK event interrupt enabled
End of enumeration elements list.
EDIR : Quadrature direction change interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : value1
Direction change event interrupt disabled
#1 : value2
Direction change event interrupt enabled
End of enumeration elements list.
EPCLK : Quadrature Period CLK interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : value1
Quadrature Period CLK event interrupt disabled
#1 : value2
Quadrature Period CLK event interrupt enabled
End of enumeration elements list.
CHESEL : Correct Hall Event Service Request Selector
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
Correct Hall Event interrupt forward to POSIFx.SR0
#1 : value2
Correct Hall Event interrupt forward to POSIFx.SR1
End of enumeration elements list.
WHESEL : Wrong Hall Event Service Request Selector
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
Wrong Hall Event interrupt forward to POSIFx.SR0
#1 : value2
Wrong Hall Event interrupt forward to POSIFx.SR1
End of enumeration elements list.
HIESEL : Hall Inputs Update Event Service Request Selector
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : value1
Hall Inputs Update Event interrupt forward to POSIFx.SR0
#1 : value2
Hall Inputs Update Event interrupt forward to POSIFx.SR1
End of enumeration elements list.
MSTSEL : Multi-Channel pattern Update Event Service Request Selector
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : value1
Multi-Channel pattern Update Event interrupt forward to POSIFx.SR0
#1 : value2
Multi-Channel pattern Update Event interrupt forward to POSIFx.SR1
End of enumeration elements list.
INDSEL : Quadrature Index Event Service Request Selector
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : value1
Quadrature Index Event interrupt forward to POSIFx.SR0
#1 : value2
Quadrature Index Event interrupt forward to POSIFx.SR1
End of enumeration elements list.
ERRSEL : Quadrature Phase Error Event Service Request Selector
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : value1
Quadrature Phase error Event interrupt forward to POSIFx.SR0
#1 : value2
Quadrature Phase error Event interrupt forward to POSIFx.SR1
End of enumeration elements list.
CNTSEL : Quadrature Clock Event Service Request Selector
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : value1
Quadrature Clock Event interrupt forward to POSIFx.SR0
#1 : value2
Quadrature Clock Event interrupt forward to POSIFx.SR1
End of enumeration elements list.
DIRSEL : Quadrature Direction Update Event Service Request Selector
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : value1
Quadrature Direction Update Event interrupt forward to POSIFx.SR0
#1 : value2
Quadrature Direction Update Event interrupt forward to POSIFx.SR1
End of enumeration elements list.
PCLSEL : Quadrature Period clock Event Service Request Selector
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : value1
Quadrature Period clock Event interrupt forward to POSIFx.SR0
#1 : value2
Quadrature Period clock Event interrupt forward to POSIFx.SR1
End of enumeration elements list.
POSIF Interrupt Set
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCHE : Correct Hall Event flag set
bits : 0 - -1 (0 bit)
access : write-only
SWHE : Wrong Hall Event flag set
bits : 1 - 0 (0 bit)
access : write-only
SHIE : Hall Inputs Update Event flag set
bits : 2 - 1 (0 bit)
access : write-only
SMST : Multi-Channel Pattern shadow transfer flag set
bits : 4 - 3 (0 bit)
access : write-only
SINDX : Quadrature Index flag set
bits : 8 - 7 (0 bit)
access : write-only
SERR : Quadrature Phase Error flag set
bits : 9 - 8 (0 bit)
access : write-only
SCNT : Quadrature CLK flag set
bits : 10 - 9 (0 bit)
access : write-only
SDIR : Quadrature Direction flag set
bits : 11 - 10 (0 bit)
access : write-only
SPCLK : Quadrature period clock flag set
bits : 12 - 11 (0 bit)
access : write-only
POSIF Interrupt Clear
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCHE : Correct Hall Event flag clear
bits : 0 - -1 (0 bit)
access : write-only
RWHE : Wrong Hall Event flag clear
bits : 1 - 0 (0 bit)
access : write-only
RHIE : Hall Inputs Update Event flag clear
bits : 2 - 1 (0 bit)
access : write-only
RMST : Multi-Channel Pattern shadow transfer flag clear
bits : 4 - 3 (0 bit)
access : write-only
RINDX : Quadrature Index flag clear
bits : 8 - 7 (0 bit)
access : write-only
RERR : Quadrature Phase Error flag clear
bits : 9 - 8 (0 bit)
access : write-only
RCNT : Quadrature CLK flag clear
bits : 10 - 9 (0 bit)
access : write-only
RDIR : Quadrature Direction flag clear
bits : 11 - 10 (0 bit)
access : write-only
RPCLK : Quadrature period clock flag clear
bits : 12 - 11 (0 bit)
access : write-only
POSIF Run Bit Set
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRB : Set Run bit
bits : 0 - -1 (0 bit)
access : write-only
POSIF Run Bit Clear
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRB : Clear Run bit
bits : 0 - -1 (0 bit)
access : write-only
CSM : Clear Current internal status
bits : 1 - 0 (0 bit)
access : write-only
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