\n

System Clock Manager

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CLK_CONFIG

TRIM_CALC

CRYPT_CLK_CTRL_0_AES

CRYPT_CLK_CTRL_1_MAA

CRYPT_CLK_CTRL_2_PRNG

I2C_TIMER_CTRL

CLK_GATE_CTRL0

CLK_GATE_CTRL1

CLK_GATE_CTRL2

CM4_START_CLK_EN0

CM4_START_CLK_EN1

CM4_START_CLK_EN2

CLK_CTRL

SYS_CLK_CTRL_0_CM4

SYS_CLK_CTRL_1_SYNC

SYS_CLK_CTRL_2_SPIX

SYS_CLK_CTRL_3_PRNG

SYS_CLK_CTRL_4_WDT0

SYS_CLK_CTRL_5_WDT1

SYS_CLK_CTRL_6_GPIO

SYS_CLK_CTRL_7_PT

SYS_CLK_CTRL_8_UART

SYS_CLK_CTRL_9_I2CM

SYS_CLK_CTRL_10_I2CS

SYS_CLK_CTRL_11_SPI0

SYS_CLK_CTRL_12_SPI1

SYS_CLK_CTRL_13_SPI2

SYS_CLK_CTRL_14_SPIB

SYS_CLK_CTRL_15_OWM

INTFL

SYS_CLK_CTRL_16_SPIS

INTEN


CLK_CONFIG

System Clock Configuration
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CONFIG CLK_CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 crypto_enable crypto_stability_count

crypto_enable : Cryptographic (TPU) Relaxation Oscillator Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

crypto_stability_count : Crypto Oscillator Stability Select
bits : 4 - 11 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.


TRIM_CALC

Trim Calculation Controls
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIM_CALC TRIM_CALC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 trim_clk_sel trim_calc_start trim_calc_completed trim_enable trim_calc_results

trim_clk_sel : Trim Clock Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

trim_calc_start : Start Trim Calculation
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

trim_calc_completed : Trim Calculation Completed
bits : 2 - 4 (3 bit)
access : read-only

Enumeration:

End of enumeration elements list.

trim_enable : Trim Logic Enable
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

trim_calc_results : Trim Calculation Results
bits : 16 - 41 (26 bit)
access : read-only

Enumeration:

End of enumeration elements list.


CRYPT_CLK_CTRL_0_AES

Control Settings for Crypto Clock 0 - AES
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRYPT_CLK_CTRL_0_AES CRYPT_CLK_CTRL_0_AES read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 aes_clk_scale

aes_clk_scale : Control Settings for Crypto Clock 0 - AES
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CRYPT_CLK_CTRL_1_MAA

Control Settings for Crypto Clock 1 - MAA
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRYPT_CLK_CTRL_1_MAA CRYPT_CLK_CTRL_1_MAA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 maa_clk_scale

maa_clk_scale : Control Settings for Crypto Clock 1 - MAA
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CRYPT_CLK_CTRL_2_PRNG

Control Settings for Crypto Clock 2 - PRNG
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRYPT_CLK_CTRL_2_PRNG CRYPT_CLK_CTRL_2_PRNG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 prng_clk_scale

prng_clk_scale : Control Settings for Crypto Clock 2 - PRNG
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


I2C_TIMER_CTRL

I2C Timer Control
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_TIMER_CTRL I2C_TIMER_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i2c_1ms_timer_en

i2c_1ms_timer_en : I2C 1ms Timer Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CLK_GATE_CTRL0

Dynamic Clock Gating Control Register 0
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_GATE_CTRL0 CLK_GATE_CTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cm4_clk_gater ahb32_clk_gater icache_clk_gater flash_clk_gater sram_clk_gater apb_bridge_clk_gater sysman_clk_gater ptp_clk_gater ssb_mux_clk_gater pad_clk_gater spix_clk_gater pmu_clk_gater usb_clk_gater crc_clk_gater tpu_clk_gater watchdog0_clk_gater

cm4_clk_gater : Clock Gating Control for CM4 CPU
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ahb32_clk_gater : Clock Gating Control for AHB32
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

icache_clk_gater : Clock Gating Control for Instruction Cache
bits : 4 - 9 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

flash_clk_gater : Clock Gating Control for Flash Memory
bits : 6 - 13 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

sram_clk_gater : Clock Gating Control for SRAM
bits : 8 - 17 (10 bit)
access : read-write

Enumeration:

End of enumeration elements list.

apb_bridge_clk_gater : Clock Gating Control for AHB-to-APB Bridge
bits : 10 - 21 (12 bit)
access : read-write

Enumeration:

End of enumeration elements list.

sysman_clk_gater : Clock Gating Control for CLKMAN, PWRMAN, and IOMAN
bits : 12 - 25 (14 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ptp_clk_gater : Clock Gating Control for PTP Logic
bits : 14 - 29 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ssb_mux_clk_gater : Clock Gating Control for SSB Mux
bits : 16 - 33 (18 bit)
access : read-write

Enumeration:

End of enumeration elements list.

pad_clk_gater : Clock Gating Control for Pad Mode Filter
bits : 18 - 37 (20 bit)
access : read-write

Enumeration:

End of enumeration elements list.

spix_clk_gater : Clock Gating Control for SPI XIP
bits : 20 - 41 (22 bit)
access : read-write

Enumeration:

End of enumeration elements list.

pmu_clk_gater : Clock Gating Control for PMU
bits : 22 - 45 (24 bit)
access : read-write

Enumeration:

End of enumeration elements list.

usb_clk_gater : Clock Gating Control for USB
bits : 24 - 49 (26 bit)
access : read-write

Enumeration:

End of enumeration elements list.

crc_clk_gater : Clock Gating Control for CRC
bits : 26 - 53 (28 bit)
access : read-write

Enumeration:

End of enumeration elements list.

tpu_clk_gater : Clock Gating Control for TPU
bits : 28 - 57 (30 bit)
access : read-write

Enumeration:

End of enumeration elements list.

watchdog0_clk_gater : Clock Gating Control for Watchdog Timer 0
bits : 30 - 61 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CLK_GATE_CTRL1

Dynamic Clock Gating Control Register 1
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_GATE_CTRL1 CLK_GATE_CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 watchdog1_clk_gater gpio_clk_gater timer0_clk_gater timer1_clk_gater timer2_clk_gater timer3_clk_gater timer4_clk_gater timer5_clk_gater pulsetrain_clk_gater uart0_clk_gater uart1_clk_gater uart2_clk_gater uart3_clk_gater i2cm0_clk_gater i2cm1_clk_gater i2cm2_clk_gater

watchdog1_clk_gater : Clock Gating Control for Watchdog Timer 1
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

gpio_clk_gater : Clock Gating Control for GPIO Ports
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

timer0_clk_gater : Clock Gating Control for Timer/Counter Module 0
bits : 4 - 9 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

timer1_clk_gater : Clock Gating Control for Timer/Counter Module 1
bits : 6 - 13 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

timer2_clk_gater : Clock Gating Control for Timer/Counter Module 2
bits : 8 - 17 (10 bit)
access : read-write

Enumeration:

End of enumeration elements list.

timer3_clk_gater : Clock Gating Control for Timer/Counter Module 3
bits : 10 - 21 (12 bit)
access : read-write

Enumeration:

End of enumeration elements list.

timer4_clk_gater : Clock Gating Control for Timer/Counter Module 4
bits : 12 - 25 (14 bit)
access : read-write

Enumeration:

End of enumeration elements list.

timer5_clk_gater : Clock Gating Control for Timer/Counter Module 5
bits : 14 - 29 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

pulsetrain_clk_gater : Clock Gating Control for Pulse Train Generators
bits : 16 - 33 (18 bit)
access : read-write

Enumeration:

End of enumeration elements list.

uart0_clk_gater : Clock Gating Control for UART 0
bits : 18 - 37 (20 bit)
access : read-write

Enumeration:

End of enumeration elements list.

uart1_clk_gater : Clock Gating Control for UART 1
bits : 20 - 41 (22 bit)
access : read-write

Enumeration:

End of enumeration elements list.

uart2_clk_gater : Clock Gating Control for UART 2
bits : 22 - 45 (24 bit)
access : read-write

Enumeration:

End of enumeration elements list.

uart3_clk_gater : Clock Gating Control for UART 3
bits : 24 - 49 (26 bit)
access : read-write

Enumeration:

End of enumeration elements list.

i2cm0_clk_gater : Clock Gating Control for I2C Master 0
bits : 26 - 53 (28 bit)
access : read-write

Enumeration:

End of enumeration elements list.

i2cm1_clk_gater : Clock Gating Control for I2C Master 1
bits : 28 - 57 (30 bit)
access : read-write

Enumeration:

End of enumeration elements list.

i2cm2_clk_gater : Clock Gating Control for I2C Master 2
bits : 30 - 61 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CLK_GATE_CTRL2

Dynamic Clock Gating Control Register 2
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_GATE_CTRL2 CLK_GATE_CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i2cs_clk_gater spi0_clk_gater spi1_clk_gater spi2_clk_gater spi_bridge_clk_gater owm_clk_gater adc_clk_gater spis_clk_gater

i2cs_clk_gater : Clock Gating Control for I2C Slave
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

spi0_clk_gater : Clock Gating Control for SPI Master 0
bits : 2 - 5 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

spi1_clk_gater : Clock Gating Control for SPI Master 1
bits : 4 - 9 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

spi2_clk_gater : Clock Gating Control for SPI Master 2
bits : 6 - 13 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

spi_bridge_clk_gater : Clock Gating Control for SPI Bridge
bits : 8 - 17 (10 bit)
access : read-write

Enumeration:

End of enumeration elements list.

owm_clk_gater : Clock Gating Control for 1-Wire Master (OWM)
bits : 10 - 21 (12 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_clk_gater : Clock Gating Control for ADC
bits : 12 - 25 (14 bit)
access : read-write

Enumeration:

End of enumeration elements list.

spis_clk_gater : Clock Gating Control for SPI Slave
bits : 14 - 29 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CM4_START_CLK_EN0

CM4 Start Clock on Interrupt Enable 0
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CM4_START_CLK_EN0 CM4_START_CLK_EN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ints

ints : Interrupt Sources 0-31
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CM4_START_CLK_EN1

CM4 Start Clock on Interrupt Enable 1
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CM4_START_CLK_EN1 CM4_START_CLK_EN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ints

ints : Interrupt Sources 32-63
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CM4_START_CLK_EN2

CM4 Start Clock on Interrupt Enable 2
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CM4_START_CLK_EN2 CM4_START_CLK_EN2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ints

ints : Interrupt Sources 95-64
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CLK_CTRL

System Clock Controls
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CTRL CLK_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 system_source_select usb_clock_enable usb_clock_select crypto_clock_enable rtos_mode cpu_dynamic_clock wdt0_clock_enable wdt0_clock_select wdt1_clock_enable wdt1_clock_select adc_clock_enable

system_source_select : System Clock Source Select
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

usb_clock_enable : USB Clock Enable
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

usb_clock_select : USB Clock Select
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

crypto_clock_enable : Crypto Clock Enable
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

End of enumeration elements list.

rtos_mode : Enable RTOS Mode for SysTick Timers
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

End of enumeration elements list.

cpu_dynamic_clock : Enable CPU Dynamic Clock Gating
bits : 13 - 26 (14 bit)
access : read-write

Enumeration:

End of enumeration elements list.

wdt0_clock_enable : Watchdog 0 Clock Enable
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

End of enumeration elements list.

wdt0_clock_select : Watchdog 0 Clock Source Select
bits : 17 - 35 (19 bit)
access : read-write

Enumeration:

End of enumeration elements list.

wdt1_clock_enable : Watchdog 1 Clock Enable
bits : 20 - 40 (21 bit)
access : read-write

Enumeration:

End of enumeration elements list.

wdt1_clock_select : Watchdog 1 Clock Source Select
bits : 21 - 43 (23 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_clock_enable : ADC Clock Enable
bits : 24 - 48 (25 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SYS_CLK_CTRL_0_CM4

Control Settings for CLK0 - Cortex M4 Clock
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CLK_CTRL_0_CM4 SYS_CLK_CTRL_0_CM4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cm4_clk_scale

cm4_clk_scale : Control Settings for CLK0 - Cortex M4 Clock
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SYS_CLK_CTRL_1_SYNC

Control Settings for CLK1 - Synchronizer Clock
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CLK_CTRL_1_SYNC SYS_CLK_CTRL_1_SYNC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sync_clk_scale

sync_clk_scale : Control Settings for CLK1 - Synchronizer Clock
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SYS_CLK_CTRL_2_SPIX

Control Settings for CLK2 - SPI XIP Clock
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CLK_CTRL_2_SPIX SYS_CLK_CTRL_2_SPIX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 spix_clk_scale

spix_clk_scale : Control Settings for CLK2 - SPI XIP Clock
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SYS_CLK_CTRL_3_PRNG

Control Settings for CLK3 - PRNG Clock
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CLK_CTRL_3_PRNG SYS_CLK_CTRL_3_PRNG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 prng_clk_scale

prng_clk_scale : Control Settings for CLK3 - PRNG Clock
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SYS_CLK_CTRL_4_WDT0

Control Settings for CLK4 - Watchdog Timer 0
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CLK_CTRL_4_WDT0 SYS_CLK_CTRL_4_WDT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 watchdog0_clk_scale

watchdog0_clk_scale : Control Settings for CLK4 - Watchdog Timer 0
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SYS_CLK_CTRL_5_WDT1

Control Settings for CLK5 - Watchdog Timer 1
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CLK_CTRL_5_WDT1 SYS_CLK_CTRL_5_WDT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 watchdog1_clk_scale

watchdog1_clk_scale : Control Settings for CLK5 - Watchdog Timer 1
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SYS_CLK_CTRL_6_GPIO

Control Settings for CLK6 - Clock for GPIO Ports
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CLK_CTRL_6_GPIO SYS_CLK_CTRL_6_GPIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 gpio_clk_scale

gpio_clk_scale : Control Settings for CLK6 - Clock for GPIO Ports
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SYS_CLK_CTRL_7_PT

Control Settings for CLK7 - Source Clock for All Pulse Trains
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CLK_CTRL_7_PT SYS_CLK_CTRL_7_PT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pulse_train_clk_scale

pulse_train_clk_scale : Control Settings for CLK7 - Source Clock for All Pulse Trains
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SYS_CLK_CTRL_8_UART

Control Settings for CLK8 - Source Clock for All UARTs
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CLK_CTRL_8_UART SYS_CLK_CTRL_8_UART read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uart_clk_scale

uart_clk_scale : Control Settings for CLK8 - Source Clock for All UARTs
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SYS_CLK_CTRL_9_I2CM

Control Settings for CLK9 - Source Clock for All I2C Masters
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CLK_CTRL_9_I2CM SYS_CLK_CTRL_9_I2CM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i2cm_clk_scale

i2cm_clk_scale : Control Settings for CLK9 - Source Clock for All I2C Masters
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SYS_CLK_CTRL_10_I2CS

Control Settings for CLK10 - Source Clock for I2C Slave
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CLK_CTRL_10_I2CS SYS_CLK_CTRL_10_I2CS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i2cs_clk_scale

i2cs_clk_scale : Control Settings for CLK10 - Source Clock for I2C Slave
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SYS_CLK_CTRL_11_SPI0

Control Settings for CLK11 - SPI Master 0
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CLK_CTRL_11_SPI0 SYS_CLK_CTRL_11_SPI0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 spi0_clk_scale

spi0_clk_scale : Control Settings for CLK11 - SPI Master 0
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SYS_CLK_CTRL_12_SPI1

Control Settings for CLK12 - SPI Master 1
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CLK_CTRL_12_SPI1 SYS_CLK_CTRL_12_SPI1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 spi1_clk_scale

spi1_clk_scale : Control Settings for CLK12 - SPI Master 1
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SYS_CLK_CTRL_13_SPI2

Control Settings for CLK13 - SPI Master 2
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CLK_CTRL_13_SPI2 SYS_CLK_CTRL_13_SPI2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 spi2_clk_scale

spi2_clk_scale : Control Settings for CLK13 - SPI Master 2
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SYS_CLK_CTRL_14_SPIB

Control Settings for CLK14 - SPI Bridge Clock
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CLK_CTRL_14_SPIB SYS_CLK_CTRL_14_SPIB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 spib_clk_scale

spib_clk_scale : Control Settings for CLK14 - SPI Bridge Clock
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SYS_CLK_CTRL_15_OWM

Control Settings for CLK15 - 1-Wire Master Clock
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CLK_CTRL_15_OWM SYS_CLK_CTRL_15_OWM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 owm_clk_scale

owm_clk_scale : Control Settings for CLK15 - 1-Wire Master Clock
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


INTFL

Interrupt Flags
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFL INTFL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 crypto_stable sys_ro_stable

crypto_stable : Crypto Oscillator Stable Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

sys_ro_stable : System Oscillator Stable Interrupt Flag
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.


SYS_CLK_CTRL_16_SPIS

Control Settings for CLK16 - SPI Slave Clock
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_CLK_CTRL_16_SPIS SYS_CLK_CTRL_16_SPIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 spis_clk_scale

spis_clk_scale : Control Settings for CLK16 - SPI Slave Clock
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.


INTEN

Interrupt Enable/Disable Controls
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 crypto_stable sys_ro_stable

crypto_stable : Crypto Oscillator Stable Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

sys_ro_stable : System Oscillator Stable Interrupt Enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.



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