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PMU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DSCADR

DSC1

DSC2

DSC3

DSC4

CFG

LOOP

OP


DSCADR

Starting Descriptor Address
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSCADR DSCADR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DSC1

Current Descriptor DWORD 1
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSC1 DSC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DSC2

Current Descriptor DWORD 2
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSC2 DSC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DSC3

Current Descriptor DWORD 3
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSC3 DSC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DSC4

Current Descriptor DWORD 4
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSC4 DSC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CFG

Channel Configuration
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 enable ll_stopped manual bus_error to_stat to_sel ps_sel interrupt int_en burst_size

enable : PMU Channel Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ll_stopped : Linked List Engine Status
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

manual : Manual Mode Enable
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

bus_error : AHB Bus Error Interrupt Flag
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

to_stat : AHB Bus Timeout Interrupt Flag
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

to_sel : Time Out Interval Select
bits : 11 - 24 (14 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ps_sel : Time Out Interval Prescale Select
bits : 14 - 29 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

interrupt : Descriptor Interrupt Flag
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

End of enumeration elements list.

int_en : PMU Channel Interrupt Enable
bits : 17 - 34 (18 bit)
access : read-write

Enumeration:

End of enumeration elements list.

burst_size : DMA Maximum Burst Size
bits : 24 - 52 (29 bit)
access : read-write

Enumeration:

End of enumeration elements list.


LOOP

Channel Loop Counters
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOOP LOOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 counter_0 counter_1

counter_0 : CH1 Loop Counter 1
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

counter_1 : CH1 Loop Counter 0
bits : 16 - 47 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.


OP

Current Descriptor DWORD 0 (OP)
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OP OP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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