Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
WDT0 - Watchdog Timer Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
int_period : Period from WDT Clear to Interrupt Flag Set
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : 2_31_CLKS
2^31 WDT clocks
1 : 2_30_CLKS
2^30 WDT clocks
2 : 2_29_CLKS
2^29 WDT clocks
3 : 2_28_CLKS
2^28 WDT clocks
4 : 2_27_CLKS
2^27 WDT clocks
5 : 2_26_CLKS
2^26 WDT clocks
6 : 2_25_CLKS
2^25 WDT clocks
7 : 2_24_CLKS
2^24 WDT clocks
8 : 2_23_CLKS
2^23 WDT clocks
9 : 2_22_CLKS
2^22 WDT clocks
10 : 2_21_CLKS
2^21 WDT clocks
11 : 2_20_CLKS
2^20 WDT clocks
12 : 2_19_CLKS
2^19 WDT clocks
13 : 2_18_CLKS
2^18 WDT clocks
14 : 2_17_CLKS
2^17 WDT clocks
15 : 2_16_CLKS
2^16 WDT clocks
End of enumeration elements list.
rst_period : Period from WDT Clear to Reset Flag Set
bits : 4 - 11 (8 bit)
access : read-write
Enumeration:
0 : 2_31_CLKS
2^31 WDT clocks.
1 : 2_30_CLKS
2^30 WDT clocks.
2 : 2_29_CLKS
2^29 WDT clocks.
3 : 2_28_CLKS
2^28 WDT clocks.
4 : 2_27_CLKS
2^27 WDT clocks.
5 : 2_26_CLKS
2^26 WDT clocks.
6 : 2_25_CLKS
2^25 WDT clocks.
7 : 2_24_CLKS
2^24 WDT clocks.
8 : 2_23_CLKS
2^23 WDT clocks.
9 : 2_22_CLKS
2^22 WDT clocks.
10 : 2_21_CLKS
2^21 WDT clocks.
11 : 2_20_CLKS
2^20 WDT clocks.
12 : 2_19_CLKS
2^19 WDT clocks.
13 : 2_18_CLKS
2^18 WDT clocks.
14 : 2_17_CLKS
2^17 WDT clocks.
15 : 2_16_CLKS
2^16 WDT clocks.
End of enumeration elements list.
en_timer : Watchdg Timer Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
en_clock : Watchdog Clock Gate
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
0 : DISABLE
WDT Clock Gate Control Disable
1 : ENABLE
WDT Clock Gate Control Enable
End of enumeration elements list.
wait_period : Period from WDT Clear to Clear Window Begin
bits : 12 - 27 (16 bit)
access : read-write
Enumeration:
0 : 2_31_CLKS
2^31 WDT clocks.
1 : 2_30_CLKS
2^30 WDT clocks.
2 : 2_29_CLKS
2^29 WDT clocks.
3 : 2_28_CLKS
2^28 WDT clocks.
4 : 2_27_CLKS
2^27 WDT clocks
5 : 2_26_CLKS
2^26 WDT clocks
6 : 2_25_CLKS
2^25 WDT clocks
7 : 2_24_CLKS
2^24 WDT clocks
8 : 2_23_CLKS
2^23 WDT clocks
9 : 2_22_CLKS
2^22 WDT clocks.
10 : 2_21_CLKS
2^21 WDT clocks.
11 : 2_20_CLKS
2^20 WDT clocks.
12 : 2_19_CLKS
2^19 WDT clocks.
13 : 2_18_CLKS
2^18 WDT clocks.
14 : 2_17_CLKS
2^17 WDT clocks.
15 : 2_16_CLKS
2^16 WDT clocks.
End of enumeration elements list.
WDT0 - Register Setting Lock for WDT0_CTRL
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
wdlock : Lock for WDT CTRL Register
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
End of enumeration elements list.
WDT0 - Watchdog Clear Register (Feed Dog)
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT0 - Watchdog Interrupt and Reset Flags
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
timeout : Watchdog Timeout Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
pre_win : Watchdog Pre-Window Clear Interrupt Flag
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
End of enumeration elements list.
reset_out : Watchdog Reset Flag
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
End of enumeration elements list.
WDT0 - Interrupt/Reset Enable/Disable Controls
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
timeout : Enable Watchdog Interrupt
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
pre_win : Enable Watchdog Pre-Window Reset Interrupt
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
End of enumeration elements list.
reset_out : Enable Watchdog Reset Output
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
End of enumeration elements list.
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