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1-Wire Master

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CFG

INTFL

INTEN

CLK_DIV_1US

CTRL_STAT

DATA


CFG

1-Wire Master Configuration
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 long_line_mode force_pres_det bit_bang_en ext_pullup_mode ext_pullup_enable single_bit_mode overdrive int_pullup_enable

long_line_mode : Long Line Mode
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

force_pres_det : Force Line During Presence Detect
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

bit_bang_en : Bit Bang Enable
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ext_pullup_mode : Provide an extra output to control an external pullup.
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ext_pullup_enable : Enable External Pullup
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

single_bit_mode : Enable Single Bit TX/RX Mode
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

overdrive : Enables overdrive speed for 1-Wire operations.
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

int_pullup_enable : Enable internal pullup.
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.


INTFL

1-Wire Master Interrupt Flags
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFL INTFL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ow_reset_done tx_data_empty rx_data_ready line_short line_low

ow_reset_done : OW Reset Sequence Completed
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

tx_data_empty : Tx Data Empty Interrupt Flag
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

rx_data_ready : Rx Data Ready Interrupt Flag
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

line_short : OW Line Short Detected Interrupt Flag
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

line_low : OW Line Low Detected Interrupt Flag
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.


INTEN

1-Wire Master Interrupt Enables
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ow_reset_done tx_data_empty rx_data_ready line_short line_low

ow_reset_done : OW Reset Sequence Completed
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

tx_data_empty : Tx Data Empty Interrupt Enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

rx_data_ready : Rx Data Ready Interrupt Enable
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

line_short : OW Line Short Detected Interrupt Enable
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

line_low : OW Line Low Detected Interrupt Enable
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CLK_DIV_1US

1-Wire Master Clock Divisor
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_DIV_1US CLK_DIV_1US read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 divisor

divisor : Clock Divisor for 1MHz
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.


CTRL_STAT

1-Wire Master Control/Status
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_STAT CTRL_STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 start_ow_reset sra_mode bit_bang_oe ow_input presence_detect

start_ow_reset : Start OW Reset
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

sra_mode : SRA Mode
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

bit_bang_oe : Bit Bang Output Enable
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ow_input : OW Input State
bits : 3 - 6 (4 bit)
access : read-only

Enumeration:

End of enumeration elements list.

presence_detect : Presence Pulse Detected
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.


DATA

1-Wire Master Data Buffer
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tx_rx

tx_rx : Tx/Rx Buffer
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.



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