Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x60 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x70 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xB4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
System Power-down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTEN : HXT Enable Bit (Write Protect)\nNote1 : reset by power on reset\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Eexternal high speed crystal (HXT) Disabled
#1 : 1
External high speed crystal (HXT) Enabled
End of enumeration elements list.
LXTEN : LXT Enable Bit (Write Protect)\nNote1 : \nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
External low speed crystal (LXT) Disabled
#1 : 1
External low speed crystal (LXT) Enabled
End of enumeration elements list.
HIRCEN : HIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal high speed RC oscillator (HIRC) Disabled
#1 : 1
Internal high speed RC oscillator (HIRC) Enabled
End of enumeration elements list.
LIRCEN : LIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal low speed RC oscillator (LIRC) Disabled
#1 : 1
Internal low speed RC oscillator (LIRC) Enabled
End of enumeration elements list.
PDWKDLY : Enable the Wake-up Delay Counter (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip works at external high speed crystal oscillator (HXT), and 512 clock cycles when chip works at internal high speed RC oscillator (HIRC).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock cycles delay Disabled
#1 : 1
Clock cycles delay Enabled
End of enumeration elements list.
PDWKIEN : Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote 1: The interrupt will occur when both PDWKIF and PDWKIEN are high.\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power-down mode wake-up interrupt Disabled
#1 : 1
Power-down mode wake-up interrupt Enabled
End of enumeration elements list.
PDWKIF : Power-down Mode Wake-up Interrupt Status\nSet by 'Power-down wake-up event', it indicates that resume from Power-down mode' \nThe flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter.\nNote 1: Write 1 to clear the bit to 0.\nNote 2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
bits : 6 - 6 (1 bit)
access : read-write
PDEN : System Power-down Enable (Write Protect)
When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down.
In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. If user disable LIRC before entering power-down mode, this bit should be set after LIRC disabled 50us.
In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip operating normally or chip in idle mode because of WFI command
#1 : 1
Chip enters Power-down mode instant or wait CPU sleep command WFI
End of enumeration elements list.
HXTGAIN : HXT Gain Control Bit (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nGain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off. \nOthers: Reserved \nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
HXT frequency is lower than from 4 MHz
#001 : 1
HXT frequency is from 4 MHz to 8 MHz
#010 : 2
HXT frequency is from 8 MHz to 12 MHz
#011 : 3
HXT frequency is from 12 MHz to 16 MHz
#100 : 4
HXT frequency is from 16 MHz to 24 MHz
#111 : 7
HXT frequency is from 24 MHz to 32 MHz
End of enumeration elements list.
LXTSELXT : LXT Mode Selection\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
LXT work as crystal mode. PF.4 and PF.5 are configured as external low speed crystal (LXT) pins
#1 : 1
LXT work as external clock mode. PF.5 is configured as external clock input pin
End of enumeration elements list.
LXTGAIN : LXT Gain Control Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 25 - 26 (2 bit)
access : read-write
Enumeration:
#00 : 0
LXT Crystal ESR = 35K, CL=12.5pF
#10 : 2
LXT Crystal ESR = 70K, CL=12.5pF
End of enumeration elements list.
Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKSEL : HCLK Clock Source Selection (Write Protect)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turned on.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote : reset by power on reset\nNote: If PLL is not supported, clock source of selection '010' will be changed to HIRC. \nNote: If LXT or HXT is not supported, clock source of selection '000'or '001' will be kept previous clock selection.\nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HXT
#001 : 1
Clock source from LXT
#010 : 2
Clock source from PLL
#011 : 3
Clock source from LIRC
#111 : 7
Clock source from HIRC
End of enumeration elements list.
STCLKSEL : Cortex-M0 SysTick Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote: If LXT or HXT is not supported, clock source of selection '000', '001', or '010' will be stopped. \nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HXT
#001 : 1
Clock source from LXT
#010 : 2
Clock source from HXT/2
#011 : 3
Clock source from HCLK/2
#111 : 7
Clock source from HIRC/2
End of enumeration elements list.
USBDSEL : USB Device Clock Source Selection (Write Protect)\nThese bits are protected bit. It means programming this bit needs to write '59h', '16h', '88h' to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.\nNote: If PLL is not supported, clock source of selection '1' will be changed to HIRC. \nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from HIRC
#1 : 1
Clock source from PLL divided
End of enumeration elements list.
Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTSEL : Watchdog Timer Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. 2. Will be forced to 11 when CONFIG0[31], CONFIG0[4], CONFIG0[3] are all ones.\nNote: If LXT is not supported, clock source of selection '01' will be stopped. \nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved.
#01 : 1
Clock source from external low speed crystal oscillator (LXT)
#10 : 2
Clock source from HCLK/2048
#11 : 3
Clock source from internal low speed RC oscillator (LIRC)
End of enumeration elements list.
WWDTSEL : Window Watchdog Timer Clock Source Selection (Write Protect)
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#10 : 2
Clock source from HCLK/2048
#11 : 3
Clock source from internal low speed RC oscillator (LIRC)
End of enumeration elements list.
CLKOSEL : Clock Divider Clock Source Selection\nNote: If PLL is not supported, clock source of selection '110' will be changed to HIRC.\nNote: If LXT or HXT is not supported, clock source of selection '000' or '001' will be stopped. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from external low speed crystal oscillator (LXT)
#010 : 2
Clock source from HCLK
#011 : 3
Clock source from internal high speed RC oscillator (HIRC)
#100 : 4
Clock source from internal low speed RC oscillator (LIRC)
#101 : 5
Clock source from internal high speed RC oscillator (HIRC)
#110 : 6
Clock source from PLL
End of enumeration elements list.
TMR0SEL : TIMER0 Clock Source Selection\nNote: If LXT or HXT is not supported, clock source of selection '000' or '001' will be stopped. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK0
#011 : 3
Clock source from external clock TM0 pin
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
TMR1SEL : TIMER1 Clock Source Selection\nNote: If LXT or HXT is not supported, clock source of selection '000' or '001' will be stopped. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK0
#011 : 3
Clock source from external clock TM1 pin
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
TMR2SEL : TIMER2 Clock Source Selection\nNote: If LXT or HXT is not supported, clock source of selection '000' or '001' will be stopped. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK1
#011 : 3
Clock source from external clock TM2 pin
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
TMR3SEL : TIMER3 Clock Source Selection\nNote: If LXT or HXT is not supported, clock source of selection '000' or '001' will be stopped. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK1
#011 : 3
Clock source from external clock TM3 pin
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
UART0SEL : UART0 Clock Source Selection\nNote: If PLL is not supported, clock source of selection '001' will be changed to PCLK0.\nNote: If LXT or HXT is not supported, clock source of selection '000' or '010' will be stopped. \nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from PLL
#010 : 2
Clock source from external low speed crystal oscillator (LXT)
#011 : 3
Clock source from internal high speed RC oscillator (HIRC)
#100 : 4
Clock source from PCLK0
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
End of enumeration elements list.
UART1SEL : UART1 Clock Source Selection\nNote: If PLL is not supported, clock source of selection '001' will be changed to PCLK1.\nNote: If LXT or HXT is not supported, clock source of selection '000' or '010' will be stopped. \nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from PLL
#010 : 2
Clock source from external low speed crystal oscillator (LXT)
#011 : 3
Clock source from internal high speed RC oscillator (HIRC)
#100 : 4
Clock source from PCLK1
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
End of enumeration elements list.
Clock Source Select Control Register 2
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM0SEL : PWM0 Clock Source Selection\nThe peripheral clock source of PWM0 is defined by PWM0SEL. \nNote: If PLL is not supported, clock source of selection '0' will be changed to PCLK0.\nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from PLL
#1 : 1
Clock source from PCLK0
End of enumeration elements list.
PWM1SEL : PWM1 Clock Source Selection\nThe peripheral clock source of PWM1 is defined by PWM1SEL. \nNote: If PLL is not supported, clock source of selection '0' will be changed to PCLK1.\nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from PLL
#1 : 1
Clock source from PCLK1
End of enumeration elements list.
QSPI0SEL : QSPI0 Clock Source Selection\nNote: If PLL is not supported, clock source of selection '01' will be changed to PCLK0.\nNote: If HXT is not supported, clock source of selection '00' will be stopped.\nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from PCLK0
#11 : 3
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
SPI0SEL : SPI0 Clock Source Selection\nNote: If PLL is not supported, clock source of selection '01' will be changed to PCLK1.\nNote: If HXT is not supported, clock source of selection '00' will be stopped.\nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from PCLK1
#11 : 3
Clock source from internal high speed RC oscillator (HIRC)
End of enumeration elements list.
BPWM0SEL : BPWM0 Clock Source Selection\nThe peripheral clock source of BPWM0 is defined by BPWM0SEL. \nNote: If PLL is not supported, clock source of selection '0' will be changed to PCLK0.\nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from PLL
#1 : 1
Clock source from PCLK0
End of enumeration elements list.
BPWM1SEL : BPWM1 Clock Source Selection\nThe peripheral clock source of BPWM1 is defined by BPWM1SEL. \nNote: If PLL is not supported, clock source of selection '0' will be changed to PCLK1.\nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from PLL
#1 : 1
Clock source from PCLK1
End of enumeration elements list.
ADCSEL : ADC Clock Source Selection\nNote: If PLL is not supported, clock source of selection '01' will be changed to PCLK1.\nNote: If HXT is not supported, clock source of selection '00' will be stopped. \nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external high speed crystal oscillator (HXT) clock
#01 : 1
Clock source from PLL
#10 : 2
Clock source from PCLK1
#11 : 3
Clock source from internal high speed RC oscillator (HIRC) clock
End of enumeration elements list.
Clock Source Select Control Register 3
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART6SEL : UART6 Clock Source Selection\nNote: If PLL is not supported, clock source of selection '001' will be changed to PCLK0.\nNote: If LXT or HXT is not supported, clock source of selection '000' or '010' will be stopped. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from PLL
#010 : 2
Clock source from external low speed crystal oscillator (LXT)
#011 : 3
Clock source from internal high speed RC oscillator (HIRC)
#100 : 4
Clock source from PCLK0
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
End of enumeration elements list.
UART7SEL : UART7 Clock Source Selection\nNote: If PLL is not supported, clock source of selection '001' will be changed to PCLK1.\nNote: If LXT or HXT is not supported, clock source of selection '000' or '010' will be stopped. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from PLL
#010 : 2
Clock source from external low speed crystal oscillator (LXT)
#011 : 3
Clock source from internal high speed RC oscillator (HIRC)
#100 : 4
Clock source from PCLK1
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
End of enumeration elements list.
UART4SEL : UART4 Clock Source Selection\nNote: If PLL is not supported, clock source of selection '001' will be changed to PCLK0.\nNote: If LXT or HXT is not supported, clock source of selection '000' or '010' will be stopped. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from PLL
#010 : 2
Clock source from external low speed crystal oscillator (LXT)
#011 : 3
Clock source from internal high speed RC oscillator (HIRC)
#100 : 4
Clock source from PCLK0
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
End of enumeration elements list.
UART5SEL : UART5 Clock Source Selection\nNote: If PLL is not supported, clock source of selection '001' will be changed to PCLK1.\nNote: If LXT or HXT is not supported, clock source of selection '000' or '010' will be stopped. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from PLL
#010 : 2
Clock source from external low speed crystal oscillator (LXT)
#011 : 3
Clock source from internal high speed RC oscillator (HIRC)
#100 : 4
Clock source from PCLK1
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
End of enumeration elements list.
UART2SEL : UART2 Clock Source Selection
Note: If PLL is not supported, clock source of selection '001' will be changed to PCLK0.
Note: If LXT or HXT is not supported, clock source of selection '000' or '010' will be stopped. Please refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from PLL
#010 : 2
Clock source from external low speed crystal oscillator (LXT)
#011 : 3
Clock source from internal high speed RC oscillator (HIRC)
#100 : 4
Clock source from PCLK0
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
End of enumeration elements list.
UART3SEL : UART3 Clock Source Selection\nNote: If PLL is not supported, clock source of selection '001' will be changed to PCLK1.\nNote: If LXT or HXT is not supported, clock source of selection '000' or '010' will be stopped. \nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external high speed crystal oscillator (HXT)
#001 : 1
Clock source from PLL
#010 : 2
Clock source from external low speed crystal oscillator (LXT)
#011 : 3
Clock source from internal high speed RC oscillator (HIRC)
#100 : 4
Clock source from PCLK1
#101 : 5
Clock source from internal low speed RC oscillator (LIRC)
End of enumeration elements list.
Clock Divider Number Register 0
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source
bits : 0 - 3 (4 bit)
access : read-write
USBDIV : USB Clock Divide Number From PLL Clock
bits : 4 - 7 (4 bit)
access : read-write
UART0DIV : UART0 Clock Divide Number From UART0 Clock Source
bits : 8 - 11 (4 bit)
access : read-write
UART1DIV : UART1 Clock Divide Number From UART1 Clock Source
bits : 12 - 15 (4 bit)
access : read-write
ADCDIV : ADC Clock Divide Number From ADC Clock Source
bits : 16 - 23 (8 bit)
access : read-write
Clock Divider Number Register 4
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART2DIV : UART2 Clock Divide Number From UART2 Clock Source
bits : 0 - 3 (4 bit)
access : read-write
UART3DIV : UART3 Clock Divide Number From UART3 Clock Source
bits : 4 - 7 (4 bit)
access : read-write
UART4DIV : UART4 Clock Divide Number From UART4 Clock Source
bits : 8 - 11 (4 bit)
access : read-write
UART5DIV : UART5 Clock Divide Number From UART5 Clock Source
bits : 12 - 15 (4 bit)
access : read-write
UART6DIV : UART6 Clock Divide Number From UART6 Clock Source
bits : 16 - 19 (4 bit)
access : read-write
UART7DIV : UART7 Clock Divide Number From UART7 Clock Source
bits : 20 - 23 (4 bit)
access : read-write
APB Clock Divider Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APB0DIV : APB0 Clock DIvider\nAPB0 clock can be divided from HCLK\nOthers: Reserved.
bits : 0 - 2 (3 bit)
access : read-write
APB1DIV : APB1 Clock DIvider\nAPB1 clock can be divided from HCLK\nOthers: Reserved.
bits : 4 - 6 (3 bit)
access : read-write
AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMACKEN : PDMA Controller Clock Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA peripheral clock Disabled
#1 : 1
PDMA peripheral clock Enabled
End of enumeration elements list.
ISPCKEN : Flash ISP Controller Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash ISP peripheral clock Disabled
#1 : 1
Flash ISP peripheral clock Enabled
End of enumeration elements list.
EBICKEN : EBI Controller Clock Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI peripheral clock Disabled
#1 : 1
EBI peripheral clock Enabled
End of enumeration elements list.
HDIV_EN : Divider Controller Clock Enable Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Divider controller peripheral clock Disabled
#1 : 1
Divider controller peripheral clock Enabled
End of enumeration elements list.
CRCCKEN : CRC Generator Controller Clock Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
CRC peripheral clock Disabled
#1 : 1
CRC peripheral clock Enabled
End of enumeration elements list.
PLL Control Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBDIV : PLL Feedback Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 8 (9 bit)
access : read-write
INDIV : PLL Input Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 9 - 13 (5 bit)
access : read-write
OUTDIV : PLL Output Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 14 - 15 (2 bit)
access : read-write
PD : Power-down Mode (Write Protect)\nIf set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is in normal mode
#1 : 1
PLL is in Power-down mode (default)
End of enumeration elements list.
BP : PLL Bypass Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is in normal mode (default)
#1 : 1
PLL clock output is same as PLL input clock FIN
End of enumeration elements list.
OE : PLL OE (FOUT Enable) Pin Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL FOUT Enabled
#1 : 1
PLL FOUT is fixed low
End of enumeration elements list.
PLLSRC : PLL Source Clock Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL source clock from external high-speed crystal oscillator (HXT)
#1 : 1
PLL source clock from 48 MHz internal high-speed oscillator (HIRC/4)
End of enumeration elements list.
STBSEL : PLL Stable Counter Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz )
#1 : 1
PLL stable time is 16128 PLL source clock (suitable for source clock is larger than 12 MHz)
End of enumeration elements list.
Clock Status Monitor Register
address_offset : 0x50 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HXTSTB : HXT Clock Source Stable Flag (Read Only)\nNote: If HXT is not supported, this bit field will be invalid. \nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
External high speed crystal oscillator (HXT) clock is not stable or disabled
#1 : 1
External high speed crystal oscillator (HXT) clock is stable and enabled
End of enumeration elements list.
LXTSTB : LXT Clock Source Stable Flag (Read Only)\nNote: If LXT is not supported, this bit field will be invalid. \nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
External low speed crystal oscillator (LXT) clock is not stable or disabled
#1 : 1
External low speed crystal oscillator (LXT) clock is stabled and enabled
End of enumeration elements list.
PLLSTB : Internal PLL Clock Source Stable Flag (Read Only)\nNote: If PLL is not supported, this bit field will be invalid. \nPlease refer to section 3.2 NuMicro M031/M032 Series Selection Guide for detailed information.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal PLL clock is not stable or disabled
#1 : 1
Internal PLL clock is stable and enabled
End of enumeration elements list.
LIRCSTB : LIRC Clock Source Stable Flag (Read Only)
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal low speed RC oscillator (LIRC) clock is not stable or disabled
#1 : 1
Internal low speed RC oscillator (LIRC) clock is stable and enabled
End of enumeration elements list.
HIRCSTB : HIRC Clock Source Stable Flag (Read Only)
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal high speed RC oscillator (HIRC) clock is not stable or disabled
#1 : 1
Internal high speed RC oscillator (HIRC) clock is stable and enabled
End of enumeration elements list.
CLKSFAIL : Clock Switching Fail Flag (Read Only) \nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nNote: Write 1 to clear the bit to 0.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Clock switching success
#1 : 1
Clock switching failure
End of enumeration elements list.
Clock Output Control Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQSEL : Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write
CLKOEN : Clock Output Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Output function Disabled
#1 : 1
Clock Output function Enabled
End of enumeration elements list.
DIV1EN : Clock Output Divide One Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Output will output clock with source frequency divided by FREQSEL
#1 : 1
Clock Output will output clock with source frequency
End of enumeration elements list.
CLK1HZEN : Clock Output 1Hz Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
1 Hz clock output for 32.768 kHz frequency compensation Disabled
#1 : 1
1 Hz clock output for 32.768 kHz frequency compensation Enabled
End of enumeration elements list.
Clock Fail Detector Control Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTFDEN : HXT Clock Fail Detector Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
External high speed crystal oscillator (HXT) clock fail detector Disabled
#1 : 1
External high speed crystal oscillator (HXT) clock fail detector Enabled
End of enumeration elements list.
HXTFIEN : HXT Clock Fail Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
External high speed crystal oscillator (HXT) clock fail interrupt Disabled
#1 : 1
External high speed crystal oscillator (HXT) clock fail interrupt Enabled
End of enumeration elements list.
LXTFDEN : LXT Clock Fail Detector Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
External low speed crystal oscillator (LXT) clock fail detector Disabled
#1 : 1
External low speed crystal oscillator (LXT) clock fail detector Enabled
End of enumeration elements list.
LXTFIEN : LXT Clock Fail Interrupt Enable Bit
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
External low speed crystal oscillator (LXT) clock fail interrupt Disabled
#1 : 1
External low speed crystal oscillator (LXT) clock fail interrupt Enabled
End of enumeration elements list.
HXTFQDEN : HXT Clock Frequency Range Detector Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
External high speed crystal oscillator (HXT) clock frequency range detector Disabled
#1 : 1
External high speed crystal oscillator (HXT) clock frequency range detector Enabled
End of enumeration elements list.
HXTFQIEN : HXT Clock Frequency Range Detector Interrupt Enable Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
External high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled
#1 : 1
External high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled
End of enumeration elements list.
Clock Fail Detector Status Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTFIF : HXT Clock Fail Interrupt Flag (Write Protect)\nNote: Write 1 to clear the bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
External high speed crystal oscillator (HXT) clock is normal
#1 : 1
External high speed crystal oscillator (HXT) clock stops
End of enumeration elements list.
LXTFIF : LXT Clock Fail Interrupt Flag (Write Protect)\nNote: Write 1 to clear the bit to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
External low speed crystal oscillator (LXT) clock is normal
#1 : 1
External low speed crystal oscillator (LXT) stops
End of enumeration elements list.
HXTFQIF : HXT Clock Frequency Range Detector Interrupt Flag (Write Protect)\nNote: Write 1 to clear the bit to 0.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
External high speed crystal oscillator (HXT) clock frequency is normal
#1 : 1
External high speed crystal oscillator (HXT) clock frequency is abnormal
End of enumeration elements list.
Clock Frequency Range Detector Upper Boundary Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPERBD : HXT Clock Frequency Range Detector Upper Boundary Value\nThe bits define the maximum value of frequency range detector window.\nWhen HXT frequency is higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will be set to 1.
bits : 0 - 9 (10 bit)
access : read-write
Clock Frequency Range Detector Lower Boundary Register
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOWERBD : HXT Clock Frequency Range Detector Lower Boundary Value\nThe bits define the minimum value of frequency range detector window.\nWhen HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.
bits : 0 - 9 (10 bit)
access : read-write
APB Devices Clock Enable Control Register 0
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTCKEN : Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote: This bit is reset by power on reset, Watchdog reset or software chip reset.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog timer clock Disabled
#1 : 1
Watchdog timer clock Enabled
End of enumeration elements list.
RTCCKEN : RTC Clock Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC clock Disabled
#1 : 1
RTC clock Enabled
End of enumeration elements list.
TMR0CKEN : Timer0 Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 clock Disabled
#1 : 1
Timer0 clock Enabled
End of enumeration elements list.
TMR1CKEN : Timer1 Clock Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 clock Disabled
#1 : 1
Timer1 clock Enabled
End of enumeration elements list.
TMR2CKEN : Timer2 Clock Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 clock Disabled
#1 : 1
Timer2 clock Enabled
End of enumeration elements list.
TMR3CKEN : Timer3 Clock Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer3 clock Disabled
#1 : 1
Timer3 clock Enabled
End of enumeration elements list.
CLKOCKEN : CLKO Clock Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
CLKO clock Disabled
#1 : 1
CLKO clock Enabled
End of enumeration elements list.
ACMP01CKEN : Analog Comparator 0/1 Clock Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog comparator 0/1 clock Disabled
#1 : 1
Analog comparator 0/1 clock Enabled
End of enumeration elements list.
I2C0CKEN : I2C0 Clock Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C0 clock Disabled
#1 : 1
I2C0 clock Enabled
End of enumeration elements list.
I2C1CKEN : I2C1 Clock Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C1 clock Disabled
#1 : 1
I2C1 clock Enabled
End of enumeration elements list.
QSPI0CKEN : QSPI0 Clock Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
QSPI0 clock Disabled
#1 : 1
QSPI0 clock Enabled
End of enumeration elements list.
SPI0CKEN : SPI0 Clock Enable Bit
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI0 clock Disabled
#1 : 1
SPI0 clock Enabled
End of enumeration elements list.
UART0CKEN : UART0 Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 clock Disabled
#1 : 1
UART0 clock Enabled
End of enumeration elements list.
UART1CKEN : UART1 Clock Enable Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 clock Disabled
#1 : 1
UART1 clock Enabled
End of enumeration elements list.
UART2CKEN : UART2 Clock Enable Bit
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART2 clock Disabled
#1 : 1
UART2 clock Enabled
End of enumeration elements list.
UART3CKEN : UART3 Clock Enable Bit
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART3 clock Disabled
#1 : 1
UART3 clock Enabled
End of enumeration elements list.
UART4CKEN : UART4 Clock Enable Bit
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART4 clock Disabled
#1 : 1
UART4 clock Enabled
End of enumeration elements list.
UART5CKEN : UART5 Clock Enable Bit
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART5 clock Disabled
#1 : 1
UART5 clock Enabled
End of enumeration elements list.
UART6CKEN : UART6 Clock Enable Bit
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART6 clock Disabled
#1 : 1
UART6 clock Enabled
End of enumeration elements list.
UART7CKEN : UART7 Clock Enable Bit
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART7 clock Disabled
#1 : 1
UART7 clock Enabled
End of enumeration elements list.
USBDCKEN : USB Device Clock Enable Bit
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB Device clock Disabled
#1 : 1
USB Device clock Enabled
End of enumeration elements list.
ADCCKEN : Analog-digital-converter (ADC) Clock Enable Bit
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC clock Disabled
#1 : 1
ADC clock Enabled
End of enumeration elements list.
LDO Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXT Filter Select Control Register
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTFSEL : HXT Filter Select \nNote: This bit should not be changed during HXT running.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
HXT frequency is greater than12 MHz
#1 : 1
HXT frequency is less than or equal to 12 MHz
End of enumeration elements list.
APB Devices Clock Enable Control Register 1
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USCI0CKEN : USCI0 Clock Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
USCI0 clock Disabled
#1 : 1
USCI0 clock Enabled
End of enumeration elements list.
USCI1CKEN : USCI1 Clock Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
USCI1 clock Disabled
#1 : 1
USCI1 clock Enabled
End of enumeration elements list.
PWM0CKEN : PWM0 Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0 clock Disabled
#1 : 1
PWM0 clock Enabled
End of enumeration elements list.
PWM1CKEN : PWM1 Clock Enable Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1 clock Disabled
#1 : 1
PWM1 clock Enabled
End of enumeration elements list.
BPWM0CKEN : BPWM0 Clock Enable Bit
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM0 clock Disabled
#1 : 1
BPWM0 clock Enabled
End of enumeration elements list.
BPWM1CKEN : BPWM1 Clock Enable Bit
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM1 clock Disabled
#1 : 1
BPWM1 clock Enabled
End of enumeration elements list.
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