FMC_ISPCTL (ISPCTL)

FMC_ISPTRG (ISPTRG)

FMC_DFBA (DFBA)

FMC_FTCTL (FTCTL)

FMC_ISPADDR (ISPADDR)

FMC_ISPSTS (ISPSTS)

FMC_ISPDAT (ISPDAT)

FMC_MPDAT0 (MPDAT0)

FMC_MPDAT1 (MPDAT1)

FMC_MPDAT2 (MPDAT2)

FMC_MPDAT3 (MPDAT3)

FMC_ISPCMD (ISPCMD)

FMC_MPSTS (MPSTS)

FMC_MPADDR (MPADDR)

ISPEN : ISP Enable Bit (Write Protect)\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BS : Boot Selection (Write Protect) Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPUEN : SPROM Update Enable Bit (Write Protect)\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

APUEN : APROM Update Enable Bit (Write Protect)\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGUEN : CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LDUEN : LDROM Update Enable Bit (Write Protect)\nLDROM update enable bit.\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\nAPROM writes to itself if APUEN is set to 0.\nLDROM writes to itself if LDUEN is set to 0.\nCONFIG is erased/programmed if CFGUEN is set to 0.\nSPROM is erased/programmed if SPUEN is set to 0\nSPROM is programmed at SPROM secured mode.\nPage Erase command at LOCK mode with ICE connection\nErase or Program command at brown-out detected\nDestination address is illegal, such as over an available range.\nInvalid ISP commands\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

INTEN : ISP Interrupt Enabled Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.Before use INT,user needs to clear the INTFLAG(FMC_ISPSTS[8]) make sure INT happen at correct time.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPGO : ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFBA : Data Flash Base Address\nThis register indicates Data Flash start address. It is a read only register.\nThe Data Flash is shared with APROM. the content of this register is loaded from CONFIG1
bits : 0 - 31 (32 bit)
access : read-only

FOM : Frequency Optimization Mode (Write Protect)\nThe M031/M032 series support adjustable Flash access timing to optimize the Flash access cycles in different system working frequency.\nFor 16/32/64/128 Kbytes Flash:\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BBOFF : Flash Branch Buffer Disable Control (Write Protect)\nNote 1: This bit is write-protected. Refer to the SYS_REGLCTL register.\nNote 2: Only suppoted in 16/32/64/128 Kbytes Flash.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CACHEINV : Flash Cache Invalidation (Write Protect)\nNote 1: Write 1 to start cache invalidation. The value will be changed to 0 once the process is finished.\nNote 2: This bit is write-protected. Refer to the SYS_REGLCTL register.\nNote 3: Only supported in 256/512 Kbytes Flash.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPADDR : ISP Address\nThe M031/M032 series is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. For CRC32 Checksum Calculation command, this field is the Flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation.\n16/32/64/128 Kbytes Flash:\nISPADR[8:0] must be kept all 0 for Vector Page Re-map Command.\n256/512 Kbytes Flash:\nISPADR[11:0] must be kept all 0 for Vector Page Re-map Command.
bits : 0 - 31 (32 bit)
access : read-write

ISPBUSY : ISP BUSY (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CBS : Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PGFF : Flash Program with Fast Verification Flag (Read Only)\nThis bit is set if data is mismatched at ISP programming verification. This bit is clear by performing ISP Flash erase or ISP read CID operation
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\nAPROM writes to itself if APUEN is set to 0.\nLDROM writes to itself if LDUEN is set to 0.\nCONFIG is erased/programmed if CFGUEN is set to 0.\nSPROM is erased/programmed if SPUEN is set to 0\nSPROM is programmed at SPROM secured mode.\nPage Erase command at LOCK mode with ICE connection\nErase or Program command at brown-out detected\nDestination address is illegal, such as over an available range.\nInvalid ISP commands
bits : 6 - 6 (1 bit)
access : read-write

ALLONE : Flash All-one Verification Flag This bit is set by hardware if all of Flash bits are 1, and cleared if Flash bits are not all 1 after 'Run Flash All-One Verification' complete this bit can also be cleared by writing 1.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTFLAG : ISP Command Finish Interrupt Flag\nNote: Only supported in 256/512 Kbytes Flash.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECMAP : Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF}, except SPROM.\nVECMAP [18:12] should be 0.
bits : 9 - 29 (21 bit)
access : read-only

FBS : Flash Bank Select Indicator\nThis bit indicates which APROM address model is selected to boot.\nNote: Only supported in 256/512 Kbytes Flash.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCODE : Security Code Active Flag This bit is set to 1 by hardware when detecting SPROM secured code is active at Flash initialization, or software writes 1 to this bit to make secured code active this bit is only cleared by SPROM page erase operation.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPDAT : ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT0 : ISP Data 0\nThis register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT1 : ISP Data 1\nThis register is the second 32-bit data for 64-bit/multi-word programming.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT2 : ISP Data 2\nThis register is the third 32-bit data for multi-word programming.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT3 : ISP Data 3\nThis register is the fourth 32-bit data for multi-word programming.
bits : 0 - 31 (32 bit)
access : read-write

CMD : ISP CMD\nISP command table is shown below:\nThe other commands are invalid.
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MPBUSY : ISP Multi-word Program Busy Flag (Read Only)\nWrite 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0]).
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PPGO : ISP Multi-program Status (Read Only)
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Read Only)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\nAPROM writes to itself if APUEN is set to 0.\nLDROM writes to itself if LDUEN is set to 0.\nCONFIG is erased/programmed if CFGUEN is set to 0.\nPage Erase command at LOCK mode with ICE connection\nErase or Program command at brown-out detected\nDestination address is illegal, such as over an available range.\nInvalid ISP commands
bits : 2 - 2 (1 bit)
access : read-only

D0 : ISP DATA 0 Flag (Read Only)\nThis bit is set when FMC_MPDAT0 is written and auto cleared to 0 when the FMC_MPDAT0 data is programmed to Flash complete.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

D1 : ISP DATA 1 Flag (Read Only)\nThis bit is set when FMC_MPDAT1 is written and auto cleared to 0 when the FMC_MPDAT1 data is programmed to Flash complete.
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

D2 : ISP DATA 2 Flag (Read Only)\nThis bit is set when FMC_MPDAT2 is written and auto cleared to 0 when the FMC_MPDAT2 data is programmed to Flash complete.
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

D3 : ISP DATA 3 Flag (Read Only)\nThis bit is set when FMC_MPDAT3 is written and auto cleared to 0 when the FMC_MPDAT3 data is programmed to Flash complete.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MPADDR : ISP Multi-word Program Address\nMPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.\nMPADDR will keep the final ISP address when ISP multi-word program is complete.
bits : 0 - 31 (32 bit)
access : read-only