\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
Watchdog Timer Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WTR : Reset Watchdog Timer Up Counter (Write Protect)\nNote: This bit will be automatically cleared by hardware.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the internal 18-bit WDT up counter value
End of enumeration elements list.
WTRE : Watchdog Timer Reset Enable Control (Write Protect)\nSetting this bit will enable the WDT time-out reset function if the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDT time-out reset function Disabled
#1 : 1
WDT time-out reset function Enabled
End of enumeration elements list.
WTRF : Watchdog Timer Time-Out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDT time-out reset did not occur
#1 : 1
WDT time-out reset occurred
End of enumeration elements list.
WTIF : Watchdog Timer Time-Out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval.\nNote: This bit is cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDT time-out interrupt did not occur
#1 : 1
WDT time-out interrupt occurred
End of enumeration elements list.
WTWKE : Watchdog Timer Time-Out Wake-Up Function Control (Write Protect)\nIf this bit is set to 1, while WTIF is generated to 1 and WTIE enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake-up trigger event Disabled if WDT time-out interrupt signal generated
#1 : 1
Wake-up trigger event Enabled if WDT time-out interrupt signal generated
End of enumeration elements list.
WTWKF : Watchdog Timer Time-Out Wake-Up Flag\nThis bit indicates the interrupt wake-up flag status of WDT.\nNote: This bit is cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDT does not cause chip wake-up
#1 : 1
Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated
End of enumeration elements list.
WTIE : Watchdog Timer Time-Out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDT time-out interrupt Disabled
#1 : 1
WDT time-out interrupt Enabled
End of enumeration elements list.
WTE : Watchdog Timer Enable Control (Write Protect)\nNote: If CWDTEN (CONFIG0[31] Watchdog Enable) bit is set to 0, this bit is forced as 1 and user cannot change this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDT Disabled. (This action will reset the internal up counter value.)
#1 : 1
WDT Enabled
End of enumeration elements list.
WTIS : Watchdog Timer Time-Out Interval Selection (Write Protect)\nThese three bits select the time-out interval period for the WDT.\n
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
24 *TWDT
#001 : 1
26 * TWDT
#010 : 2
28 * TWDT
#011 : 3
210 * TWDT
#100 : 4
212 * TWDT
#101 : 5
214 * TWDT
#110 : 6
216 * TWDT
#111 : 7
218 * TWDT
End of enumeration elements list.
DBGACK_WDT : ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode acknowledgement effects WDT counting
#1 : 1
ICE debug mode acknowledgement Disabled
End of enumeration elements list.
Watchdog Timer Alternative Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WTRDSEL : Watchdog Timer Reset Delay Selection (Write Protect)\nWhen WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter to prevent WDT time-out reset happened. User can select a suitable value of WDT Reset Delay Period for different WDT time-out period.\nThese bits are protected bit. It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.\nNote: This register will be reset to 0 if WDT time-out reset happened.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Watchdog Timer Reset Delay Period is 1026 * WDT_CLK
#01 : 1
Watchdog Timer Reset Delay Period is 130 * WDT_CLK
#10 : 2
Watchdog Timer Reset Delay Period is 18 * WDT_CLK
#11 : 3
Watchdog Timer Reset Delay Period is 3 * WDT_CLK
End of enumeration elements list.
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