\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
Part Device Identification Number Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDID : Part Device Identification Number\nThis register reflects device part number code. Software can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only
Register Write-protection Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGPROTDIS : Register Write-protection Disable Index (Read Only)\nNote: This bit is write protected bit. Refer to the REGWRPROT register.\nPlease refer to Table 6-3 The protected register table.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Write-protection Enabled for writing protected registers. Any write to the protected register is ignored
#1 : 1
Write-protection Disabled for writing protected registers
End of enumeration elements list.
REGWRPROT : Register Write-protection Code (Write Only)
Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write.
bits : 1 - 7 (7 bit)
access : write-only
Brown-out Detector Control Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOD_EN : Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBODEN (Config0[23]) bit.\nNote: This bit is write protected. Refer to the REGWRPROT register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector function Disabled
#1 : 1
Brown-out Detector function Enabled
End of enumeration elements list.
BOD_VL : Brown-out Detector Threshold Voltage Select (Write Protect)\nThe default value is set by flash controller user configuration register CBOV (Config0[22:21]) bits.\nNote: This bit is write protected. Refer to the REGWRPROT register.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#00 : 0
Brown-out voltage is 2.2V
#01 : 1
Brown-out voltage is 2.7V
#10 : 2
Brown-out voltage is 3.7V
#11 : 3
Brown-out voltage is 4.4V
End of enumeration elements list.
BOD_RSTEN : Brown-out Reset Enable Bit (Write Protect)\nNote1: While the Brown-out Detector function is enabled (BOD_EN high) and BOD reset function is enabled (BOD_RSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BOD_OUT high).\nNote2: The default value is set by flash controller user configuration register CBRST (Config0[20]).\nNote3: This bit is write protected. Refer to the REGWRPROT register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out INTERRUPT function Enabled
#1 : 1
Brown-out RESET function Enabled
End of enumeration elements list.
BOD_INTF : Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting
#1 : 1
When Brown-out Detector detects the VDD is dropped down through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled
End of enumeration elements list.
BOD_LPM : Brown-out Detector Low Power Mode (Write Protect)\nNote1: The BOD consumes about 100 uA in Normal mode, and the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote2: This bit is write protected. Refer to the REGWRPROT register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
BOD operated in Normal mode (default)
#1 : 1
BOD Low Power mode Enabled
End of enumeration elements list.
BOD_OUT : Brown-out Detector Output Status\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector output status is 0. It means the detected voltage is higher than BOD_VL setting or BOD_EN is 0
#1 : 1
Brown-out Detector output status is 1. It means the detected voltage is lower than BOD_VL setting. If the BOD_EN is 0, BOD function disabled, this bit always responds to 0
End of enumeration elements list.
LVR_EN : Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote: This bit is write protected. Refer to the REGWRPROT register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low Voltage Reset function Disabled
#1 : 1
Low Voltage Reset function Enabled - After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default)
End of enumeration elements list.
Temperature Sensor Control Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTEMP_EN : Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1, the value of temperature sensor output can be obtained from the ADC conversion result. Please refer to the EADC chapter for detailed ADC conversion functional description.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Temperature sensor function Disabled (default)
#1 : 1
Temperature sensor function Enabled
End of enumeration elements list.
Power-on Reset Controller Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POR_DIS_CODE : Power-on Reset Enable Bits (Write Protect)\nWhen powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.\nThe POR function will be active again when this field is set to another value or chip is reset by other reset source, including:\nnRESET, Watchdog Timer reset, Window Watchdog Timer reset, LVR reset, BOD reset, ICE reset command and the software-chip reset function.\nNote: This bit is write protected. Refer to the REGWRPROT register.
bits : 0 - 15 (16 bit)
access : read-write
P0 Multiple Function and Input Type Control Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0_MFP0 : P0.0 Multi-function Selection\nBits P0_ALT[0] and P0_MFP[0] determine the P0.0 function.\n(P0_ALT[0], P0_MFP[0]) value and function mapping is as following list.\n
bits : 0 - 0 (1 bit)
access : read-write
P0_MFP1 : P0.1 Multi-function Selection\nBits P0_ALT[1] and P0_MFP[1] determine the P0.1 function.\n(P0_ALT[2], P0_MFP[2]) value and function mapping is as following list.\n
bits : 1 - 1 (1 bit)
access : read-write
P0_MFP2 : P0.2 Multi-function Selection\nBits P0_ALT[2] and P0_MFP[2] determine the P0.2 function.\n(P0_ALT[2], P0_MFP[2]) value and function mapping is as following list.\n
bits : 2 - 2 (1 bit)
access : read-write
P0_MFP3 : P0.3 Multi-function Selection\nBits P0_ALT[3] and P0_MFP[3] determine the P0.3 function.\n(P0_ALT[3], P0_MFP[3]) value and function mapping is as following list.\n
bits : 3 - 3 (1 bit)
access : read-write
P0_MFP4 : P0.4 Multi-function Selection\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P0.4 is selected
#1 : 1
The EPWM0_CH4 function is selected
End of enumeration elements list.
P0_MFP5 : P0.5 Multi-function Selection\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P0.5 is selected
#1 : 1
The EPWM0_CH5 function is selected
End of enumeration elements list.
P0_MFP6 : P0.6 Multi-function Selection\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P0.6 is selected
#1 : 1
The EPWM0_BRAKE1 function is selected
End of enumeration elements list.
P0_MFP7 : P0.7 Multi-function Selection\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P0.7 is selected
#1 : 1
The STADC function is selected
End of enumeration elements list.
P0_ALT0 : P0.0 Alternative Function\nSee P0_MFP[0].
bits : 8 - 8 (1 bit)
access : read-write
P0_ALT1 : P0.1 Alternative Function\nSee P0_MFP[1].
bits : 9 - 9 (1 bit)
access : read-write
P0_ALT2 : P0.2 Alternative Function\nSee P0_MFP[2].
bits : 10 - 10 (1 bit)
access : read-write
P0_ALT3 : P0.3 Alternative Function\nSee P0_MFP[3].
bits : 11 - 11 (1 bit)
access : read-write
P0_TYPE0 : Port 0 Schmitt Trigger Input Enable Bits\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port 0 bit m Schmitt trigger input function Disabled
#1 : 1
Port 0 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P0_TYPE1 : Port 0 Schmitt Trigger Input Enable Bits\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port 0 bit m Schmitt trigger input function Disabled
#1 : 1
Port 0 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P0_TYPE2 : Port 0 Schmitt Trigger Input Enable Bits\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port 0 bit m Schmitt trigger input function Disabled
#1 : 1
Port 0 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P0_TYPE3 : Port 0 Schmitt Trigger Input Enable Bits\n
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port 0 bit m Schmitt trigger input function Disabled
#1 : 1
Port 0 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P0_TYPE4 : Port 0 Schmitt Trigger Input Enable Bits\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port 0 bit m Schmitt trigger input function Disabled
#1 : 1
Port 0 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P0_TYPE5 : Port 0 Schmitt Trigger Input Enable Bits\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port 0 bit m Schmitt trigger input function Disabled
#1 : 1
Port 0 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P0_TYPE6 : Port 0 Schmitt Trigger Input Enable Bits\n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port 0 bit m Schmitt trigger input function Disabled
#1 : 1
Port 0 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P0_TYPE7 : Port 0 Schmitt Trigger Input Enable Bits\n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port 0 bit m Schmitt trigger input function Disabled
#1 : 1
Port 0 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P1 Multiple Function and Input Type Control Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1_MFP0 : P1.0 Multi-function Selection\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P1.0 is selected
#1 : 1
The EPWM1_CH0 function is selected
End of enumeration elements list.
P1_MFP1 : P1.1 Multi-function Selection\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P1.1 is selected
#1 : 1
The EPWM1_CH1 function is selected
End of enumeration elements list.
P1_MFP2 : P1.2 Multi-function Selection\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P1.2 is selected
#1 : 1
The EPWM1_CH2 function is selected
End of enumeration elements list.
P1_MFP3 : P1.3 Multi-function Selection\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P1.3 is selected
#1 : 1
The EPWM1_CH3 function is selected
End of enumeration elements list.
P1_MFP4 : P1.4 Multi-function Selection\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P1.4 is selected
#1 : 1
The EPWM1_CH4 function is selected
End of enumeration elements list.
P1_MFP5 : P1.5 Multi-function Selection\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P1.5 is selected
#1 : 1
The EPWM1_CH5 function is selected
End of enumeration elements list.
P1_MFP6 : P1.6 Multi-function Selection\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P1.6 is selected
#1 : 1
The EPWM0_BRAKE0 function is selected
End of enumeration elements list.
P1_MFP7 : P1.7 Multi-function Selection\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P1.7 is selected
#1 : 1
The EPWM1_BRAKE0 function is selected
End of enumeration elements list.
P1_TYPE0 : Port 1 Schmitt Trigger Input Enable Bits\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port 1 bit m Schmitt trigger input function Disabled
#1 : 1
Port 1 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P1_TYPE1 : Port 1 Schmitt Trigger Input Enable Bits\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port 1 bit m Schmitt trigger input function Disabled
#1 : 1
Port 1 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P1_TYPE2 : Port 1 Schmitt Trigger Input Enable Bits\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port 1 bit m Schmitt trigger input function Disabled
#1 : 1
Port 1 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P1_TYPE3 : Port 1 Schmitt Trigger Input Enable Bits\n
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port 1 bit m Schmitt trigger input function Disabled
#1 : 1
Port 1 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P1_TYPE4 : Port 1 Schmitt Trigger Input Enable Bits\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port 1 bit m Schmitt trigger input function Disabled
#1 : 1
Port 1 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P1_TYPE5 : Port 1 Schmitt Trigger Input Enable Bits\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port 1 bit m Schmitt trigger input function Disabled
#1 : 1
Port 1 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P1_TYPE6 : Port 1 Schmitt Trigger Input Enable Bits\n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port 1 bit m Schmitt trigger input function Disabled
#1 : 1
Port 1 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P1_TYPE7 : Port 1 Schmitt Trigger Input Enable Bits\n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Port 1 bit m Schmitt trigger input function Disabled
#1 : 1
Port 1 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P2 Multiple Function and Input Type Control Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2_MFP0 : P2.0 Multi-function Selection\nBits P2_ALT[0] and P2_MFP[0] determine the P2.0 function.\n(P2_ALT[0], P2_MFP[0]) value and function mapping is as following list.\n
bits : 0 - 0 (1 bit)
access : read-write
P2_MFP1 : P2.1 Multi-function Selection\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P2.1 is selected
#1 : 1
The ECAP0_IC2 function is selected
End of enumeration elements list.
P2_MFP2 : P2.2 Multi-function Selection\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P2.2 is selected
#1 : 1
The ECAP0_IC1 function is selected
End of enumeration elements list.
P2_MFP3 : P2.3 Multi-function Selection\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P2.3 is selected
#1 : 1
The ECAP0_IC0 function is selected
End of enumeration elements list.
P2_MFP4 : P2.4 Multi-function Selection\nBits P2_ALT[4] and P2_MFP[4] determine the P2.4 function.\n(P2_ALT[4], P2_MFP[4]) value and function mapping is as following list.\n
bits : 4 - 4 (1 bit)
access : read-write
P2_MFP5 : P2.5 Multi-function Selection\nBits P2_ALT[5] and P2_MFP[5] determine the P2.5 function.\n(P2_ALT[5], P2_MFP[5]) value and function mapping is as following list.\n
bits : 5 - 5 (1 bit)
access : read-write
P2_MFP6 : P2.6 Multi-function Selection\nBits P2_ALT[6] and P2_MFP[6] determine the P2.6 function.\n(P2_ALT[6], P2_MFP[6]) value and function mapping is as following list.\n
bits : 6 - 6 (1 bit)
access : read-write
P2_MFP7 : P2.7 Multi-function Selection\nBits P2_ALT[7] and P2_MFP[7] determine the P2.7 function.\n(P2_ALT[7], P2_MFP[7]) value and function mapping is as following list.\n
bits : 7 - 7 (1 bit)
access : read-write
P2_ALT0 : P2.0 Alternative Function\nSee P2_MFP[0].
bits : 8 - 8 (1 bit)
access : read-write
P2_ALT4 : P2.4 Alternative Function\nSee P2_MFP[4].
bits : 12 - 12 (1 bit)
access : read-write
P2_ALT5 : P2.5 Alternative Function\nSee P2_MFP[5].
bits : 13 - 13 (1 bit)
access : read-write
P2_ALT6 : P2.6 Alternative Function\nSee P2_MFP[6].
bits : 14 - 14 (1 bit)
access : read-write
P2_ALT7 : P2.7 Alternative Function\nSee P2_MFP[7].
bits : 15 - 15 (1 bit)
access : read-write
P2_TYPE : Port 2 Schmitt Trigger Input Enable Bits\n
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0 : 0
Port 2 bit m Schmitt trigger input function Disabled
1 : 1
Port 2 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P3 Multiple Function and Input Type Control Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3_MFP0 : P3.0 Multi-function Selection\nBits P3_ALT[0] and P3_MFP[0] determine the P3.0 function.\n(P3_ALT[0], P3_MFP[0]) value and function mapping is as following list.\n
bits : 0 - 0 (1 bit)
access : read-write
P3_MFP1 : P3.1 Multi-function Selection\nBits P3_ALT[1] and P3_MFP[1] determine the P3.1 function.\n(P3_ALT[1], P3_MFP[1]) value and function mapping is as following list.\n
bits : 1 - 1 (1 bit)
access : read-write
P3_MFP2 : P3.2 Multi-function Selection\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P3.2 is selected
#1 : 1
The INT0 function is selected
End of enumeration elements list.
P3_MFP3 : P3.3 Multi-function Selection\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P3.3 is selected
#1 : 1
The INT1 function is selected
End of enumeration elements list.
P3_MFP4 : P3.4 Multi-function Selection\nBits P3_ALT[4] and P3_MFP[4] determine the P3.4 function.\n(P3_ALT[4], P3_MFP[4]) value and function mapping is as following list.\n
bits : 4 - 4 (1 bit)
access : read-write
P3_MFP5 : P3.5 Multi-function Selection\nBits P3_ALT[5] and P3_MFP[5] determine the P3.5 function.\n(P3_ALT[5], P3_MFP[5]) value and function mapping is as following list.\n
bits : 5 - 5 (1 bit)
access : read-write
P3_MFP6 : P3.6 Multi-function Selection\nShould be 0 for GPIO P3.6.
bits : 6 - 6 (1 bit)
access : read-write
P3_MFP7 : P3.7 Multi-function Selection\nShould be 0 for GPIO P3.7.
bits : 7 - 7 (1 bit)
access : read-write
P3_ALT0 : P3.0 Alternative Function\nSee P3_MFP[0].
bits : 8 - 8 (1 bit)
access : read-write
P3_ALT1 : P3.1 Alternative Function\nSee P3_MFP[1].
bits : 9 - 9 (1 bit)
access : read-write
P3_ALT4 : P3.4 Alternative Function\nSee P3_MFP[4].
bits : 12 - 12 (1 bit)
access : read-write
P3_ALT5 : P3.5 Alternative Function\nSee P3_MFP[5].
bits : 13 - 13 (1 bit)
access : read-write
P3_TYPE : Port 3 Schmitt Trigger Input Enable Bit\n
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0 : 0
Port 3 bit m Schmitt trigger input function Disabled
1 : 1
Port 3 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
System Reset Source Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTS_POR : Power-on Reset Flag
The RSTS_POR flag is set by the Reset Signal from the Power-on Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from POR or CHIP_RST (IPRSTC1[0])
#1 : 1
Power-on Reset (POR) or CHIP_RST (IPRSTC1[0]) had issued the reset signal to reset the system
End of enumeration elements list.
RSTS_RESET : Reset Pin Reset Flag
The RSTS_RESET flag is set by the Reset Signal from the nRESET pin to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from the nRESET pin
#1 : 1
The nRESET pin had issued the reset signal to reset the system
End of enumeration elements list.
RSTS_WDT : Watchdog Timer Reset Flag
The RSTS_WDT flag is set by the Reset Signal from the watchdog timer or window watchdog timer to indicate the previous reset source.
Note1: Write 1 to clear this bit to 0.
Note2: Watchdog Timer register WTRF(WTCR[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDTSR) bit is set if the system has been reset by WWDT time-out reset.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from watchdog timer or window watchdog timer
#1 : 1
The watchdog timer or window watchdog timer had issued the reset signal to reset the system
End of enumeration elements list.
RSTS_LVR : Low Voltage Reset Flag
The RSTS_LVR flag is set by the Reset Signal from the Low-Voltage-Reset controller to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from LVR
#1 : 1
The LVR controller had issued the reset signal to reset the system
End of enumeration elements list.
RSTS_BOD : Brown-out Detector Reset Flag
The RSTS_BOD flag is set by the Reset Signal from the Brown-out Detector to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from BOD
#1 : 1
The BOD had issued the reset signal to reset the system
End of enumeration elements list.
RSTS_SYS : SYS Reset Flag
The RSTS_SYS flag is set by the Reset Signal from the Cortex-M0 kernel to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from Cortex-M0
#1 : 1
The Cortex-M0 had issued the reset signal to reset the system by writing 1 to bit SYSRESETREQ (AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 core
End of enumeration elements list.
RSTS_CPU : CPU Reset Flag\nThe RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 core and Flash memory controller (FMC).\nNote: Write 1 to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from CPU
#1 : 1
Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST(IPRSTC1[1]) to 1
End of enumeration elements list.
P4 Multiple Function and Input Type Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4_MFP0 : P4.0 Multi-function Selection\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P4.0 is selected
#1 : 1
The ECAP1_IC0 function is selected
End of enumeration elements list.
P4_MFP1 : P4.1 Multi-function Selection\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P4.1 is selected
#1 : 1
The ECAP1_IC1 function is selected
End of enumeration elements list.
P4_MFP2 : P4.2 Multi-function Selection\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P4.2 is selected
#1 : 1
The ECAP1_IC2 function is selected
End of enumeration elements list.
P4_MFP4 : P4.4 Multi-function Selection\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P4.4 is selected
#1 : 1
Reserved
End of enumeration elements list.
P4_MFP5 : P4.5 Multi-function Selection\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P4.5 is selected
#1 : 1
Reserved
End of enumeration elements list.
P4_MFP6 : P4.6 Multi-function Selection\nBits P4_ALT[6] and P4_MFP[6] determine the P4.6 function.\n(P4_ALT[6], P4_MFP[6]) value and function mapping is as following list.\n
bits : 6 - 6 (1 bit)
access : read-write
P4_MFP7 : P4.7 Multi-function Selection\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P4.7 is selected
#1 : 1
The TM3 function is selected
End of enumeration elements list.
P4_ALT : P4.6 Alternative Function\nSee P4_MFP[6].
bits : 14 - 14 (1 bit)
access : read-write
P4_TYPE : Port 4 Schmitt Trigger Input Enable Bit\n
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0 : 0
Port 4 bit m Schmitt trigger input function Disabled
1 : 1
Port 4 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P5 Multiple Function and Input Type Control Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5_MFP0 : P5.0 Multi-function Selection\nThis bit combined with P5_ALT[0] selects P5.0 multi-function.\nBits P5_ALT[0] and P5_MFP[0] determine the P5.0 function.\n(P5_ALT[0], P5_MFP[0]) value and function mapping is as following list.\n
bits : 0 - 0 (1 bit)
access : read-write
P5_MFP1 : P5.1 Multi-function Selection\nBits P5_ALT[1] and P5_MFP[1] determine the P5.1 function.\n(P5_ALT[1], P5_MFP[1]) value and function mapping is as following list.\n
bits : 1 - 1 (1 bit)
access : read-write
P5_MFP2 : P5.2 Multi-function Selection\nBits P5_ALT[2] and P5_MFP[2] determine the P5.2 function.\n(P5_ALT[2], P5_MFP[2]) value and function mapping is as following list.\n
bits : 2 - 2 (1 bit)
access : read-write
P5_MFP3 : P5.3 Multi-function Selection\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P5.3 is selected
#1 : 1
The SPI2_CLK function is selected
End of enumeration elements list.
P5_MFP4 : P5.4 Multi-function Selection\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P5.4 is selected
#1 : 1
The SPI2_SS function is selected
End of enumeration elements list.
P5_MFP5 : P5.5 Multi-function Selection\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P5.5 is selected
#1 : 1
The CLKO function is selected
End of enumeration elements list.
P5_MFP6 : P5.6 Multi-function Selection\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P5.6 is selected
#1 : 1
The BPWM0_CH0 function is selected
End of enumeration elements list.
P5_MFP7 : P5.7 Multi-function Selection\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P5.7 is selected
#1 : 1
The BPWM0_CH1 function is selected
End of enumeration elements list.
P5_ALT0 : P5.0 Alternative Function\nSee P5_MFP[0].
bits : 8 - 8 (1 bit)
access : read-write
P5_ALT1 : P5.1 Alternative Function\nSee P5_MFP[1].
bits : 9 - 9 (1 bit)
access : read-write
P5_ALT2 : P5.2 Alternative Function\nSee P5_MFP[2].
bits : 10 - 10 (1 bit)
access : read-write
P5_TYPE : Port 5 Schmitt Trigger Input Enable Bit\n
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0 : 0
Port 5 bit m Schmitt trigger input function Disabled
1 : 1
Port 5 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P6 Multiple Function and Input Type Control Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P6_MFP0 : P6.0 Multi-function Selection\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P6.0 is selected
#1 : 1
The EADC0_CH0 function is selected
End of enumeration elements list.
P6_MFP1 : P6.1 Multi-function Selection\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P6.1 is selected
#1 : 1
The EADC0_CH1 function is selected
End of enumeration elements list.
P6_MFP2 : P6.2 Multi-function Selection\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P6.2 is selected
#1 : 1
The EADC0_CH2 function is selected
End of enumeration elements list.
P6_MFP3 : P6.3 Multi-function Selection\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P6.3 is selected
#1 : 1
The EADC0_CH3 function is selected
End of enumeration elements list.
P6_MFP4 : P6.4 Multi-function Selection\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P6.4 is selected
#1 : 1
The EADC0_CH4 or ACMP1_N function is selected
End of enumeration elements list.
P6_MFP5 : P6.5 Multi-function Selection\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P6.5 is selected
#1 : 1
The EADC0_CH5 or ACMP1_P function is selected
End of enumeration elements list.
P6_MFP6 : P6.6 Multi-function Selection\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P6.6 is selected
#1 : 1
The EADC0_CH6 function is selected
End of enumeration elements list.
P6_MFP7 : P6.7 Multi-function Selection\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P6.7 is selected
#1 : 1
The EADC0_CH7 function is selected
End of enumeration elements list.
P6_TYPE : Port 6 Schmitt Trigger Input Enable Bit\n
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0 : 0
Port 6 bit m Schmitt trigger input function Disabled
1 : 1
Port 6 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P7 Multiple Function and Input Type Control Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P7_MFP0 : P7.0 Multi-function Selection\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P7.0 is selected
#1 : 1
The EADC1_CH0 function is selected
End of enumeration elements list.
P7_MFP1 : P7.1 Multi-function Selection\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P7.1 is selected
#1 : 1
The EADC1_CH1 function is selected
End of enumeration elements list.
P7_MFP2 : P7.2 Multi-function Selection\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P7.2 is selected
#1 : 1
The EADC1_CH2 function is selected
End of enumeration elements list.
P7_MFP3 : P7.3 Multi-function Selection\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P7.3 is selected
#1 : 1
The EADC1_CH3 function is selected
End of enumeration elements list.
P7_MFP4 : P7.4 Multi-function Selection\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P7.4 is selected
#1 : 1
The EADC1_CH4 or ACMP2_N function is selected
End of enumeration elements list.
P7_MFP5 : P7.5 Multi-function Selection\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P7.5 is selected
#1 : 1
The EADC1_CH5 or ACMP2_P function is selected
End of enumeration elements list.
P7_MFP6 : P7.6 Multi-function Selection\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P7.6 is selected
#1 : 1
The EADC1_CH6 function is selected
End of enumeration elements list.
P7_MFP7 : P7.7 Multi-function Selection\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P7.7 is selected
#1 : 1
The EADC1_CH7 function is selected
End of enumeration elements list.
P7_TYPE : Port 7 Schmitt Trigger Input Enable Bit\n
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0 : 0
Port 7 bit m Schmitt trigger input function Disabled
1 : 1
Port 7 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P8 Multiple Function and Input Type Control Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P8_MFP0 : P8.0 Multi-function Selection\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P8.0 is selected
#1 : 1
The OP0_P function is selected
End of enumeration elements list.
P8_MFP1 : P8.1 Multi-function Selection\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P8.1 is selected
#1 : 1
The OP0_N function is selected
End of enumeration elements list.
P8_MFP2 : P8.2 Multi-function Selection\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P8.2 is selected
#1 : 1
The OP0_O function is selected
End of enumeration elements list.
P8_MFP3 : P8.3 Multi-function Selection\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P8.3 is selected
#1 : 1
The ACMP0_N function is selected
End of enumeration elements list.
P8_MFP4 : P8.4 Multi-function Selection\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P8.4 is selected
#1 : 1
The ACMP0_P function is selected
End of enumeration elements list.
P8_MFP7 : P8.7 Multi-function Selection\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P8.7 is selected
#1 : 1
The ACMP0_O function is selected
End of enumeration elements list.
P8_TYPE : Port 8 Schmitt Trigger Input Enable Bits\n
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0 : 0
Port 8 bit m Schmitt trigger input function Disabled
1 : 1
Port 8 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
P9 Multiple Function and Input Type Control Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P9_MFP0 : P9.0 Multi-function Selection\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P9.0 is selected
#1 : 1
The OP1_O function is selected
End of enumeration elements list.
P9_MFP1 : P9.1 Multi-function Selection\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P9.1 is selected
#1 : 1
The OP1_N function is selected
End of enumeration elements list.
P9_MFP2 : P9.2 Multi-function Selection\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P9.2 is selected
#1 : 1
The OP1_P function is selected
End of enumeration elements list.
P9_MFP3 : P9.3 Multi-function Selection\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P9.3 is selected
#1 : 1
The EPWM1_BRAKE1 function is selected
End of enumeration elements list.
P9_MFP4 : P9.4 Multi-function Selection\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P9.4 is selected
#1 : 1
The SPI1_CLK function is selected
End of enumeration elements list.
P9_MFP5 : P9.5 Multi-function Selection\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P9.5 is selected
#1 : 1
The SPI1_MISO function is selected
End of enumeration elements list.
P9_MFP6 : P9.6 Multi-function Selection\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P9.6 is selected
#1 : 1
The SPI1_MOSI function is selected
End of enumeration elements list.
P9_MFP7 : P9.7 Multi-function Selection\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO P9.7 is selected
#1 : 1
The SPI1_SS function is selected
End of enumeration elements list.
P9_TYPE : Port 9 Schmitt Trigger Input Enable Bits\n
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0 : 0
Port 9 bit m Schmitt trigger input function Disabled
1 : 1
Port 9 bit m Schmitt trigger input function Enabled
End of enumeration elements list.
PA Multiple Function and Input Type Control Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA_MFP0 : PA.0 Multi-function Selection\nBits PA_ALT[0] and PA_MFP[0] determine the PA.0 function.\n(PA_ALT[0], PA_MFP[0]) value and function mapping is as following list.\n
bits : 0 - 0 (1 bit)
access : read-write
PA_MFP1 : PA.1 Multi-function Selection\nBits PA_ALT[1] and PA_MFP[1] determine the PA.1 function.\n(PA_ALT[1], PA_MFP[1]) value and function mapping is as following list.\n
bits : 1 - 1 (1 bit)
access : read-write
PA_ALT0 : PA.0 Alternative Function\nSee PA_MFP[0].
bits : 8 - 8 (1 bit)
access : read-write
PA_ALT1 : PA.1 Alternative Function\nSee PA_MFP[1].
bits : 9 - 9 (1 bit)
access : read-write
PA_TYPE : Port a Schmitt Trigger Input Enable Bits\n
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0 : 0
Port A bit m Schmitt trigger input function Disabled
1 : 1
Port A bit m Schmitt trigger input function Enabled
End of enumeration elements list.
Peripheral Reset Control Register1
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIP_RST : Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIP_RST is the same as the POR reset. All the chip controllers are reset and the chip setting from flash are also reload.\nNote: This bit is write protected. Refer to the REGWRPROT register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip normal operation
#1 : 1
Chip one-shot reset
End of enumeration elements list.
CPU_RST : Cortex-M0 Core One-shot Reset (Write Protect)\nSetting this bit will only reset the CPU kernel and Flash Memory Controller (FMC), and this bit will automatically return 0 after the two clock cycles.\nNote: This bit is write protected. Refer to the REGWRPROT register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
CPU normal operation
#1 : 1
CPU one-shot reset
End of enumeration elements list.
HDIV_RST : HDIV Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the hardware divider. User need to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the REGWRPROT register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware divider controller normal operation
#1 : 1
Hardware divider controller reset
End of enumeration elements list.
Peripheral Reset Control Register2
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO_RST : GPIO Controller Reset\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO controller normal operation
#1 : 1
GPIO controller reset
End of enumeration elements list.
TMR0_RST : Timer0 Controller Reset\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 controller normal operation
#1 : 1
Timer0 controller reset
End of enumeration elements list.
TMR1_RST : Timer1 Controller Reset\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 controller normal operation
#1 : 1
Timer1 controller reset
End of enumeration elements list.
TMR2_RST : Timer2 Controller Reset\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 controller normal operation
#1 : 1
Timer2 controller reset
End of enumeration elements list.
TMR3_RST : Timer3 Controller Reset\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer3 controller normal operation
#1 : 1
Timer3 controller reset
End of enumeration elements list.
I2C0_RST : I2C0 Controller Reset\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C0 controller normal operation
#1 : 1
I2C0 controller reset
End of enumeration elements list.
SPI0_RST : SPI0 Controller Reset\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI0 controller normal operation
#1 : 1
SPI0 controller reset
End of enumeration elements list.
SPI1_RST : SPI1 Controller Reset\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI1 controller normal operation
#1 : 1
SPI1 controller reset
End of enumeration elements list.
SPI2_RST : SPI2 Controller Reset\n
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI2 controller normal operation
#1 : 1
SPI2 controller reset
End of enumeration elements list.
UART0_RST : UART0 Controller Reset\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 controller normal operation
#1 : 1
UART0 controller reset
End of enumeration elements list.
UART1_RST : UART1 Controller Reset\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 controller normal operation
#1 : 1
UART1 controller reset
End of enumeration elements list.
BPWM0_RST : Basic PWM0 Controller Reset\n
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Basic PWM0 controller normal operation
#1 : 1
Basic PWM0 controller reset
End of enumeration elements list.
EPWM0_RST : Enhanced PWM0 Controller Reset\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM0 controller normal operation
#1 : 1
EPWM0 controller reset
End of enumeration elements list.
EPWM1_RST : Enhanced PWM1 Controller Reset\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM1 controller normal operation
#1 : 1
EPWM1 controller reset
End of enumeration elements list.
ACMP_RST : Analog Comparator Controller Reset\n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog Comparator controller normal operation
#1 : 1
Analog Comparator controller reset
End of enumeration elements list.
ECAP0_RST : Enhanced Input Capture 0 Controller Reset\n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enhanced input capture 0 controller normal operation
#1 : 1
Enhanced input capture 0 controller reset
End of enumeration elements list.
ECAP1_RST : Enhanced Input Capture 1 Controller Reset\n
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enhanced input capture 1 controller normal operation
#1 : 1
Enhanced input capture 1 controller reset
End of enumeration elements list.
EADC_RST : EADC Controller Reset\n
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
EADC controller normal operation
#1 : 1
EADC controller reset
End of enumeration elements list.
OPA_RST : OPA0 and OPA1 Controller Reset\n
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
OPA0 and OPA1 controller normal operation
#1 : 1
OPA0 and OPA1 controller reset
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.