\n
address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
System Power-down Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTL12M_EN : External 4~24 MHz Crystal Enable Bit (Write Protect)\nThe bit default value is set by flash controller user configuration register CFOSC (Config0[26:24]). When the default clock source is from external 4~24 MHz crystal, this bit is set to 1 automatically.\nNote: This bit is write protected bit. Refer to the REGWRPROT register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
External 4~24 MHz crystal Disabled
#1 : 1
External 4~24 MHz crystal Enabled
End of enumeration elements list.
OSC22M_EN : Internal 22.1184 MHz Oscillator Enable Bit (Write Protect)\nNote: This bit is write protected bit. Refer to the REGWRPROT register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
22.1184 MHz Oscillation Disabled
#1 : 1
22.1184 MHz Oscillation Enabled
End of enumeration elements list.
OSC10K_EN : Internal 10 kHz Oscillator Enable Bit (Write Protect)\nNote: This bit is write protected bit. Refer to the REGWRPROT register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
10 kHz Oscillation Disabled
#1 : 1
10 kHz Oscillation Enabled
End of enumeration elements list.
PD_WU_INT_EN : Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote1: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.\nNote2: This bit is write protected bit. Refer to the REGWRPROT register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power-down mode wake-up interrupt Disabled
#1 : 1
Power-down mode wake-up interrupt Enabled
End of enumeration elements list.
PD_WU_STS : Power-down Mode Wake-up Interrupt Status
Set by power down wake up event , it indicates that resume from Power-down mode.
Write 1 to clear the bit to zero.
Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1.
bits : 6 - 6 (1 bit)
access : read-write
Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLK_S : HCLK Clock Source Selection (Write Protect)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turn on.\nThe 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b.\nNote: These bits are write protected bits. Refer to the REGWRPROT register.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external 4~24 MHz crystal clock
#001 : 1
Reserved
#010 : 2
Clock source from PLL clock
#011 : 3
Clock source from internal 10 kHz oscillator clock
#111 : 7
Clock source from internal 22.1184 MHz oscillator clock
End of enumeration elements list.
STCLK_S : Cortex-M0 SysTick Clock Source Selection (Write Protect)\n
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external 4~24 MHz crystal clock
#001 : 1
Reserved
#010 : 2
Clock source from external 4~24 MHz crystal clock/2
#011 : 3
Clock source from HCLK/2
#111 : 7
Clock source from internal 22.1184 MHz oscillator clock/2
End of enumeration elements list.
Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_S : Watchdog Timer Clock Source Selection (Write Protect)\nNote: These bits are write protected bits. Refer to the REGWRPROT register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from HCLK/128 clock
#01 : 1
Clock source from HCLK/512 clock
#10 : 2
Clock source from HCLK/2048 clock
#11 : 3
Clock source from internal 10 kHz oscillator clock
End of enumeration elements list.
SPI0_S : SPI0 Clock Source Selection\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from PLL clock
#1 : 1
Clock source from HCLK
End of enumeration elements list.
SPI1_S : SPI1 Clock Source Selection\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from PLL clock
#1 : 1
Clock source from HCLK
End of enumeration elements list.
SPI2_S : SPI2 Clock Source Selection\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from PLL clock
#1 : 1
Clock source from HCLK
End of enumeration elements list.
UART_S : UART Clock Source Selection\n
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external 4~24 MHz crystal clock
#01 : 1
Clock source from PLL clock
#10 : 2
Reserved
#11 : 3
Clock source from internal 22.1184 MHz oscillator clock
End of enumeration elements list.
Clock Divider Number Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLK_N : HCLK Clock Divider\n
bits : 0 - 3 (4 bit)
access : read-write
UART_N : UART Clock Divider\n
bits : 8 - 11 (4 bit)
access : read-write
EADC_N : EADC Clock Divider\n
bits : 16 - 23 (8 bit)
access : read-write
Clock Source Select Control Register 2
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRQDIV_S : Clock Divider Clock Source Selection\n
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from external 4~24 MHz crystal clock
#01 : 1
Reserved
#10 : 2
Clock source from HCLK
#11 : 3
Clock source from internal 22.1184 MHz oscillator clock
End of enumeration elements list.
WWDT_S : Window Watchdog Timer Clock Source Selection\n
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved
#01 : 1
Reserved
#10 : 2
Clock source from HCLK/2048 clock
#11 : 3
Clock source from internal 10 kHz low speed oscillator clock
End of enumeration elements list.
PLL Control Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FB_DV : PLL Feedback Divider Control Bits\nRefer to the formulas below the table.
bits : 0 - 8 (9 bit)
access : read-write
IN_DV : PLL Input Divider Control Bits\nRefer to the formulas below the table.
bits : 9 - 13 (5 bit)
access : read-write
OUT_DV : PLL Output Divider Control Bits\nRefer to the formulas below the table.
bits : 14 - 15 (2 bit)
access : read-write
PD : Power-down Mode\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is in normal mode
#1 : 1
PLL is in power-down mode (default)
End of enumeration elements list.
BP : PLL Bypass Control\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is in normal mode (default)
#1 : 1
PLL clock output is same as clock input
End of enumeration elements list.
OE : PLL OE (FOUT Enable) Bit\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL FOUT enable
#1 : 1
PLL FOUT is fixed low
End of enumeration elements list.
PLL_SRC : PLL Source Clock Selection\n
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL source clock from external 4~24 MHz crystal
#1 : 1
PLL source clock from internal 22.1184 MHz oscillator
End of enumeration elements list.
FCO_SEL : PLL FCO Selection\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
When the FCO frequency range between 100MHz and 200MHz, this bit should be set as 0
#1 : 1
When the FCO frequency range between 200MHz to 500MHz, this bit should be set as 1
End of enumeration elements list.
Frequency Divider Control Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSEL : Frequency Divider Output Selection Bits\nThe output formula is:\nwhere FFRQDIV_CLK is the input clock frequency, FCLKO is the clock divider output frequency and N is the 4-bit value in FSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write
DIVIDER_EN : Frequency Divider Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frequency divider Disabled
#1 : 1
Frequency divider Enabled
End of enumeration elements list.
DIV1 : Frequency Divider Divide 1 Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frequency divider will output clock with source frequency divide by FSEL
#1 : 1
Frequency divider will output clock with source frequency
End of enumeration elements list.
AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HDIV_EN : Hardware Divider Controller Clock Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Hardware Divider engine clock Disabled
#1 : 1
Hardware Divider engine clock Enabled
End of enumeration elements list.
APB Devices Clock Enable Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_EN : Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected bit. Refer to the REGWRPROT register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog Timer clock Disabled
#1 : 1
Watchdog Timer clock Enabled
End of enumeration elements list.
TMR0_EN : Timer0 Clock Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 clock Disabled
#1 : 1
Timer0 clock Enabled
End of enumeration elements list.
TMR1_EN : Timer1 Clock Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 clock Disabled
#1 : 1
Timer1 clock Enabled
End of enumeration elements list.
TMR2_EN : Timer2 Clock Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 clock Disabled
#1 : 1
Timer2 clock Enabled
End of enumeration elements list.
TMR3_EN : Timer3 Clock Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer3 clock Disabled
#1 : 1
Timer3 clock Enabled
End of enumeration elements list.
FDIV_EN : Frequency Divider Output Clock Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frequency divider output clock Disabled
#1 : 1
Frequency divider output clock Enabled
End of enumeration elements list.
I2C0_EN : I2C0 Clock Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C0 clock Disabled
#1 : 1
I2C0 clock Enabled
End of enumeration elements list.
SPI0_EN : SPI0 Clock Enable Bit\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI0 clock Disabled
#1 : 1
SPI0 clock Enabled
End of enumeration elements list.
SPI1_EN : SPI1 Clock Enable Bit\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI1 clock Disabled
#1 : 1
SPI1 clock Enabled
End of enumeration elements list.
SPI2_EN : SPI2 Clock Enable Bit\n
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI2 clock Disabled
#1 : 1
SPI2 clock Enabled
End of enumeration elements list.
UART0_EN : UART0 Clock Enable Bit\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 clock Disabled
#1 : 1
UART0 clock Enabled
End of enumeration elements list.
UART1_EN : UART1 Clock Enable Bit\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 clock Disabled
#1 : 1
UART1 clock Enabled
End of enumeration elements list.
BPWM0_EN : Basic PWM0 Clock Enable Bit\n
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Basic PWM0 clock Disabled
#1 : 1
Basic PWM0 clock Enabled
End of enumeration elements list.
EPWM0_EN : Enhanced PWM0 Clock Enable Bit\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enhanced PWM0 clock Disabled
#1 : 1
Enhanced PWM0 clock Enabled
End of enumeration elements list.
EPWM1_EN : Enhanced PWM1 Clock Enable Bit\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enhanced PWM1 clock Disabled
#1 : 1
Enhanced PWM1 clock Enabled
End of enumeration elements list.
ACMP_EN : Analog Comparator Clock Enable Bit\n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog comparator clock Disabled
#1 : 1
Analog comparator clock Enabled
End of enumeration elements list.
ECAP0_EN : Enhanced Input Capture 0 Clock Enable Bit\n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enhanced input capture 0 clock Disabled
#1 : 1
Enhanced input capture 0 clock Enabled
End of enumeration elements list.
ECAP1_EN : Enhanced Input Capture 1 Clock Enable Bit\n
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enhanced input capture 1 clock Disabled
#1 : 1
Enhanced input capture 1 clock Enabled
End of enumeration elements list.
EADC_EN : EADC Clock Enable Bit\n
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
EADC clock Disabled
#1 : 1
EADC clock Enabled
End of enumeration elements list.
OPA_EN : OPA0 and OPA1 Clock Enable Bit\n
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
OPA0 and OPA1 clock Disabled
#1 : 1
OPA0 and OPA1 clock Enabled
End of enumeration elements list.
Clock Status Monitor Register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
XTL12M_STB : External 4~24 MHz Crystal Clock Source Stable Flag (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
External 4~24 MHz crystal clock is not stable or disabled
#1 : 1
External 4~24 MHz crystal clock is stable and enabled
End of enumeration elements list.
PLL_STB : PLL Clock Source Stable Flag (Read Only)\n
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
PLL clock is not stable or disabled
#1 : 1
PLL clock is stable in normal mode
End of enumeration elements list.
OSC10K_STB : Internal 10k Hz Clock Source Stable Flag (Read Only)\n
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal 10k Hz oscillator clock is not stable or disabled
#1 : 1
Internal 10k Hz oscillator clock is stable and enabled
End of enumeration elements list.
OSC22M_STB : Internal 22.1184M Hz Oscillator Clock Source Stable Flag (Read Only)\n
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal 22.1184M Hz oscillator clock is not stable or disabled
#1 : 1
Internal 22.1184M Hz oscillator clock is stable and enabled
End of enumeration elements list.
CLK_SW_FAIL : Clock Switching Fail Flag (Read Only)\nThis bit is an index that if current system clock source is match as user defined at HCLK_S (CLKSEL0[2:0]). When user switch system clock, the system clock source will keep old clock until the new clock is stable. During the period that waiting new clock stable, this bit will be an index shows system clock source is not match as user wanted.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Clock switching success
#1 : 1
Clock switching failure
End of enumeration elements list.
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