\n

NVIC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x80 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x180 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x300 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

Registers

NVIC_ISER (ISER)

NVIC_ISPR (ISPR)

NVIC_ICPR (ICPR)

NVIC_IPR0 (IPR0)

NVIC_IPR1 (IPR1)

NVIC_IPR2 (IPR2)

NVIC_IPR3 (IPR3)

NVIC_IPR4 (IPR4)

NVIC_IPR5 (IPR5)

NVIC_IPR6 (IPR6)

NVIC_IPR7 (IPR7)

NVIC_ICER (ICER)


NVIC_ISER (ISER)

IRQ0 ~ IRQ31 Set-enable Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISER NVIC_ISER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt Enable Register\nEnable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite:\nRead value indicates the current enable status.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect.\nAssociated interrupt status is Disabled

1 : 1

Write 1 to enable associated interrupt.\nAssociated interrupt status is Enabled

End of enumeration elements list.


NVIC_ISPR (ISPR)

IRQ0 ~ IRQ31 Set-pending Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISPR NVIC_ISPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Set Interrupt Pending Register\nWrite:\nRead value indicates the current pending status.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect.\nAssociated interrupt in not in pending status

1 : 1

Write 1 to set pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status

End of enumeration elements list.


NVIC_ICPR (ICPR)

IRQ0 ~ IRQ31 Clear-pending Control Register
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICPR NVIC_ICPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : Clear Interrupt Pending Register\nWrite:\nRead value indicates the current pending status.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect.\nAssociated interrupt in not in pending status

1 : 1

Write 1 to clear pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status

End of enumeration elements list.


NVIC_IPR0 (IPR0)

IRQ0 ~ IRQ3 Interrupt Priority Control Register
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR0 NVIC_IPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority of IRQ0 0 denotes the highest priority and 3 denotes lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI_1 : Priority of IRQ1 0 denotes the highest priority and 3 denotes lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI_2 : Priority of IRQ2 0 denotes the highest priority and 3 denotes lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI_3 : Priority of IRQ3 0 denotes the highest priority and 3 denotes lowest priority.
bits : 30 - 31 (2 bit)
access : read-write


NVIC_IPR1 (IPR1)

IRQ4 ~ IRQ7 Interrupt Priority Control Register
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR1 NVIC_IPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_4 PRI_5 PRI_6 PRI_7

PRI_4 : Priority of IRQ4 0 denotes the highest priority and 3 denotes lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI_5 : Priority of IRQ5 0 denotes the highest priority and 3 denotes lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI_6 : Priority of IRQ6 0 denotes the highest priority and 3 denotes lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI_7 : Priority of IRQ7 0 denotes the highest priority and 3 denotes lowest priority.
bits : 30 - 31 (2 bit)
access : read-write


NVIC_IPR2 (IPR2)

IRQ8 ~ IRQ11 Interrupt Priority Control Register
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR2 NVIC_IPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_8 PRI_9 PRI_10 PRI_11

PRI_8 : Priority of IRQ8 0 denotes the highest priority and 3 denotes lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI_9 : Priority of IRQ9 0 denotes the highest priority and 3 denotes lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI_10 : Priority of IRQ10 0 denotes the highest priority and 3 denotes lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI_11 : Priority of IRQ11 0 denotes the highest priority and 3 denotes lowest priority.
bits : 30 - 31 (2 bit)
access : read-write


NVIC_IPR3 (IPR3)

IRQ12 ~ IRQ15 Interrupt Priority Control Register
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR3 NVIC_IPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_12 PRI_13 PRI_14 PRI_15

PRI_12 : Priority of IRQ12 0 denotes the highest priority and 3 denotes lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI_13 : Priority of IRQ13 0 denotes the highest priority and 3 denotes lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI_14 : Priority of IRQ14 0 denotes the highest priority and 3 denotes lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI_15 : Priority of IRQ15 0 denotes the highest priority and 3 denotes lowest priority.
bits : 30 - 31 (2 bit)
access : read-write


NVIC_IPR4 (IPR4)

IRQ16 ~ IRQ19 Interrupt Priority Control Register
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR4 NVIC_IPR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_16 PRI_17 PRI_18 PRI_19

PRI_16 : Priority of IRQ16 0 denotes the highest priority and 3 denotes lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI_17 : Priority of IRQ17 0 denotes the highest priority and 3 denotes lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI_18 : Priority of IRQ18 0 denotes the highest priority and 3 denotes lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI_19 : Priority of IRQ19 0 denotes the highest priority and 3 denotes lowest priority.
bits : 30 - 31 (2 bit)
access : read-write


NVIC_IPR5 (IPR5)

IRQ20 ~ IRQ23 Interrupt Priority Control Register
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR5 NVIC_IPR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_20 PRI_21 PRI_22 PRI_23

PRI_20 : Priority of IRQ20 0 denotes the highest priority and 3 denotes lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI_21 : Priority of IRQ21 0 denotes the highest priority and 3 denotes lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI_22 : Priority of IRQ22 0 denotes the highest priority and 3 denotes lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI_23 : Priority of IRQ23 0 denotes the highest priority and 3 denotes lowest priority.
bits : 30 - 31 (2 bit)
access : read-write


NVIC_IPR6 (IPR6)

IRQ24 ~ IRQ27 Interrupt Priority Control Register
address_offset : 0x318 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR6 NVIC_IPR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_24 PRI_25 PRI_26 PRI_27

PRI_24 : Priority of IRQ24 0 denotes the highest priority and 3 denotes lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI_25 : Priority of IRQ25 0 denotes the highest priority and 3 denotes lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI_26 : Priority of IRQ26 0 denotes the highest priority and 3 denotes lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI_27 : Priority of IRQ27 0 denotes the highest priority and 3 denotes lowest priority.
bits : 30 - 31 (2 bit)
access : read-write


NVIC_IPR7 (IPR7)

IRQ28 ~ IRQ31 Interrupt Priority Control Register
address_offset : 0x31C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR7 NVIC_IPR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_28 PRI_29 PRI_30 PRI_31

PRI_28 : Priority of IRQ28 0 denotes the highest priority and 3 denotes lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI_29 : Priority of IRQ29 0 denotes the highest priority and 3 denotes lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI_30 : Priority of IRQ30 0 denotes the highest priority and 3 denotes lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI_31 : Priority of IRQ31 0 denotes the highest priority and 3 denotes lowest priority.
bits : 30 - 31 (2 bit)
access : read-write


NVIC_ICER (ICER)

IRQ0 ~ IRQ31 Clear-enable Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICER NVIC_ICER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : Interrupt Disable Register\nDisable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite:\nRead value indicates the current enable status.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect.\nAssociated interrupt status is Disabled

1 : 1

Write 1 to disable associated interrupt.\nAssociated interrupt status is Enabled

End of enumeration elements list.



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