SYS_PDID (PDID)

SYS_IPRST2 (IPRST2)

SYS_REGLCTL (REGLCTL)

SYS_TSOFFSET (TSOFFSET)

SYS_BODCTL (BODCTL)

SYS_IVSCTL (IVSCTL)

SYS_PORCTL (PORCTL)

SYS_VREFCTL (VREFCTL)

SYS_GPA_MFPL (GPA_MFPL)

SYS_GPA_MFPH (GPA_MFPH)

SYS_GPB_MFPL (GPB_MFPL)

SYS_GPB_MFPH (GPB_MFPH)

SYS_RSTSTS (RSTSTS)

SYS_GPC_MFPL (GPC_MFPL)

SYS_GPC_MFPH (GPC_MFPH)

SYS_GPD_MFPL (GPD_MFPL)

SYS_GPD_MFPH (GPD_MFPH)

SYS_GPE_MFPL (GPE_MFPL)

SYS_GPE_MFPH (GPE_MFPH)

SYS_GPF_MFPL (GPF_MFPL)

SYS_IPRST0 (IPRST0)

SYS_IRCTCTL0 (IRCTCTL0)

SYS_IRCTIEN (IRCTIEN)

SYS_IRCTISTS (IRCTISTS)

SYS_IRCTCTL1 (IRCTCTL1)

SYS_IPRST1 (IPRST1)

SYS_MODCTL (MODCTL)

PDID : Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only

SC0RST : SC0 Controller Reset
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SC1RST : SC1 Controller Reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USCI0RST : USCI0 Controller Reset
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USCI1RST : USCI1 Controller Reset
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USCI2RST : USCI2 Controller Reset
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REGLCTL0 : Register Lock Control Disable Index (Read Only)\nThe Protected registers are:\nSYS_IPRST0: address 0x5000_0008\nSYS_BODCTL: address 0x5000_0018\nSYS_PORCTL: address 0x5000_0024\nSYS_VREFCTL: address 0x5000_0028\nCLK_PWRCTL[13]: address 0x5000_0200 (HIRC48 Enable Bit)\nCLK_PWRCTL[12]: address 0x5000_0200 (HXT Crystal Type Select Bit)\nCLK_PWRCTL[11:10]: address 0x5000_0200 (HXT Gain Control Bit)\nCLK_PWRCTL[7]: address 0x5000_0200 (System Power-down Enable)\nCLK_PWRCTL[5]: address 0x5000_0200 (Power-down Mode Wake-up Interrupt Enable Bit)\nCLK_PWRCTL[4]: address 0x5000_0200 (Enable the Wake-up Delay Counter)\nCLK_PWRCTL[3]: address 0x5000_0200 (LIRC Enable Bit)\nCLK_PWRCTL[2]: address 0x5000_0200 (HIRC Enable Bit)\nCLK_PWRCTL[1]: address 0x5000_0200 (LXT Enable Bit)\nCLK_PWRCTL[0]: address 0x5000_0200 (HXT Enable Bit)\nCLK_APBCLK0 [0]: address 0x5000_0208 (bit[0] is watchdog clock enable)\nCLK_CLKSEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source select)\nCLK_CLKSEL1 [1:0]: address 0x5000_0214 (for watchdog clock source select)\nCLK_CLKDSTS: address 0x5000_0274\nFMC_ISPCTL: address 0x5000_C000 (Flash ISP Control register)\nFMC_ISPTRG: address 0x5000_C010 (ISP Trigger Control register)\nFMC_ISPSTS: address 0x5000_C040\nWDT_CTL: address 0x4000_4000\nFMC_FTCTL: address 0x5000_C018\nPWM0_CTL: address 0x4004_0000 \nPWM1_CTL: address 0x4014_0000\nPWM0_DTCTL0_1: address 0x4004_0070\nPWM1_DTCTL0_1: address 0x4014_0070\nPWM0_DTCTL2_3: address 0x4004_0074\nPWM1_DTCTL2_3: address 0x4014_0074\nPWM0_DTCTL4_5: address 0x4004_0078\nPWM1_DTCTL4_5: address 0x4014_0078\nPWM0_BRKCTL0_1: address 0x4004_00C8\nPWM1_BRKCTL0_1: address 0x4014_00C8\nPWM0_BRKCTL2_3: address 0x4004_00CC\nPWM1_BRKCTL2_3: address 0x4014_00CC\nPWM0_BRKCTL4_5: address 0x4004_00D0\nPWM1_BRKCTL4_5: address 0x4014_00D0\nPWM0_INTEN1: address 0x4004_00E4\nPWM1_INTEN1: address 0x4014_00E4\nPWM0_INTSTS1: address 0x4004_00EC\nPWM1_INTSTS1: address 0x4014_00EC\nTIMER0_PWMCTL: address 0x4001_0040\nTIMER1_PWMCTL: address 0x4001_0140\nTIMER2_PWMCTL: address 0x4011_0040\nTIMER3_PWMCTL: address 0x4011_0140\nTIMER0_PWMDTCTL: address 0x4001_0058\nTIMER1_PWMDTCTL: address 0x4001_0158\nTIMER2_PWMDTCTL: address 0x4011_0058\nTIMER3_PWMDTCTL: address 0x4011_0158\nTIMER0_PWMBRKCTL: address 0x4001_0070\nTIMER1_PWMBRKCTL: address 0x4001_0170\nTIMER2_PWMBRKCTL: address 0x4011_0070\nTIMER3_PWMBRKCTL: address 0x4011_0170\nTIMER0_PWMSWBRK: address 0x4001_007C\nTIMER1_PWMSWBRK: address 0x4001_017C\nTIMER2_PWMSWBRK: address 0x4011_007C\nTIMER3_PWMSWBRK: address 0x4011_017C\nTIMER0_PWMINTEN1: address 0x4001_0084\nTIMER1_PWMINTEN1: address 0x4001_0184\nTIMER2_PWMINTEN1: address 0x4011_0084\nTIMER3_PWMINTEN1: address 0x4011_0184\nTIMER0_PWMINTSTS1: address 0x4001_008C\nTIMER1_PWMINTSTS1: address 0x4001_018C\nTIMER2_PWMINTSTS1: address 0x4011_008C\nTIMER3_PWMINTSTS1: address 0x4011_018
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REGLCTL : Register Lock Control Code (Write Only)\nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h', '16h', '88h' to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
bits : 1 - 7 (7 bit)
access : write-only

VTEMP : Temperature Sensor Offset Value \nThis field reflects temperature sensor output voltage offset at 25oC from flash.
bits : 0 - 11 (12 bit)
access : read-only

BODEN : Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODVL : Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by flash controller user configuration register CBOV (CONFIG0 [22:21]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODRSTEN : Brown-out Reset Enable Bit (Write Protect) The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit. Note1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will keep till to the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODIF : Brown-out Detector Interrupt Flag\nNote: This bit can be cleared by software writing '1'.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODLPM : Brown-out Detector Low Power Mode (Write Protect)\nNote1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODOUT : Brown-out Detector Output Status\nIt means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled, this bit always responds 0.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVREN : Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote1: After enabling the bit, the LVR function will be active with 200us delay for LVR output stable (default).\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODDGSEL : Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVRDGSEL : LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VDETEN : Voltage Detector Enable Bit\nNote1: This function is still active in whole chip power-down mode.\nNote2: This function need use LIRC or LXT as VDET clock source, which is selected in VDETCKSEL (CLK_BODCLK[0]).\nNote2: The input pin for VDET detect voltage is selectabe by VDETPINSEL (SYS_BODCTL[17]).
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VDETPINSEL : Voltage Detector External Input Voltage Pin Selection\nNote1: If VDET_P0 is selected, multi-function pin must be selected correctly in PB0MFP (SYS_GPB_MFPL[3:0]).\nNote2: If VDET_P1 is selected, multi-function pin must be selected correctly in PB1MFP (SYS_GPB_MFPL[7:4]).
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VDETIEN : Voltage Detector Interrupt Enable Bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VDETIF : Voltage Detector Interrupt Flag\nNote: This bit can be cleared by software writing '1'.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VDETOUT : Voltage Detector Output Status\nIt means the detected voltage is lower than Bandgap. If the VDETEN is 0, VDET function disabled, this bit always responds 0.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VDETDGSEL : Voltage Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 25 - 27 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VTEMPEN : Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result. Please refer to ADC function chapter for details.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VBATUGEN : VBAT Unity Gain Buffer Enable Bit\nThis bit is used to enable/disable VBAT unity gain buffer function.\nNote: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result. Please refer to ADC function chapter for details.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POROFF : Power-on Reset Enable Bit (Write Protect) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 15 (16 bit)
access : read-write

VREFCTL : Int_VREF Control Bits (Write Protect)\nNote: These bit are write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA0MFP : PA.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PA1MFP : PA.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PA2MFP : PA.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PA3MFP : PA.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PA4MFP : PA.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PA5MFP : PA.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PA6MFP : PA.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PA7MFP : PA.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PA8MFP : PA.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PA9MFP : PA.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PA10MFP : PA.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PA11MFP : PA.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PA12MFP : PA.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PA13MFP : PA.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PA14MFP : PA.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PA15MFP : PA.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PB0MFP : PB.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PB1MFP : PB.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PB2MFP : PB.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PB3MFP : PB.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PB4MFP : PB.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PB5MFP : PB.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PB6MFP : PB.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PB7MFP : PB.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PB8MFP : PB.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PB9MFP : PB.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PB10MFP : PB.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PB11MFP : PB.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PB12MFP : PB.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PB13MFP : PB.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PB14MFP : PB.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PB15MFP : PB.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PORF : POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: This bit can be cleared by software writing '1'.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINRF : nRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.\nNote: This bit can be cleared by software writing '1'.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTRF : WDT Reset Flag\nThe WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\nNote1: This bit can be cleared by software writing '1'.\nNote2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVRF : LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.\nNote: This bit can be cleared by software writing '1'.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODRF : BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-out Detector to indicate the previous reset source.\nNote: This bit can be cleared by software writing '1'.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MCURF : MCU Reset Flag\nThe MCU reset flag is set by the 'Reset Signal' from the Cortex-M0 Core to indicate the previous reset source.\nNote: This bit can be cleared by software writing '1'.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURF : CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC).\nNote: This bit can be cleared by software writing '1'.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPULKRF : CPU Lockup Reset Flag\nThe CPU lockup reset flag is set by hardware If Cortex-M0 lockup happened.\nNote: This bit can be cleared by software writing '1'.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PC0MFP : PC.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PC1MFP : PC.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PC2MFP : PC.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PC3MFP : PC.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PC4MFP : PC.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PC5MFP : PC.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PC6MFP : PC.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PC7MFP : PC.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PC8MFP : PC8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PC9MFP : PC9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PC10MFP : PC10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PC11MFP : PC11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PC12MFP : PC12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PC13MFP : PC13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PC14MFP : PC14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PC15MFP : PC15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PD0MFP : PD.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PD1MFP : PD.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PD2MFP : PD.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PD3MFP : PD.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PD4MFP : PD.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PD5MFP : PD.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PD6MFP : PD.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PD7MFP : PD.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PD8MFP : PD.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PD9MFP : PD.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PD10MFP : PD.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PD11MFP : PD.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PD12MFP : PD.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PD13MFP : PD.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PD14MFP : PD.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PD15MFP : PD.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PE0MFP : PE.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PE1MFP : PE.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PE2MFP : PE.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PE3MFP : PE.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PE4MFP : PE.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PE5MFP : PE.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PE6MFP : PE.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PE7MFP : PE.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

PE8MFP : PE.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PE9MFP : PE.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PE10MFP : PE.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PE11MFP : PE.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write

PE12MFP : PE.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write

PE13MFP : PE.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PF0MFP : PF.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write

PF1MFP : PF.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write

PF2MFP : PF.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write

PF3MFP : PF.3 Multi-function Pin Selection\nThe default value is set by flash controller user configuration register CFGXT1(CONFIG0[27]) bit.
bits : 12 - 15 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PF4MFP : PF.4 Multi-function Pin Selection\nThe default value is set by flash controller user configuration register CFGXT1(CONFIG0[27]) bit.
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PF5MFP : PF.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write

PF6MFP : PF.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write

PF7MFP : PF.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write

CHIPRST : Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.\nAbout the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURST : Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMARST : PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EBIRST : EBI Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the EBI. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HDIVRST : HDIV Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the HDIV controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRCRST : CRC Calculation Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQSEL : Trim Frequency Selection\nThis field indicates the target frequency of internal high speed RC oscillator 0 (HIRC0) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN(SYS_IRCTCTL0[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LOOPSEL : Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many clocks of reference clock (32.768 kHz, LXT).\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RETRYCNT : Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC0 trim value before the frequency of HIRC0 locked.\nOnce the HIRC0 locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC0 still doesn't lock, the auto trim operation will be disabled and FREQSEL(SYS_IRCTCTL0[1:0]) will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CESTOPEN : Clock Error Stop Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REFCKSEL : Reference Clock Selection
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFAILIEN : HIRC0 Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC0 trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL0[1:0]).\nIf this bit is high and TFAILIF(SYS_IRCTSTS0[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC0 trim value update limitation count was reached.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKEIEN : HIRC0 Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while HIRC0 clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_IRCTSTS0[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFAILIEN1 : HIRC1 Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC1 trim value update limitation count reached and HIRC1 frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL1[1:0]).\nIf this bit is high and TFAILIF(SYS_IRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC1 trim value update limitation count was reached.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKEIEN1 : HIRC1 Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while HIRC1 clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_IRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQLOCK : HIRC Frequency Lock Status\nThis bit indicates the HIRC0 frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFAILIF : Trim Failure Interrupt Status\nThis bit indicates that HIRC0 trim value update limitation count reached and the HIRC0 clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_iRCTCTL0[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_IRCTIEN0[1]) is high, an interrupt will be triggered to notify that HIRC0 trim value update limitation count was reached. Write 1 to clear this to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKERRIF : Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 22.1184 MHz internal high speed RC oscillator 0 (HIRC0) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL0[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL0[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_IRCTIEN0[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQLOCK1 : HIRC1 Frequency Lock Status\nThis bit indicates the HIRC1 frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFAILIF1 : HIRC1 Trim Failure Interrupt Status\nThis bit indicates that HIRC1 trim value update limitation count reached and the HIRC1 clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL1[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_IRCTIEN1[1]) is high, an interrupt will be triggered to notify that HIRC1 trim value update limitation count was reached. Write 1 to clear this to 0.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKERRIF1 : HIRC1 Clock Error Interrupt Status\nWhen 48 MHz internal high speed RC oscillator 1 (HIRC1) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL1[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL1[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_IRCTIEN1[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQSEL : Trim Frequency Selection\nThis field indicates the target frequency of internal high speed RC oscillator 1 (HIRC 1) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN(SYS_IRCTCTL1[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LOOPSEL : Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many clocks of reference clock.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RETRYCNT : Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC1 trim value before the frequency of HIRC1 locked.\nOnce the HIRC1 locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC1 still doesn't lock, the auto trim operation will be disabled and FREQSEL(SYS_IRCTCTL1[1:0]) will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CESTOPEN : Clock Error Stop Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REFCKSEL : Reference Clock Selection
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIORST : GPIO Controller Reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0RST : Timer0 Controller Reset
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1RST : Timer1 Controller Reset
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2RST : Timer2 Controller Reset
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR3RST : Timer3 Controller Reset
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C0RST : I2C0 Controller Reset
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C1RST : I2C1 Controller Reset
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0RST : SPI0 Controller Reset
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI1RST : SPI1 Controller Reset
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0RST : UART0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1RST : UART1 Controller Reset
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART2RST : UART2 Controller Reset
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0RST : PWM0 Controller Reset
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM1RST : PWM1 Controller Reset
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP01RST : ACMP01 Controller Reset
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCRST : ADC Controller Reset
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODEN : Modulation Function Enable Bit\nThis bit enables modulation funcion by modulating with PWM channel output and UART1_TXD.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODH : Modulation at Data High\nSelect modulation pulse(PWM) at UART1_TXD high or low
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODPWMSEL : PWM0 Channel Select for Modulation\nSelect the PWM0 channel to modulate with the UART1_TXD.\nNote: This bit is valid while MODEN (SYS_MODCTL[0]) is set to 1.
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.