ADC_ADDR0 (ADDR0)

ADC_ADDR4 (ADDR4)

ADC_ADPDMA (ADPDMA)

ADC_ADDR5 (ADDR5)

ADC_ADDR6 (ADDR6)

ADC_ADDR7 (ADDR7)

ADC_ADDR8 (ADDR8)

ADC_ADDR9 (ADDR9)

ADC_ADDR10 (ADDR10)

ADC_ADDR11 (ADDR11)

ADC_ADDR12 (ADDR12)

ADC_ADDR13 (ADDR13)

ADC_ADDR14 (ADDR14)

ADC_ADDR15 (ADDR15)

ADC_ADDR1 (ADDR1)

ADC_ADDR16 (ADDR16)

ADC_ADDR17 (ADDR17)

ADC_ADDR18 (ADDR18)

ADC_ADDR19 (ADDR19)

ADC_ADDR29 (ADDR29)

ADC_ADDR30 (ADDR30)

ADC_ADDR31 (ADDR31)

ADC_ADDR2 (ADDR2)

ADC_ADCR (ADCR)

ADC_ADCHER (ADCHER)

ADC_ADCMPR0 (ADCMPR0)

ADC_ADCMPR1 (ADCMPR1)

ADC_ADSR0 (ADSR0)

ADC_ADSR1 (ADSR1)

ADC_ADSR2 (ADSR2)

ADC_ADTDCR (ADTDCR)

ADC_ADDR3 (ADDR3)

RSLT : A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC.
bits : 0 - 15 (16 bit)
access : read-only

OVERRUN : Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register, OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

VALID : Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read.
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CURDAT : ADC PDMA Current Transfer Data Register (Read Only)\nWhen PDMA transferring, read this register can monitor current PDMA transfer data.\nCurrent PDMA transfer data could be the content of ADDR0 ~ ADDR19 and ADDR29 ~ ADDR31 registers.
bits : 0 - 17 (18 bit)
access : read-only

ADEN : A/D Converter Enable Bit\nNote: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADIE : A/D Interrupt Enable Bit\nA/D conversion end interrupt request is generated if ADIE bit is set to 1.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADMD : A/D Converter Operation Mode Control\nNote1: When changing the operation mode, software should clear ADST bit first.\nNote2: In Burst mode, the A/D result data is always at ADC Data Register 0.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGS : Hardware Trigger Source\nNote: Software should clear TRGEN bit and ADST bit to 0 before changing TRGS bits.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGCOND : External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and at least 4 PCLKs for edge trigger.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGEN : External Trigger Enable Bit\nEnable or disable triggering of A/D conversion by external STADC pin, PWM trigger and Timer trigger. If external trigger is enabled, the ADST bit can be set to 1 by the selected hardware trigger source.\nNote: The ADC external trigger function is only supported in Single-cycle Scan mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PTEN : PDMA Transfer Enable Bit\nWhen A/D conversion is completed, the converted data is loaded into ADDR0~19, ADDR29~ADDR31. Software can enable this bit to generate a PDMA data transfer request.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIFFEN : Differential Input Mode Control\nNote: In Differential Input mode, only the even number of the two corresponding channels needs to be enabled in ADCHER register. The conversion result will be placed to the corresponding data register of the enabled channel.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADST : A/D Conversion Start\nADST bit can be set to 1 from four sources: software, external pin STADC, PWM trigger and Timer trigger. ADST bit will be cleared to 0 by hardware automatically at the ends of Single mode and Single-cycle Scan mode. In Continuous Scan mode and Burst mode, A/D conversion is continuously performed until software writes 0 to this bit or chip is reset.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMPTSEL : ADC Internal Sampling Time Selection
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMOF : Differential Input Mode Output Format\nIf user enables differential input mode, the conversion result can be expressed with binary straight format (unsigned format) or 2's complement format (signed format).
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN : Analog Input Channel Enable Control\nSet ADCHER[19:0] bits to enable the corresponding analog input channel 19 ~ 0. If DIFFEN bit is set to 1, only the even number channel needs to be enabled.\nBesides, set ADCHER[29] to ADCHER[31] bits will enable internal channel for band-gap voltage, temperature sensor and battery power respectively. Other bits are reserved.\nNote1: If the internal channel for band-gap voltage (CHEN[29]) is active, the maximum sampling rate will be 300k SPS.\nNote2: If the internal channel for temperature sensor (CHEN[30]) is active, the maximum sampling rate will be 300k SPS.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPEN : Compare Enable Bit\nSet this bit to 1 to enable ADC controller to compare CMPD (ADCMPRx[27:16]) with specified channel conversion result when converted data is loaded into ADDR register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPIE : Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPFx bit will be asserted, in the meanwhile, if CMPIE bit is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCOND : Compare Condition\nNote: When the internal counter reaches to (CMPMATCNT +1), the CMPFx bit will be set.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCH : Compare Channel Selection
bits : 3 - 7 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPMATCNT : Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND bit, the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
bits : 8 - 11 (4 bit)
access : read-write

CMPWEN : Compare Window Mode Enable Bit\nNote: This bit is only presented in ADCMPR0 register.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPD : Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nNote: CMPD bits should be filled in unsigned format (straight binary format).
bits : 16 - 27 (12 bit)
access : read-write

ADF : A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion. Software can write 1 to clear this bit.\nADF bit is set to 1 at the following three conditions:\nWhen A/D conversion ends in Single mode.\nWhen A/D conversion ends on all specified channels in Single-cycle Scan mode and Continuous Scan mode.\nWhen more than or equal to 8 samples in FIFO in Burst mode.
bits : 0 - 0 (1 bit)
access : read-write

CMPF0 : Compare Flag 0\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR0 register then this bit is set to 1. This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPF1 : Compare Flag 1 When the A/D conversion result of the selected channel meets setting condition in ADCMPR1 register then this bit is set to 1 it is cleared by writing 1 to it
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSY : BUSY/IDLE (Read Only)\nThis bit is a mirror of ADST bit in ADCR register.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

VALIDF : Data Valid Flag (Read Only)\nIf any one of VALID (ADDRx[17]) is set, this flag will be set to 1.\nNote: When ADC is in burst mode and any conversion result is valid, this flag will be set to 1.
bits : 8 - 8 (1 bit)
access : read-only

OVERRUNF : Overrun Flag (Read Only)\nIf any one of OVERRUN (ADDRx[16]) is set, this flag will be set to 1.\nNote: When ADC is in burst mode and the FIFO is overrun, this flag will be set to 1.
bits : 16 - 16 (1 bit)
access : read-only

CHANNEL : Current Conversion Channel (Read Only)
bits : 27 - 31 (5 bit)
access : read-only

VALID : Data Valid Flag (Read Only) VALID[31:29, 19:0] are the mirror of the VALID bits in ADDR31[17] ~ ADDR29[17], ADDR19[17]~ ADDR0[17]. The other bits are reserved. Note: When ADC is in burst mode and any conversion result is valid, VALID[31:29, 19:0] will be set to 1.
bits : 0 - 31 (32 bit)
access : read-only

OVERRUN : Overrun Flag (Read Only)\nOVERRUN[31:29, 19:0] are the mirror of the OVERRUN bit in ADDR31[16] ~ADDR29[16], ADDR19[16] ~ ADDR0[16]. The other bits are reserved. \nNote: When ADC is in burst mode and the FIFO is overrun, OVERRUN[31:29, 19:0] will be set to 1.
bits : 0 - 31 (32 bit)
access : read-only

PTDT : PWM Trigger Delay Time\nSet this field will delay ADC start conversion time after PWM trigger.\nPWM trigger delay time is (4 * PTDT) * system clock
bits : 0 - 7 (8 bit)
access : read-write