CRC_CTL (CTL)

CRC_DAT (DAT)

CRC_SEED (SEED)

CRC_CHECKSUM (CHECKSUM)

CRCEN : CRC Generator Enable Bit\nSet this bit 1 to enable CRC generator for CRC operation.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHKSINIT : Checksum Initialization\nSet this bit will auto reolad SEED (CRC_SEED [31:0]) to CHECKSUM (CRC_CHECKSUM[31:0]) as CRC operation initial value.\nNote: This bit will be cleared automatically.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATREV : Write Data Bit Order Reverse Enable Bit\nThis bit is used to enable the bit order reverse function per byte for write data value DATA (CRC_DATA[31:0]).\nNote: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHKSREV : Checksum Bit Order Reverse Enable Bit\nThis bit is used to enable the bit order reverse function for checksum result CHECKSUM (CRC_CHECKSUM[31:0]).\nNote: If the checksum result is 0xDD7B0F2E, the bit order reverse result for CRC checksum is 0x74F0DEBB.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATFMT : Write Data 1's Complement Enable Bit\nThis bit is used to enable the 1's complement function for write data value DATA (CRC_DATA[31:0]).
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHKSFMT : Checksum 1's Complement Enable Bit\nThis bit is used to enable the 1's complement function for checksum result CHECKSUM (CRC_CHECKSUM[31:0]).
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATLEN : CPU Write Data Length This field indicates the valid write data length of DATA (CRC_DAT[31:0]). Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRCMODE : CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode.
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATA : CRC Write Data Bits User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation. Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].
bits : 0 - 31 (32 bit)
access : read-write

SEED : CRC Seed Value\nThis field indicates the CRC seed value.\nNote1: This SEED value will be loaded to checksum initial value CHECKSUM (CRC_CHECKSUM[31:0]) after set CHKSINIT (CRC_CTL[1]) to 1.\nNote2: The valid bits of CRC_SEED[31:0] is correlated to CRCMODE (CRC_CTL[31:30]).
bits : 0 - 31 (32 bit)
access : read-write

CHECKSUM : CRC Checksum Results\nThis field indicates the CRC checksum result.\nNote: The valid bits of CRC_CHECKSUM[31:0] is correlated to CRCMODE (CRC_CTL[31:30]).
bits : 0 - 31 (32 bit)
access : read-only