Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
External Bus Interface Bank0 Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : EBI Enable Bit\nThis bit is the functional enable bit for EBI.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI function Disabled
#1 : 1
EBI function Enabled
End of enumeration elements list.
DW16 : EBI Data Width 16-bit Select\nThis bit defines if the EBI data width is 8-bit or 16-bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI data width is 8-bit
#1 : 1
EBI data width is 16-bit
End of enumeration elements list.
CSPOLINV : Chip Select Pin Polar Inverse
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip select pin (EBI_nCSx) is active low
#1 : 1
Chip select pin (EBI_nCSx) is active high
End of enumeration elements list.
CACCESS : Continuous Data Access Mode\nWhen continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Continuous data access mode Disabled
#1 : 1
Continuous data access mode Enabled
End of enumeration elements list.
MCLKDIV : External Output Clock Divider\nThe frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
HCLK/1
#001 : 1
HCLK/2
#010 : 2
HCLK/4
#011 : 3
HCLK/8
#100 : 4
HCLK/16
#101 : 5
HCLK/32
#110 : 6
HCLK/64
#111 : 7
HCLK/128
End of enumeration elements list.
TALE : Extend Time of ALE\nThe EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.\nNote: This field only available in EBI_CTL0 register
bits : 16 - 18 (3 bit)
access : read-write
External Bus Interface Bank1 Control Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
External Bus Interface Bank1 Timing Control Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
External Bus Interface Bank0 Timing Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TACC : EBI Data Access Time\nTACC define data access time (tACC).
bits : 3 - 7 (5 bit)
access : read-write
TAHD : EBI Data Access Hold Time\nTAHD define data access hold time (tAHD).
bits : 8 - 10 (3 bit)
access : read-write
W2X : Idle Cycle After Write\nThis field defines the number of W2X idle cycle.
bits : 12 - 15 (4 bit)
access : read-write
RAHDOFF : Access Hold Time Disable Control When Read
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data Access Hold Time (tAHD) during EBI reading Enabled
#1 : 1
Data Access Hold Time (tAHD) during EBI reading Disabled
End of enumeration elements list.
WAHDOFF : Access Hold Time Disable Control When Write
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data Access Hold Time (tAHD) during EBI writing Enabled
#1 : 1
Data Access Hold Time (tAHD) during EBI writing Disabled
End of enumeration elements list.
R2R : Idle Cycle Between Read-to-read\nThis field defines the number of R2R idle cycle.
bits : 24 - 27 (4 bit)
access : read-write
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