\n

HDIV

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

Registers

HDIV_DIVIDEND (DIVIDEND)

HDIV_DIVSTS (DIVSTS)

HDIV_DIVISOR (DIVISOR)

HDIV_DIVQUO (DIVQUO)

HDIV_DIVREM (DIVREM)


HDIV_DIVIDEND (DIVIDEND)

Dividend Source Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HDIV_DIVIDEND HDIV_DIVIDEND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVIDEND

DIVIDEND : Dividend Source\nThis register is given the dividend of divider before calculation starting.
bits : 0 - 31 (32 bit)
access : read-write


HDIV_DIVSTS (DIVSTS)

Divider Status Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HDIV_DIVSTS HDIV_DIVSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FINISH DIV0

FINISH : Division Finish Flag\nThe flag will become low when the divider is in calculation. The flag will go back to high once the calculation finished.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Under Calculation

#1 : 1

Calculation finished

End of enumeration elements list.

DIV0 : Divisor Zero Warning\nNote: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written. This register is read only.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

The divisor is not 0

#1 : 1

The divisor is 0

End of enumeration elements list.


HDIV_DIVISOR (DIVISOR)

Divisor Source Resister
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HDIV_DIVISOR HDIV_DIVISOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVISOR

DIVISOR : Divisor Source\nThis register is given the divisor of divider before calculation starts.\nNote: When this register is written, hardware divider will start calculate.
bits : 0 - 15 (16 bit)
access : read-write


HDIV_DIVQUO (DIVQUO)

Quotient Result Resister
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HDIV_DIVQUO HDIV_DIVQUO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QUOTIENT

QUOTIENT : Quotient Result\nThis register holds the quotient result of divider after calculation complete.
bits : 0 - 31 (32 bit)
access : read-write


HDIV_DIVREM (DIVREM)

Remainder Result Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HDIV_DIVREM HDIV_DIVREM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REMAINDER

REMAINDER : Remainder Result\nThe remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]), which holds the remainder result of divider after calculation complete. The remainder of hardware divider with sign extension (REMAINDER[31:16]) to 32-bit integer.\nThis register holds the remainder result of divider after calculation complete.
bits : 0 - 31 (32 bit)
access : read-write



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