\n
address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3C Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
I2C Control Register 0
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AA : Assert Acknowledge Control
bits : 2 - 2 (1 bit)
access : read-write
SI : I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware. If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
bits : 3 - 3 (1 bit)
access : read-write
STO : I2C STOP Control\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically.
bits : 4 - 4 (1 bit)
access : read-write
STA : I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
bits : 5 - 5 (1 bit)
access : read-write
I2CEN : I2C Controller Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C serial function Disabled
#1 : 1
I2C serial function Enabled
End of enumeration elements list.
INTEN : Enable Interrupt
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C interrupt Disabled
#1 : 1
I2C interrupt Enabled
End of enumeration elements list.
I2C Clock Divided Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDER : I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4.
bits : 0 - 7 (8 bit)
access : read-write
I2C Time-out Control Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOIF : Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
TOCDIV4 : Time-out Counter Input Clock Divided by 4\nWhen Enabled, The time-out period is extend 4 times.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time-out period is extend 4 times Disabled
#1 : 1
Time-out period is extend 4 times Enabled
End of enumeration elements list.
TOCEN : Time-out Counter Enable Bit\nWhen Enabled, the 14-bit time-out counter will start counting when SI is clear. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time-out counter Disabled
#1 : 1
Time-out counter Enabled
End of enumeration elements list.
I2C Slave Address Register1
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C Slave Address Register2
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C Slave Address Register3
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C Slave Address Mask Register0
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRMSK : I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
bits : 1 - 7 (7 bit)
access : read-write
Enumeration:
0 : 0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
1 : 1
Mask Enabled (the received corresponding address bit is don't care.)
End of enumeration elements list.
I2C Slave Address Mask Register1
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C Slave Address Mask Register2
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C Slave Address Mask Register3
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2C Wake-up Control Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKEN : I2C Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C wake-up function Disabled
#1 : 1
I2C wake-up function Enabled
End of enumeration elements list.
NHDBUSEN : I2C No Hold BUS Enable Bit\nNote: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C don't hold bus after wake-up disable
#1 : 1
I2C don't hold bus after wake-up enable
End of enumeration elements list.
I2C Slave Address Register0
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GC : General Call Function
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
General Call Function Disabled
#1 : 1
General Call Function Enabled
End of enumeration elements list.
ADDR : I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
bits : 1 - 7 (7 bit)
access : read-write
I2C Wake-up Status Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKIF : I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
WKAKDONE : Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF. Software can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The ACK bit cycle of address match frame isn't done
#1 : 1
The ACK bit cycle of address match frame is done in power-down
End of enumeration elements list.
WRSTSWK : Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write command be record on the address match wakeup frame
#1 : 1
Read command be record on the address match wakeup frame
End of enumeration elements list.
I2C Control Register 1
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPDMAEN : PDMA Transmit Channel Available
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit PDMA function Disabled
#1 : 1
Transmit PDMA function Enabled
End of enumeration elements list.
RXPDMAEN : PDMA Receive Channel Available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive PDMA function Disabled
#1 : 1
Receive PDMA function Enabled
End of enumeration elements list.
PDMARST : PDMA Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the PDMA control logic. This bit will be cleared to 0 automatically
End of enumeration elements list.
OVRIEN : I2C over Run Interrupt Control Bit\nSetting OVRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is over run event in received buffer.
bits : 3 - 3 (1 bit)
access : read-write
UDRIEN : I2C Under Run Interrupt Control Bit\nSetting UDRIEN to logic 1 will send a interrupt to system when the TWOBUFEN bit is enabled and there is under run event happened in transmitted buffer.
bits : 4 - 4 (1 bit)
access : read-write
TWOBUFEN : Two-level Buffer Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Two-level buffer Disabled
#1 : 1
Two-level buffer Enabled
End of enumeration elements list.
TWOBUFRST : Two-level Buffer Reset
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the related counters, two-level buffer state machine, and the content of data buffer
End of enumeration elements list.
NSTRETCH : No Stretch on the I2C Bus
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C SCL bus is stretched by hardware if the SI is not cleared in master mode
#1 : 1
I2C SCL bus is not stretched by hardware if the SI is not cleared in master mode
End of enumeration elements list.
PDMASTR : PDMA Stretch Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C sends STOP automatically after PDMA transfer done. (only master TX)
#1 : 1
I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared. (only master TX)
End of enumeration elements list.
I2C Status Register 1
address_offset : 0x48 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FULL : Two-level Buffer Full\nThis bit is set when POINTER is equal to 2
bits : 4 - 4 (1 bit)
access : read-only
EMPTY : Two-level Buffer Empty\nThis bit is set when POINTER is equal to 0.
bits : 5 - 5 (1 bit)
access : read-only
OVR : I2C over Run Status Bit
bits : 6 - 6 (1 bit)
access : read-only
UDR : I2C Under Run Status Bit
bits : 7 - 7 (1 bit)
access : read-only
ONBUSY : on Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected.
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
The bus is IDLE (both SCLK and SDA High)
#1 : 1
The bus is busy
End of enumeration elements list.
I2C Timing Configure Control Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STCTL : Setup Time Configure Control Register \nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs.
bits : 0 - 5 (6 bit)
access : read-write
HTCTL : Hold Time Configure Control Register\nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
bits : 6 - 11 (6 bit)
access : read-write
I2C Data Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAT : I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
bits : 0 - 7 (8 bit)
access : read-write
I2C Status Register 0
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATUS : I2C Status
bits : 0 - 7 (8 bit)
access : read-only
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