PDMA_DSCT0_CTL (DSCT0_CTL)

PDMA_DSCT1_CTL (DSCT1_CTL)

PDMA_DSCT1_SA (DSCT1_SA)

PDMA_DSCT1_DA (DSCT1_DA)

PDMA_DSCT1_FIRST (DSCT1_FIRST)

PDMA_DSCT2_CTL (DSCT2_CTL)

PDMA_DSCT2_SA (DSCT2_SA)

PDMA_DSCT2_DA (DSCT2_DA)

PDMA_DSCT2_FIRST (DSCT2_FIRST)

PDMA_DSCT3_CTL (DSCT3_CTL)

PDMA_DSCT3_SA (DSCT3_SA)

PDMA_DSCT3_DA (DSCT3_DA)

PDMA_DSCT3_FIRST (DSCT3_FIRST)

PDMA_DSCT0_SA (DSCT0_SA)

PDMA_DSCT4_CTL (DSCT4_CTL)

PDMA_CHCTL (CHCTL)

PDMA_PAUSE (PAUSE)

PDMA_SWREQ (SWREQ)

PDMA_TRGSTS (TRGSTS)

PDMA_PRISET (PRISET)

PDMA_PRICLR (PRICLR)

PDMA_INTEN (INTEN)

PDMA_INTSTS (INTSTS)

PDMA_ABTSTS (ABTSTS)

PDMA_TDSTS (TDSTS)

PDMA_SCATSTS (SCATSTS)

PDMA_TACTSTS (TACTSTS)

PDMA_TOUTPSC (TOUTPSC)

PDMA_TOUTEN (TOUTEN)

PDMA_TOUTIEN (TOUTIEN)

PDMA_SCATBA (SCATBA)

PDMA_DSCT4_SA (DSCT4_SA)

PDMA_TOC0_1 (TOC0_1)

PDMA_RESET (RESET)

PDMA_DSCT4_DA (DSCT4_DA)

PDMA_REQSEL0_3 (REQSEL0_3)

PDMA_REQSEL4 (REQSEL4)

PDMA_DSCT4_FIRST (DSCT4_FIRST)

PDMA_CURSCAT0 (CURSCAT0)

PDMA_CURSCAT1 (CURSCAT1)

PDMA_CURSCAT2 (CURSCAT2)

PDMA_CURSCAT3 (CURSCAT3)

PDMA_CURSCAT4 (CURSCAT4)

PDMA_DSCT0_DA (DSCT0_DA)

PDMA_DSCT0_FIRST (DSCT0_FIRST)

OPMODE : PDMA Operation Mode Selection\nNote: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXTYPE : Transfer Type
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BURSIZE : Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type.
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TBINTDIS : Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt.\nNote: If this bit set to '1', the TEMPTYF will not be set.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SAINC : Source Address Increment\nThis Field Is Used To Set The Source Address Increment Size.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DAINC : Destination Address Increment\nThis field is used to set the destination address increment size.
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXWIDTH : Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection. For example, if source address is 0x2000_0202, but TXWIDTH is word transfer, the source address is not word alignment. The source address is aligned when TXWIDTH is byte or half-word transfer.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXCNT : Transfer Count The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field. Note: When PDMA finish each transfer data, this field will be decrease immediately.
bits : 16 - 29 (14 bit)
access : read-write

SA : PDMA Transfer Source Address Register\nThis field indicates a 32-bit source address of PDMA controller.
bits : 0 - 31 (32 bit)
access : read-write

CHEN0 : PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN1 : PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN2 : PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN3 : PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN4 : PDMA Channel N Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PAUSE0 : PDMA Channel N Transfer Pause Control Register (Write Only)
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PAUSE1 : PDMA Channel N Transfer Pause Control Register (Write Only)
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PAUSE2 : PDMA Channel N Transfer Pause Control Register (Write Only)
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PAUSE3 : PDMA Channel N Transfer Pause Control Register (Write Only)
bits : 3 - 3 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PAUSE4 : PDMA Channel N Transfer Pause Control Register (Write Only)
bits : 4 - 4 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ0 : PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ1 : PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ2 : PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ3 : PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 3 - 3 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ4 : PDMA Channel N Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 4 - 4 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

REQSTS0 : PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS1 : PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS2 : PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS3 : PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS4 : PDMA Channel N Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_RESET register respectively, this bit will be cleared automatically after finishing current transfer.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

FPRISET0 : PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET1 : PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET2 : PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET3 : PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET4 : PDMA Channel N Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority, the higher number of channels have higher priority.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRICLR0 : PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR1 : PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR2 : PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR3 : PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 3 - 3 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR4 : PDMA Channel N Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 4 - 4 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

INTEN0 : PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN1 : PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN2 : PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN3 : PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN4 : PDMA Channel N Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF : PDMA Read/Write Target Abort Interrupt Flag (Read Only) This bit indicates that PDMA has target abort error Software can read PDMA_ABTSTS register to find which channel has target abort error.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TDIF : Transfer Done Interrupt Flag (Read Only) This bit indicates that PDMA controller has finished transmission User can read PDMA_TDSTS register to indicate which channel finished transfer.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TEIF : Table Empty Interrupt Flag (Read Only)\nThis bit indicates PDMA channel scatter-gather table is empty. User can read PDMA_SCATSTS register to indicate which channel scatter-gather table is empty.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQTOF0 : PDMA Channel N Request Time-out Flag\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQTOF1 : PDMA Channel N Request Time-out Flag\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF0 : PDMA Channel N Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF1 : PDMA Channel N Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF2 : PDMA Channel N Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF3 : PDMA Channel N Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF4 : PDMA Channel N Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF0 : PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF1 : PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF2 : PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF3 : PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF4 : PDMA Channel N Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEMPTYF0 : Table Empty Flag Register\nT This bit indicates which PDMA channel table is empty when channel have a request , no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEMPTYF1 : Table Empty Flag Register\nT This bit indicates which PDMA channel table is empty when channel have a request , no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEMPTYF2 : Table Empty Flag Register\nT This bit indicates which PDMA channel table is empty when channel have a request , no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEMPTYF3 : Table Empty Flag Register\nT This bit indicates which PDMA channel table is empty when channel have a request , no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEMPTYF4 : Table Empty Flag Register\nT This bit indicates which PDMA channel table is empty when channel have a request , no matter request from software or peripheral, but operation mode of channel descriptor table is idle state, or channel has finished current transfer and next table operation mode is idle state for PDMA Scatter-Gather mode. User can write 1 to clear these bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXACTF0 : PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXACTF1 : PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXACTF2 : PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXACTF3 : PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXACTF4 : PDMA Channel N Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TOUTPSC0 : PDMA Channel 0 Time-out Clock Source Prescaler Bits
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOUTPSC1 : PDMA Channel 1 Time-out Clock Source Prescaler Bits
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOUTEN0 : PDMA Channel N Time-out Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOUTEN1 : PDMA Channel N Time-out Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOUTIEN0 : PDMA Channel N Time-out Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOUTIEN1 : PDMA Channel N Time-out Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCATBA : PDMA Scatter-gather Descriptor Table Address Register\nIn Scatter-Gather mode, this is the base address for calculating the next link - list address. The next link address equation is \nNote: Only useful in Scatter-Gather mode.
bits : 16 - 31 (16 bit)
access : read-write

TOC0 : Time-out Counter for Channel 0\nThis controls the period of time-out function for channel 0. The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock.
bits : 0 - 15 (16 bit)
access : read-write

TOC1 : Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1. The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[5:3]) clock. The example of time-out period can refer TOC0 bit description.
bits : 16 - 31 (16 bit)
access : read-write

RESET0 : PDMA Channel N Reset Control Register \nNote: This bit will be cleared automatically after finishing reset process.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESET1 : PDMA Channel N Reset Control Register \nNote: This bit will be cleared automatically after finishing reset process.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESET2 : PDMA Channel N Reset Control Register \nNote: This bit will be cleared automatically after finishing reset process.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESET3 : PDMA Channel N Reset Control Register \nNote: This bit will be cleared automatically after finishing reset process.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESET4 : PDMA Channel N Reset Control Register \nNote: This bit will be cleared automatically after finishing reset process.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQSRC0 : Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.\nNote1: A request source can't assign to two channels at the same time.\nNote2: This field is useless when transfer between memory and memory.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQSRC1 : Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 13 (6 bit)
access : read-write

REQSRC2 : Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 21 (6 bit)
access : read-write

REQSRC3 : Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 29 (6 bit)
access : read-write

REQSRC4 : Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0
bits : 0 - 5 (6 bit)
access : read-write

CURADDR : PDMA Current Description Address Register (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.
bits : 0 - 31 (32 bit)
access : read-only