Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x70 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
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size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
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mem_usage : registers
protection : not protected
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size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
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size : 0x4C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x90 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
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size : 0x44 byte (0x0)
mem_usage : registers
protection : not protected
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mem_usage : registers
protection : not protected
address_offset : 0x110 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x304 Bytes (0x0)
size : 0x4C byte (0x0)
mem_usage : registers
protection : not protected
PWM Control Register 0
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRLD0 : Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a period.
bits : 0 - 0 (1 bit)
access : read-write
CTRLD1 : Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a period.
bits : 1 - 1 (1 bit)
access : read-write
CTRLD2 : Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a period.
bits : 2 - 2 (1 bit)
access : read-write
CTRLD3 : Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a period.
bits : 3 - 3 (1 bit)
access : read-write
CTRLD4 : Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a period.
bits : 4 - 4 (1 bit)
access : read-write
CTRLD5 : Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the center point of a period.
bits : 5 - 5 (1 bit)
access : read-write
WINLDEN0 : Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit
#1 : 1
PERIODn register will load to PBUFn and CMPDATn registers will load to CMPBUFn register at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register, and cleared by hardware after load success
End of enumeration elements list.
WINLDEN1 : Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit
#1 : 1
PERIODn register will load to PBUFn and CMPDATn registers will load to CMPBUFn register at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register, and cleared by hardware after load success
End of enumeration elements list.
WINLDEN2 : Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit
#1 : 1
PERIODn register will load to PBUFn and CMPDATn registers will load to CMPBUFn register at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register, and cleared by hardware after load success
End of enumeration elements list.
WINLDEN3 : Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit
#1 : 1
PERIODn register will load to PBUFn and CMPDATn registers will load to CMPBUFn register at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register, and cleared by hardware after load success
End of enumeration elements list.
WINLDEN4 : Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit
#1 : 1
PERIODn register will load to PBUFn and CMPDATn registers will load to CMPBUFn register at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register, and cleared by hardware after load success
End of enumeration elements list.
WINLDEN5 : Window Load Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit
#1 : 1
PERIODn register will load to PBUFn and CMPDATn registers will load to CMPBUFn register at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register, and cleared by hardware after load success
End of enumeration elements list.
IMMLDEN0 : Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled, WINLDENn bit and CTRLDn bits will be invalid.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit
#1 : 1
PERIODn/CMPDATn registers will load to PBUFn and CMPBUFn register immediately when software update PERIODn/CMPDATn register
End of enumeration elements list.
IMMLDEN1 : Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled, WINLDENn bit and CTRLDn bits will be invalid.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit
#1 : 1
PERIODn/CMPDATn registers will load to PBUFn and CMPBUFn register immediately when software update PERIODn/CMPDATn register
End of enumeration elements list.
IMMLDEN2 : Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled, WINLDENn bit and CTRLDn bits will be invalid.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit
#1 : 1
PERIODn/CMPDATn registers will load to PBUFn and CMPBUFn register immediately when software update PERIODn/CMPDATn register
End of enumeration elements list.
IMMLDEN3 : Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled, WINLDENn bit and CTRLDn bits will be invalid.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit
#1 : 1
PERIODn/CMPDATn registers will load to PBUFn and CMPBUFn register immediately when software update PERIODn/CMPDATn register
End of enumeration elements list.
IMMLDEN4 : Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled, WINLDENn bit and CTRLDn bits will be invalid.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit
#1 : 1
PERIODn/CMPDATn registers will load to PBUFn and CMPBUFn register immediately when software update PERIODn/CMPDATn register
End of enumeration elements list.
IMMLDEN5 : Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn bit is enabled, WINLDENn bit and CTRLDn bits will be invalid.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIODn register will load to PBUFn register at the end point of each period. CMPDATn register will load to CMPBUFn register at the end point or center point of each period by setting CTRLDn bit
#1 : 1
PERIODn/CMPDATn registers will load to PBUFn and CMPBUFn register immediately when software update PERIODn/CMPDATn register
End of enumeration elements list.
GROUPEN : Group Function Enable Bit
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
The output waveform of each PWM channel are independent
#1 : 1
Unify the PWMx_CH2 and PWMx_CH4 to output the same waveform as PWMx_CH0 and unify the PWMx_CH3 and PWMx_CH5 to output the same waveform as PWMx_CH1
End of enumeration elements list.
DBGHALT : ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode counter halt Disabled
#1 : 1
ICE debug mode counter halt Enabled
End of enumeration elements list.
DBGTRIOFF : ICE Debug Mode Acknowledge Disable (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode acknowledgement effects PWM output
#1 : 1
ICE debug mode acknowledgement Disabled
End of enumeration elements list.
PWM Clock Source Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECLKSRC0 : PWMx_CH0/1 External Clock Source Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
PWMx_CLK, x denotes 0 or 1
#001 : 1
TIMER0 time-out event
#010 : 2
TIMER1 time-out event
#011 : 3
TIMER2 time-out event
#100 : 4
TIMER3 time-out event
End of enumeration elements list.
ECLKSRC2 : PWMx_CH2/3 External Clock Source Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
PWMx_CLK, x denotes 0 or 1
#001 : 1
TIMER0 time-out event
#010 : 2
TIMER1 time-out event
#011 : 3
TIMER2 time-out event
#100 : 4
TIMER3 time-out event
End of enumeration elements list.
ECLKSRC4 : PWMx_CH4/5 External Clock Source Select
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
PWMx_CLK, x denotes 0 or 1
#001 : 1
TIMER0 time-out event
#010 : 2
TIMER1 time-out event
#011 : 3
TIMER2 time-out event
#100 : 4
TIMER3 time-out event
End of enumeration elements list.
PWM Free Trigger Compare Register 0/1
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTCMP : PWM Free Trigger Compare Register
bits : 0 - 15 (16 bit)
access : read-write
PWM Free Trigger Compare Register 2/3
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Free Trigger Compare Register 4/5
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Synchronous Start Control Register
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSEN0 : PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM channel n.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM synchronous start function Disabled
#1 : 1
PWM synchronous start function Enabled
End of enumeration elements list.
SSEN1 : PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM channel n.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM synchronous start function Disabled
#1 : 1
PWM synchronous start function Enabled
End of enumeration elements list.
SSEN2 : PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM channel n.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM synchronous start function Disabled
#1 : 1
PWM synchronous start function Enabled
End of enumeration elements list.
SSEN3 : PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM channel n.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM synchronous start function Disabled
#1 : 1
PWM synchronous start function Enabled
End of enumeration elements list.
SSEN4 : PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM channel n.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM synchronous start function Disabled
#1 : 1
PWM synchronous start function Enabled
End of enumeration elements list.
SSEN5 : PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM channel n.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM synchronous start function Disabled
#1 : 1
PWM synchronous start function Enabled
End of enumeration elements list.
SSRC : PWM Synchronous Start Source Select Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Synchronous start source come from PWM0
#1 : 1
Synchronous start source come from PWM1
End of enumeration elements list.
PWM Synchronous Start Trigger Register
address_offset : 0x114 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CNTSEN : PWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected PWM channels (PWMx_CHn) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled.
bits : 0 - 0 (1 bit)
access : write-only
PWM Leading Edge Blanking Control Register
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEBEN : PWM Leading Edge Blanking Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Leading Edge Blanking Disabled
#1 : 1
PWM Leading Edge Blanking Enabled
End of enumeration elements list.
SRCEN0 : PWM Leading Edge Blanking Source From PWMx_CH0 Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Leading Edge Blanking Source from PWMx_CH0 Disabled
#1 : 1
PWM Leading Edge Blanking Source from PWMx_CH0 Enabled
End of enumeration elements list.
SRCEN2 : PWM Leading Edge Blanking Source From PWMx_CH2 Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Leading Edge Blanking Source from PWMx_CH2 Disabled
#1 : 1
PWM Leading Edge Blanking Source from PWMx_CH2 Enabled
End of enumeration elements list.
SRCEN4 : PWM Leading Edge Blanking Source From PWMx_CH4 Enable Bit
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Leading Edge Blanking Source from PWMx_CH4 Disabled
#1 : 1
PWM Leading Edge Blanking Source from PWMx_CH4 Enabled
End of enumeration elements list.
TRGTYPE : PWM Leading Edge Blanking Trigger Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
When detect leading edge blanking source rising edge, blanking counter start counting
#01 : 1
When detect leading edge blanking source falling edge, blanking counter start counting
#10 : 2
When detect leading edge blanking source rising or falling edge, blanking counter start counting
#11 : 3
Reserved.
End of enumeration elements list.
PWM Leading Edge Blanking Counter Register
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEBCNT : PWM Leading Edge Blanking Counter\nThis counter value decides leading edge blanking window size.
bits : 0 - 8 (9 bit)
access : read-write
PWM Status Register
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTMAXF0 : Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
indicates the time-base counter(PWM_CNTn[15:0]) never reached its maximum value 0xFFFF
#1 : 1
indicates the time-base counter(PWM_CNTn[15:0]) reached its maximum value, software can write 1 to clear this bit
End of enumeration elements list.
CNTMAXF1 : Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
indicates the time-base counter(PWM_CNTn[15:0]) never reached its maximum value 0xFFFF
#1 : 1
indicates the time-base counter(PWM_CNTn[15:0]) reached its maximum value, software can write 1 to clear this bit
End of enumeration elements list.
CNTMAXF2 : Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
indicates the time-base counter(PWM_CNTn[15:0]) never reached its maximum value 0xFFFF
#1 : 1
indicates the time-base counter(PWM_CNTn[15:0]) reached its maximum value, software can write 1 to clear this bit
End of enumeration elements list.
CNTMAXF3 : Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
indicates the time-base counter(PWM_CNTn[15:0]) never reached its maximum value 0xFFFF
#1 : 1
indicates the time-base counter(PWM_CNTn[15:0]) reached its maximum value, software can write 1 to clear this bit
End of enumeration elements list.
CNTMAXF4 : Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
indicates the time-base counter(PWM_CNTn[15:0]) never reached its maximum value 0xFFFF
#1 : 1
indicates the time-base counter(PWM_CNTn[15:0]) reached its maximum value, software can write 1 to clear this bit
End of enumeration elements list.
CNTMAXF5 : Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
indicates the time-base counter(PWM_CNTn[15:0]) never reached its maximum value 0xFFFF
#1 : 1
indicates the time-base counter(PWM_CNTn[15:0]) reached its maximum value, software can write 1 to clear this bit
End of enumeration elements list.
SYNCINF0 : Input Synchronization Latched Flag\nEach bit n controls the corresponding PWM channel n.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no SYNC_IN event has occurred
#1 : 1
Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit
End of enumeration elements list.
SYNCINF2 : Input Synchronization Latched Flag\nEach bit n controls the corresponding PWM channel n.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no SYNC_IN event has occurred
#1 : 1
Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit
End of enumeration elements list.
SYNCINF4 : Input Synchronization Latched Flag\nEach bit n controls the corresponding PWM channel n.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no SYNC_IN event has occurred
#1 : 1
Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit
End of enumeration elements list.
ADCTRGF0 : ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no ADC start of conversion trigger event has occurred
#1 : 1
Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit
End of enumeration elements list.
ADCTRGF1 : ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no ADC start of conversion trigger event has occurred
#1 : 1
Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit
End of enumeration elements list.
ADCTRGF2 : ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no ADC start of conversion trigger event has occurred
#1 : 1
Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit
End of enumeration elements list.
ADCTRGF3 : ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no ADC start of conversion trigger event has occurred
#1 : 1
Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit
End of enumeration elements list.
ADCTRGF4 : ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no ADC start of conversion trigger event has occurred
#1 : 1
Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit
End of enumeration elements list.
ADCTRGF5 : ADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no ADC start of conversion trigger event has occurred
#1 : 1
Indicates an ADC start of conversion trigger event has occurred, software can write 1 to clear this bit
End of enumeration elements list.
PWM Clock Pre-scale Register 0/1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKPSC : PWM Counter Clock Pre-scale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1).
bits : 0 - 11 (12 bit)
access : read-write
PWM Clock Pre-scale Register 2/3
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Clock Pre-scale Register 4/5
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTEN0 : PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Counter and clock prescaler Stop Running
#1 : 1
PWM Counter and clock prescaler Start Running
End of enumeration elements list.
CNTEN1 : PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Counter and clock prescaler Stop Running
#1 : 1
PWM Counter and clock prescaler Start Running
End of enumeration elements list.
CNTEN2 : PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Counter and clock prescaler Stop Running
#1 : 1
PWM Counter and clock prescaler Start Running
End of enumeration elements list.
CNTEN3 : PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Counter and clock prescaler Stop Running
#1 : 1
PWM Counter and clock prescaler Start Running
End of enumeration elements list.
CNTEN4 : PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Counter and clock prescaler Stop Running
#1 : 1
PWM Counter and clock prescaler Start Running
End of enumeration elements list.
CNTEN5 : PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Counter and clock prescaler Stop Running
#1 : 1
PWM Counter and clock prescaler Start Running
End of enumeration elements list.
PWM Capture Input Enable Register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPINEN0 : Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#1 : 1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN1 : Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#1 : 1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN2 : Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#1 : 1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN3 : Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#1 : 1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN4 : Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#1 : 1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN5 : Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#1 : 1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
PWM Capture Control Register
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPEN0 : Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT registers will not be updated
#1 : 1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers
End of enumeration elements list.
CAPEN1 : Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT registers will not be updated
#1 : 1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers
End of enumeration elements list.
CAPEN2 : Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT registers will not be updated
#1 : 1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers
End of enumeration elements list.
CAPEN3 : Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT registers will not be updated
#1 : 1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers
End of enumeration elements list.
CAPEN4 : Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT registers will not be updated
#1 : 1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers
End of enumeration elements list.
CAPEN5 : Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT registers will not be updated
#1 : 1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers
End of enumeration elements list.
CAPINV0 : Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV1 : Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV2 : Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV3 : Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV4 : Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV5 : Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
RCRLDEN0 : Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN1 : Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN2 : Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN3 : Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN4 : Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN5 : Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
FCRLDEN0 : Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN1 : Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN2 : Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN3 : Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN4 : Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN5 : Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
PWM Capture Status Register
address_offset : 0x208 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRLIFOV0 : Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn bit.
bits : 0 - 0 (1 bit)
access : read-only
CRLIFOV1 : Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn bit.
bits : 1 - 1 (1 bit)
access : read-only
CRLIFOV2 : Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn bit.
bits : 2 - 2 (1 bit)
access : read-only
CRLIFOV3 : Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn bit.
bits : 3 - 3 (1 bit)
access : read-only
CRLIFOV4 : Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn bit.
bits : 4 - 4 (1 bit)
access : read-only
CRLIFOV5 : Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(PWM_CAPIF[5:0]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn bit.
bits : 5 - 5 (1 bit)
access : read-only
CFLIFOV0 : Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn bit.
bits : 8 - 8 (1 bit)
access : read-only
CFLIFOV1 : Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn bit.
bits : 9 - 9 (1 bit)
access : read-only
CFLIFOV2 : Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn bit.
bits : 10 - 10 (1 bit)
access : read-only
CFLIFOV3 : Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn bit.
bits : 11 - 11 (1 bit)
access : read-only
CFLIFOV4 : Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn bit.
bits : 12 - 12 (1 bit)
access : read-only
CFLIFOV5 : Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(PWM_CAPIF[13:8]) bit is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn bit.
bits : 13 - 13 (1 bit)
access : read-only
PWM Rising Capture Data Register 0
address_offset : 0x20C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RCAPDAT : PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the PWM counter value will be saved in this register.
bits : 0 - 15 (16 bit)
access : read-only
PWM Falling Capture Data Register 0
address_offset : 0x210 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FCAPDAT : PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the PWM counter value will be saved in this register.
bits : 0 - 15 (16 bit)
access : read-only
PWM Rising Capture Data Register 1
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Falling Capture Data Register 1
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Rising Capture Data Register 2
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Falling Capture Data Register 2
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Rising Capture Data Register 3
address_offset : 0x224 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Falling Capture Data Register 3
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Rising Capture Data Register 4
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Falling Capture Data Register 4
address_offset : 0x230 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Rising Capture Data Register 5
address_offset : 0x234 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Falling Capture Data Register 5
address_offset : 0x238 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM PDMA Control Register
address_offset : 0x23C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN0_1 : Channel 0/1 PDMA Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 0/1 PDMA function Disabled
#1 : 1
Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory
End of enumeration elements list.
CAPMOD0_1 : Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved.
#01 : 1
PWM_RCAPDAT0/1 register
#10 : 2
PWM_FCAPDAT0/1 register
#11 : 3
Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1 registers
End of enumeration elements list.
CAPORD0_1 : Capture Channel 0/1 Rising/Falling Order \nSet this bit to determine whether the PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 register is the first captured data transferred to memory through PDMA when CAPMOD0_1 bits are set to 0x3.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_FCAPDAT0/1 register is the first captured data to memory
#1 : 1
PWM_RCAPDAT0/1 register is the first captured data to memory
End of enumeration elements list.
CHSEL0_1 : Select Channel 0/1 to Do PDMA Transfer
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel0
#1 : 1
Channel1
End of enumeration elements list.
CHEN2_3 : Channel 2/3 PDMA Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 2/3 PDMA function Disabled
#1 : 1
Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory
End of enumeration elements list.
CAPMOD2_3 : Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved.
#01 : 1
PWM_RCAPDAT2/3 register
#10 : 2
PWM_FCAPDAT2/3 register
#11 : 3
Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3 registers
End of enumeration elements list.
CAPORD2_3 : Capture Channel 2/3 Rising/Falling Order \nSet this bit to determine whether the PWM_RCAPDAT2/3 or PWM_FCAPDAT2/3 register is the first captured data transferred to memory through PDMA when CAPMOD2_3 bits are set to 0x3.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_FCAPDAT2/3 register is the first captured data to memory
#1 : 1
PWM_RCAPDAT2/3 register is the first captured data to memory
End of enumeration elements list.
CHSEL2_3 : Select Channel 2/3 to Do PDMA Transfer
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel2
#1 : 1
Channel3
End of enumeration elements list.
CHEN4_5 : Channel 4/5 PDMA Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 4/5 PDMA function Disabled
#1 : 1
Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory
End of enumeration elements list.
CAPMOD4_5 : Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved.
#01 : 1
PWM_RCAPDAT4/5 register
#10 : 2
PWM_FCAPDAT4/5 register
#11 : 3
Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5 registers
End of enumeration elements list.
CAPORD4_5 : Capture Channel 4/5 Rising/Falling Order \nSet this bit to determine whether the PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 register is the first captured data transferred to memory through PDMA when CAPMOD4_5 bits are set to 0x3.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_FCAPDAT4/5 register is the first captured data to memory
#1 : 1
PWM_RCAPDAT4/5 register is the first captured data to memory
End of enumeration elements list.
CHSEL4_5 : Select Channel 4/5 to Do PDMA Transfer
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel4
#1 : 1
Channel5
End of enumeration elements list.
PWM Clear Counter Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTCLR0 : Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit PWM counter to 0x0000(CNT(PWM_CNTn[15:0]))
End of enumeration elements list.
CNTCLR1 : Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit PWM counter to 0x0000(CNT(PWM_CNTn[15:0]))
End of enumeration elements list.
CNTCLR2 : Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit PWM counter to 0x0000(CNT(PWM_CNTn[15:0]))
End of enumeration elements list.
CNTCLR3 : Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit PWM counter to 0x0000(CNT(PWM_CNTn[15:0]))
End of enumeration elements list.
CNTCLR4 : Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit PWM counter to 0x0000(CNT(PWM_CNTn[15:0]))
End of enumeration elements list.
CNTCLR5 : Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit PWM counter to 0x0000(CNT(PWM_CNTn[15:0]))
End of enumeration elements list.
PWM Capture Channel 0/1 PDMA Register
address_offset : 0x240 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPBUF : PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
bits : 0 - 15 (16 bit)
access : read-only
PWM Capture Channel 2/3 PDMA Register
address_offset : 0x244 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Capture Channel 4/5 PDMA Register
address_offset : 0x248 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Capture Interrupt Enable Register
address_offset : 0x250 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPRIEN0 : PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPRIENn bit must be disabled.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPRIEN1 : PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPRIENn bit must be disabled.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPRIEN2 : PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPRIENn bit must be disabled.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPRIEN3 : PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPRIENn bit must be disabled.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPRIEN4 : PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPRIENn bit must be disabled.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPRIEN5 : PWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPRIENn bit must be disabled.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN0 : PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPFIENn bit must be disabled.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN1 : PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPFIENn bit must be disabled.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN2 : PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPFIENn bit must be disabled.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN3 : PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPFIENn bit must be disabled.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN4 : PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPFIENn bit must be disabled.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN5 : PWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CAPFIENn bit must be disabled.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
PWM Capture Interrupt Flag Register
address_offset : 0x254 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRLIF0 : PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer data.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CRLIF1 : PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer data.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CRLIF2 : PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer data.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CRLIF3 : PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer data.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CRLIF4 : PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer data.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CRLIF5 : PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CRLIFn bit will cleared by hardware after PDMA transfer data.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF0 : PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer data.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF1 : PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer data.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF2 : PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer data.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF3 : PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer data.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF4 : PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer data.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF5 : PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, corresponding channel CFLIFn bit will cleared by hardware after PDMA transfer data.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
PWM Load Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOAD0 : Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.\nWrite Operation:
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nNo load window is set
#1 : 1
Set load window of window loading mode.\nLoad window is set
End of enumeration elements list.
LOAD1 : Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.\nWrite Operation:
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nNo load window is set
#1 : 1
Set load window of window loading mode.\nLoad window is set
End of enumeration elements list.
LOAD2 : Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.\nWrite Operation:
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nNo load window is set
#1 : 1
Set load window of window loading mode.\nLoad window is set
End of enumeration elements list.
LOAD3 : Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.\nWrite Operation:
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nNo load window is set
#1 : 1
Set load window of window loading mode.\nLoad window is set
End of enumeration elements list.
LOAD4 : Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.\nWrite Operation:
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nNo load window is set
#1 : 1
Set load window of window loading mode.\nLoad window is set
End of enumeration elements list.
LOAD5 : Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, and hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.\nWrite Operation:
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nNo load window is set
#1 : 1
Set load window of window loading mode.\nLoad window is set
End of enumeration elements list.
PWM Period Register 0
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : PWM Period Register\nUp-Count mode: \nIn this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.
bits : 0 - 15 (16 bit)
access : read-write
PWM PERIOD0 Buffer
address_offset : 0x304 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PBUF : PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register.
bits : 0 - 15 (16 bit)
access : read-only
PWM PERIOD1 Buffer
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM PERIOD2 Buffer
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM PERIOD3 Buffer
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM PERIOD4 Buffer
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM PERIOD5 Buffer
address_offset : 0x318 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM CMPDAT0 Buffer
address_offset : 0x31C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMPBUF : PWM Comparator Register Buffer (Read Only)\nUsed as CMPDAT active register.
bits : 0 - 15 (16 bit)
access : read-only
PWM CMPDAT1 Buffer
address_offset : 0x320 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM CMPDAT2 Buffer
address_offset : 0x324 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM CMPDAT3 Buffer
address_offset : 0x328 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM CMPDAT4 Buffer
address_offset : 0x32C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM CMPDAT5 Buffer
address_offset : 0x330 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM CLKPSC0_1 Buffer
address_offset : 0x334 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPSCBUF : PWM Counter Clock Pre-scale Buffer\nUsed as PWM counter clock pre-scare active register.
bits : 0 - 11 (12 bit)
access : read-only
PWM CLKPSC2_3 Buffer
address_offset : 0x338 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM CLKPSC4_5 Buffer
address_offset : 0x33C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Period Register 1
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM FTCMPDAT0_1 Buffer
address_offset : 0x340 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FTCMPBUF : PWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register.
bits : 0 - 15 (16 bit)
access : read-only
PWM FTCMPDAT2_3 Buffer
address_offset : 0x344 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM FTCMPDAT4_5 Buffer
address_offset : 0x348 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM FTCMPDAT Indicator Register
address_offset : 0x34C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTCMU0 : PWM FTCMPDAT Up Indicator\nIndicator will be set to high when FTCMP(PWM_CTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 1, software can write 1 to clear this bit. Each bit n controls the corresponding PWM channel n.
bits : 0 - 0 (1 bit)
access : read-write
FTCMU2 : PWM FTCMPDAT Up Indicator\nIndicator will be set to high when FTCMP(PWM_CTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 1, software can write 1 to clear this bit. Each bit n controls the corresponding PWM channel n.
bits : 1 - 1 (1 bit)
access : read-write
FTCMU4 : PWM FTCMPDAT Up Indicator\nIndicator will be set to high when FTCMP(PWM_CTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 1, software can write 1 to clear this bit. Each bit n controls the corresponding PWM channel n.
bits : 2 - 2 (1 bit)
access : read-write
FTCMD0 : PWM FTCMPDAT Down Indicator\nIndicator will be set to high when FTCMP(PWM_FTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 0, software can write 1 to clear this bit. Each bit n controls the corresponding PWM channel n.
bits : 8 - 8 (1 bit)
access : read-write
FTCMD2 : PWM FTCMPDAT Down Indicator\nIndicator will be set to high when FTCMP(PWM_FTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 0, software can write 1 to clear this bit. Each bit n controls the corresponding PWM channel n.
bits : 9 - 9 (1 bit)
access : read-write
FTCMD4 : PWM FTCMPDAT Down Indicator\nIndicator will be set to high when FTCMP(PWM_FTCMPDATn[15:0]) bits equal to PERIOD(PWM_PERIODn[15:0]) bits and DIRF(PWM_CNTn[16]) bit is 0, software can write 1 to clear this bit. Each bit n controls the corresponding PWM channel n.
bits : 10 - 10 (1 bit)
access : read-write
PWM Period Register 2
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Period Register 3
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Control Register 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTTYPE0 : PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supported in capture mode)
#01 : 1
Down count type (supported in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved.
End of enumeration elements list.
CNTTYPE1 : PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supported in capture mode)
#01 : 1
Down count type (supported in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved.
End of enumeration elements list.
CNTTYPE2 : PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supported in capture mode)
#01 : 1
Down count type (supported in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved.
End of enumeration elements list.
CNTTYPE3 : PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supported in capture mode)
#01 : 1
Down count type (supported in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved.
End of enumeration elements list.
CNTTYPE4 : PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supported in capture mode)
#01 : 1
Down count type (supported in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved.
End of enumeration elements list.
CNTTYPE5 : PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supported in capture mode)
#01 : 1
Down count type (supported in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved.
End of enumeration elements list.
CNTMODE0 : PWM Counter Mode\nEach bit n controls the corresponding PWM channel n.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-reload mode
#1 : 1
One-shot mode
End of enumeration elements list.
CNTMODE1 : PWM Counter Mode\nEach bit n controls the corresponding PWM channel n.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-reload mode
#1 : 1
One-shot mode
End of enumeration elements list.
CNTMODE2 : PWM Counter Mode\nEach bit n controls the corresponding PWM channel n.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-reload mode
#1 : 1
One-shot mode
End of enumeration elements list.
CNTMODE3 : PWM Counter Mode\nEach bit n controls the corresponding PWM channel n.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-reload mode
#1 : 1
One-shot mode
End of enumeration elements list.
CNTMODE4 : PWM Counter Mode\nEach bit n controls the corresponding PWM channel n.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-reload mode
#1 : 1
One-shot mode
End of enumeration elements list.
CNTMODE5 : PWM Counter Mode\nEach bit n controls the corresponding PWM channel n.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-reload mode
#1 : 1
One-shot mode
End of enumeration elements list.
OUTMODE0 : PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function, these bits must all set to the same mode.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM independent mode
#1 : 1
PWM complementary mode
End of enumeration elements list.
OUTMODE2 : PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function, these bits must all set to the same mode.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM independent mode
#1 : 1
PWM complementary mode
End of enumeration elements list.
OUTMODE4 : PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function, these bits must all set to the same mode.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM independent mode
#1 : 1
PWM complementary mode
End of enumeration elements list.
PWM Period Register 4
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Period Register 5
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 0
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP : PWM Comparator Register\nCMP bits use to compare with CNT(PWM_CNTn[15:0]) bits to generate PWM waveform, interrupt and trigger ADC.\nIn independent mode, CMPDAT0~5 registers denote as 6 independent PWMx_CH0~5 compared point.\nIn complementary mode, CMPDAT0, 2, 4 registers denote as first compared point, and CMPDAT1, 3, 5 register denote as second compared point for the corresponding 3 complementary pairs PWMx_CH0 and PWMx_CH1, PWMx_CH2 and PWMx_CH3, PWMx_CH4 and PWMx_CH5
bits : 0 - 15 (16 bit)
access : read-write
PWM Comparator Register 1
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 2
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 3
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 4
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 5
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Dead-time Control Register 0/1
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCNT : Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 11 (12 bit)
access : read-write
DTEN : Enable Dead-time Insertion for PWM Pair (PWMx_CH0, PWMx_CH1) (PWMx_CH2, PWMx_CH3) (PWMx_CH4, PWMx_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-time insertion Disabled on the pin pair
#1 : 1
Dead-time insertion Enabled on the pin pair
End of enumeration elements list.
DTCKSEL : Dead-time Clock Select (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-time clock source from PWMx_CLK without counter clock prescale
#1 : 1
Dead-time clock source from prescaler output with counter clock prescale
End of enumeration elements list.
PWM Dead-time Control Register 2/3
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Dead-time Control Register 4/5
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Synchronization Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHSEN0 : SYNC Phase Enable Bits\nn denotes PWM channel 0,2,4 and m denotes channel 1,3,5.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM counter disable to load value of PHS(PWM_PHSn_m[15:0]) bits
#1 : 1
PWM counter enable to load value of PHS(PWM_PHSn_m[15:0]) bits
End of enumeration elements list.
PHSEN2 : SYNC Phase Enable Bits\nn denotes PWM channel 0,2,4 and m denotes channel 1,3,5.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM counter disable to load value of PHS(PWM_PHSn_m[15:0]) bits
#1 : 1
PWM counter enable to load value of PHS(PWM_PHSn_m[15:0]) bits
End of enumeration elements list.
PHSEN4 : SYNC Phase Enable Bits\nn denotes PWM channel 0,2,4 and m denotes channel 1,3,5.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM counter disable to load value of PHS(PWM_PHSn_m[15:0]) bits
#1 : 1
PWM counter enable to load value of PHS(PWM_PHSn_m[15:0]) bits
End of enumeration elements list.
SINSRC0 : PWM0_SYNC_IN Source Selection\nEach bit n controls corresponding PWM channel n.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Synchronize source from SYNC_IN or SWSYNC
#01 : 1
Counter equal to 0
#10 : 2
Counter equal to PWM_CMPDATm, m denotes 1, 3, 5
#11 : 3
SYNC_OUT signal will not be generated
End of enumeration elements list.
SINSRC2 : PWM0_SYNC_IN Source Selection\nEach bit n controls corresponding PWM channel n.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Synchronize source from SYNC_IN or SWSYNC
#01 : 1
Counter equal to 0
#10 : 2
Counter equal to PWM_CMPDATm, m denotes 1, 3, 5
#11 : 3
SYNC_OUT signal will not be generated
End of enumeration elements list.
SINSRC4 : PWM0_SYNC_IN Source Selection\nEach bit n controls corresponding PWM channel n.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
Synchronize source from SYNC_IN or SWSYNC
#01 : 1
Counter equal to 0
#10 : 2
Counter equal to PWM_CMPDATm, m denotes 1, 3, 5
#11 : 3
SYNC_OUT signal will not be generated
End of enumeration elements list.
SNFLTEN : PWM0_SYNC_IN Noise Filter Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter of input PWM0_SYNC_IN pin Disabled
#1 : 1
Noise filter of input PWM0_SYNC_IN pin Enabled
End of enumeration elements list.
SFLTCSEL : SYNC Edge Detector Filter Clock Selection
bits : 17 - 19 (3 bit)
access : read-write
Enumeration:
#000 : 0
Filter clock = HCLK
#001 : 1
Filter clock = HCLK/2
#010 : 2
Filter clock = HCLK/4
#011 : 3
Filter clock = HCLK/8
#100 : 4
Filter clock = HCLK/16
#101 : 5
Filter clock = HCLK/32
#110 : 6
Filter clock = HCLK/64
#111 : 7
Filter clock = HCLK/128
End of enumeration elements list.
SFLTCNT : SYNC Edge Detector Filter Count\nThe register bits control the counter number of edge detector.
bits : 20 - 22 (3 bit)
access : read-write
SINPINV : SYNC Input Pin Inverse
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
The state of PWM0_SYNC_IN pin is passed to the negative edge detector
#1 : 1
The inversed state of PWM0_SYNC_IN pin is passed to the negative edge detector
End of enumeration elements list.
PHSDIR0 : PWM Phase Direction Control\nEach bit n controls corresponding PWM channel n.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Control PWM counter count decrement after synchronizing
#1 : 1
Control PWM counter count increment after synchronizing
End of enumeration elements list.
PHSDIR2 : PWM Phase Direction Control\nEach bit n controls corresponding PWM channel n.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Control PWM counter count decrement after synchronizing
#1 : 1
Control PWM counter count increment after synchronizing
End of enumeration elements list.
PHSDIR4 : PWM Phase Direction Control\nEach bit n controls corresponding PWM channel n.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Control PWM counter count decrement after synchronizing
#1 : 1
Control PWM counter count increment after synchronizing
End of enumeration elements list.
PWM Counter Phase Register 0/1
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHS : PWM Synchronous Start Phase Bits\nPHS bits determines the PWM synchronous start phase value. These bits only use in synchronous function.
bits : 0 - 15 (16 bit)
access : read-write
PWM Counter Phase Register 2/3
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Phase Register 4/5
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Register 0
address_offset : 0x90 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : PWM Counter Data Bits (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter.
bits : 0 - 15 (16 bit)
access : read-only
DIRF : PWM Direction Indicator Flag (Read Only)
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Counter is Down count
#1 : 1
Counter is UP count
End of enumeration elements list.
PWM Counter Register 1
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Register 2
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Register 3
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Register 4
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Register 5
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Generation Register 0
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZPCTL0 : PWM Zero Point Control\nPWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM zero point output Low
#10 : 2
PWM zero point output High
#11 : 3
PWM zero point output Toggle
End of enumeration elements list.
ZPCTL1 : PWM Zero Point Control\nPWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM zero point output Low
#10 : 2
PWM zero point output High
#11 : 3
PWM zero point output Toggle
End of enumeration elements list.
ZPCTL2 : PWM Zero Point Control\nPWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM zero point output Low
#10 : 2
PWM zero point output High
#11 : 3
PWM zero point output Toggle
End of enumeration elements list.
ZPCTL3 : PWM Zero Point Control\nPWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM zero point output Low
#10 : 2
PWM zero point output High
#11 : 3
PWM zero point output Toggle
End of enumeration elements list.
ZPCTL4 : PWM Zero Point Control\nPWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM zero point output Low
#10 : 2
PWM zero point output High
#11 : 3
PWM zero point output Toggle
End of enumeration elements list.
ZPCTL5 : PWM Zero Point Control\nPWM can control output level on zero point event. Each bit n controls the corresponding PWM channel n.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM zero point output Low
#10 : 2
PWM zero point output High
#11 : 3
PWM zero point output Toggle
End of enumeration elements list.
PRDPCTL0 : PWM Period (Center) Point Control\nPWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n.\nNote: This bit is center point control when PWM counter operating in up-down counter type.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM period (center) point output Low
#10 : 2
PWM period (center) point output High
#11 : 3
PWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL1 : PWM Period (Center) Point Control\nPWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n.\nNote: This bit is center point control when PWM counter operating in up-down counter type.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM period (center) point output Low
#10 : 2
PWM period (center) point output High
#11 : 3
PWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL2 : PWM Period (Center) Point Control\nPWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n.\nNote: This bit is center point control when PWM counter operating in up-down counter type.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM period (center) point output Low
#10 : 2
PWM period (center) point output High
#11 : 3
PWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL3 : PWM Period (Center) Point Control\nPWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n.\nNote: This bit is center point control when PWM counter operating in up-down counter type.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM period (center) point output Low
#10 : 2
PWM period (center) point output High
#11 : 3
PWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL4 : PWM Period (Center) Point Control\nPWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n.\nNote: This bit is center point control when PWM counter operating in up-down counter type.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM period (center) point output Low
#10 : 2
PWM period (center) point output High
#11 : 3
PWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL5 : PWM Period (Center) Point Control\nPWM can control output level on period(center) point event. Each bit n controls the corresponding PWM channel n.\nNote: This bit is center point control when PWM counter operating in up-down counter type.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM period (center) point output Low
#10 : 2
PWM period (center) point output High
#11 : 3
PWM period (center) point output Toggle
End of enumeration elements list.
PWM Generation Register 1
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPUCTL0 : PWM Compare Up Point Control\nPWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare up point output Low
#10 : 2
PWM compare up point output High
#11 : 3
PWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL1 : PWM Compare Up Point Control\nPWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare up point output Low
#10 : 2
PWM compare up point output High
#11 : 3
PWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL2 : PWM Compare Up Point Control\nPWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare up point output Low
#10 : 2
PWM compare up point output High
#11 : 3
PWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL3 : PWM Compare Up Point Control\nPWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare up point output Low
#10 : 2
PWM compare up point output High
#11 : 3
PWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL4 : PWM Compare Up Point Control\nPWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare up point output Low
#10 : 2
PWM compare up point output High
#11 : 3
PWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL5 : PWM Compare Up Point Control\nPWM can control output level on compare up point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare up point output Low
#10 : 2
PWM compare up point output High
#11 : 3
PWM compare up point output Toggle
End of enumeration elements list.
CMPDCTL0 : PWM Compare Down Point Control\nPWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare down point output Low
#10 : 2
PWM compare down point output High
#11 : 3
PWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL1 : PWM Compare Down Point Control\nPWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare down point output Low
#10 : 2
PWM compare down point output High
#11 : 3
PWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL2 : PWM Compare Down Point Control\nPWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare down point output Low
#10 : 2
PWM compare down point output High
#11 : 3
PWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL3 : PWM Compare Down Point Control\nPWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare down point output Low
#10 : 2
PWM compare down point output High
#11 : 3
PWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL4 : PWM Compare Down Point Control\nPWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare down point output Low
#10 : 2
PWM compare down point output High
#11 : 3
PWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL5 : PWM Compare Down Point Control\nPWM can control output level on compare down point event. Each bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare down point output Low
#10 : 2
PWM compare down point output High
#11 : 3
PWM compare down point output Toggle
End of enumeration elements list.
PWM Mask Enable Register
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSKEN0 : PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output signal is non-masked
#1 : 1
PWM output signal is masked and output MSKDATn data
End of enumeration elements list.
MSKEN1 : PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output signal is non-masked
#1 : 1
PWM output signal is masked and output MSKDATn data
End of enumeration elements list.
MSKEN2 : PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output signal is non-masked
#1 : 1
PWM output signal is masked and output MSKDATn data
End of enumeration elements list.
MSKEN3 : PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output signal is non-masked
#1 : 1
PWM output signal is masked and output MSKDATn data
End of enumeration elements list.
MSKEN4 : PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output signal is non-masked
#1 : 1
PWM output signal is masked and output MSKDATn data
End of enumeration elements list.
MSKEN5 : PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data. Each bit n controls the corresponding PWM channel n.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output signal is non-masked
#1 : 1
PWM output signal is masked and output MSKDATn data
End of enumeration elements list.
PWM Mask Data Register
address_offset : 0xBC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSKDAT0 : PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to PWMx_CHn
#1 : 1
Output logic high to PWMx_CHn
End of enumeration elements list.
MSKDAT1 : PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to PWMx_CHn
#1 : 1
Output logic high to PWMx_CHn
End of enumeration elements list.
MSKDAT2 : PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to PWMx_CHn
#1 : 1
Output logic high to PWMx_CHn
End of enumeration elements list.
MSKDAT3 : PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to PWMx_CHn
#1 : 1
Output logic high to PWMx_CHn
End of enumeration elements list.
MSKDAT4 : PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to PWMx_CHn
#1 : 1
Output logic high to PWMx_CHn
End of enumeration elements list.
MSKDAT5 : PWM Mask Data Bit\nThis data bit control the state of PWMx_CHn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to PWMx_CHn
#1 : 1
Output logic high to PWMx_CHn
End of enumeration elements list.
PWM Software Control Synchronization Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWSYNC0 : Software SYNC Function\nEach bit n controls corresponding PWM channel n.\nWhen SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
bits : 0 - 0 (1 bit)
access : read-write
SWSYNC2 : Software SYNC Function\nEach bit n controls corresponding PWM channel n.\nWhen SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
bits : 1 - 1 (1 bit)
access : read-write
SWSYNC4 : Software SYNC Function\nEach bit n controls corresponding PWM channel n.\nWhen SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
bits : 2 - 2 (1 bit)
access : read-write
PWM Brake Noise Filter Register
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRK0NFEN : PWM Brake 0 Noise Filter Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter of PWM Brake 0 Disabled
#1 : 1
Noise filter of PWM Brake 0 Enabled
End of enumeration elements list.
BRK0NFSEL : Brake 0 Edge Detector Filter Clock Selection
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
#000 : 0
Filter clock = HCLK
#001 : 1
Filter clock = HCLK/2
#010 : 2
Filter clock = HCLK/4
#011 : 3
Filter clock = HCLK/8
#100 : 4
Filter clock = HCLK/16
#101 : 5
Filter clock = HCLK/32
#110 : 6
Filter clock = HCLK/64
#111 : 7
Filter clock = HCLK/128
End of enumeration elements list.
BRK0FCNT : Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK0FCNT.
bits : 4 - 6 (3 bit)
access : read-write
BRK0PINV : Brake 0 Pin Inverse
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake pin event will be detected if PWM0_BRAKEx pin status transfer from low to high in edge-detect, or pin status is high in level-detect
#1 : 1
Brake pin event will be detected if PWM0_BRAKEx pin status transfer from high to low in edge-detect, or pin status is low in level-detect
End of enumeration elements list.
BRK1NFEN : PWM Brake 1 Noise Filter Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter of PWM Brake 1 Disabled
#1 : 1
Noise filter of PWM Brake 1 Enabled
End of enumeration elements list.
BRK1NFSEL : Brake 1 Edge Detector Filter Clock Selection
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
#000 : 0
Filter clock = HCLK
#001 : 1
Filter clock = HCLK/2
#010 : 2
Filter clock = HCLK/4
#011 : 3
Filter clock = HCLK/8
#100 : 4
Filter clock = HCLK/16
#101 : 5
Filter clock = HCLK/32
#110 : 6
Filter clock = HCLK/64
#111 : 7
Filter clock = HCLK/128
End of enumeration elements list.
BRK1FCNT : Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
bits : 12 - 14 (3 bit)
access : read-write
BRK1PINV : Brake 1 Pin Inverse
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake pin event will be detected if PWM1_BRAKEx pin status transfer from low to high in edge-detect, or pin status is high in level-detect
#1 : 1
Brake pin event will be detected if PWM1_BRAKEx pin status transfer from high to low in edge-detect, or pin status is low in level-detect
End of enumeration elements list.
BK0SRC : Brake 0 Pin Source Select\nFor PWM0 setting:
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake 0 pin source come from PWM0_BRAKE0.\nBrake 0 pin source come from PWM1_BRAKE0
#1 : 1
Brake 0 pin source come from PWM1_BRAKE0.\nBrake 0 pin source come from PWM0_BRAKE0
End of enumeration elements list.
BK1SRC : Brake 1 Pin Source Select\nFor PWM0 setting:
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake 1 pin source come from PWM0_BRAKE1.\nBrake 1 pin source come from PWM1_BRAKE1
#1 : 1
Brake 1 pin source come from PWM1_BRAKE1.\nBrake 1 pin source come from PWM0_BRAKE1
End of enumeration elements list.
PWM System Fail Brake Control Register
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSSBRKEN : Clock Security System Detection Trigger PWM Brake Function Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function triggered by clock fail detection Disabled
#1 : 1
Brake Function triggered by clock fail detection Enabled
End of enumeration elements list.
BODBRKEN : Brown-out Detection Trigger PWM Brake Function Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function triggered by BOD event Disabled
#1 : 1
Brake Function triggered by BOD event Enabled
End of enumeration elements list.
CORBRKEN : Core Lockup Detection Trigger PWM Brake Function Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function triggered by Core lockup event Disabled
#1 : 1
Brake Function triggered by Core lockup event Enabled
End of enumeration elements list.
PWM Brake Edge Detect Control Register 0/1
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPO0EBEN : Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP0_O as edge-detect brake source Disabled
#1 : 1
ACMP0_O as edge-detect brake source Enabled
End of enumeration elements list.
CPO1EBEN : Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP1_O as edge-detect brake source Disabled
#1 : 1
ACMP1_O as edge-detect brake source Enabled
End of enumeration elements list.
BRKP0EEN : Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_BRAKE0 pin as edge-detect brake source Disabled
#1 : 1
PWMx_BRAKE0 pin as edge-detect brake source Enabled
End of enumeration elements list.
BRKP1EEN : Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_BRAKE1 pin as edge-detect brake source Disabled
#1 : 1
PWMx_BRAKE1 pin as edge-detect brake source Enabled
End of enumeration elements list.
SYSEBEN : Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
System Fail condition as edge-detect brake source Disabled
#1 : 1
System Fail condition as edge-detect brake source Enabled
End of enumeration elements list.
CPO0LBEN : Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP0_O as level-detect brake source Disabled
#1 : 1
ACMP0_O as level-detect brake source Enabled
End of enumeration elements list.
CPO1LBEN : Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP1_O as level-detect brake source Disabled
#1 : 1
ACMP1_O as level-detect brake source Enabled
End of enumeration elements list.
BRKP0LEN : Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_BRAKE0 pin as level-detect brake source Disabled
#1 : 1
PWMx_BRAKE0 pin as level-detect brake source Enabled
End of enumeration elements list.
BRKP1LEN : Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_BRAKE1 pin as level-detect brake source Disabled
#1 : 1
PWMx_BRAKE1 pin as level-detect brake source Enabled
End of enumeration elements list.
SYSLBEN : Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
System Fail condition as level-detect brake source Disabled
#1 : 1
System Fail condition as level-detect brake source Enabled
End of enumeration elements list.
BRKAEVEN : PWM Brake Action Select for Even Channel (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
PWMx brake event will not affect even channels output
#01 : 1
PWM even channel output tri-state when PWMx brake event happened
#10 : 2
PWM even channel output low level when PWMx brake event happened
#11 : 3
PWM even channel output high level when PWMx brake event happened
End of enumeration elements list.
BRKAODD : PWM Brake Action Select for Odd Channel (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
PWMx brake event will not affect odd channels output
#01 : 1
PWM odd channel output tri-state when PWMx brake event happened
#10 : 2
PWM odd channel output low level when PWMx brake event happened
#11 : 3
PWM odd channel output high level when PWMx brake event happened
End of enumeration elements list.
ADCEBEN : Enable ADC Result Monitor (ADCRM) As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADCRM as edge-detect brake source Disabled
#1 : 1
ADCRM as edge-detect brake source Enabled
End of enumeration elements list.
ADCLBEN : Enable ADC Result Monitor (ADCRM) As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADCRM as level-detect brake source Disabled
#1 : 1
ADCRM as level-detect brake source Enabled
End of enumeration elements list.
PWM Brake Edge Detect Control Register 2/3
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Brake Edge Detect Control Register 4/5
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Pin Polar Inverse Register
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PINV0 : PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CHn output pin polar inverse Disabled
#1 : 1
PWMx_CHn output pin polar inverse Enabled
End of enumeration elements list.
PINV1 : PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CHn output pin polar inverse Disabled
#1 : 1
PWMx_CHn output pin polar inverse Enabled
End of enumeration elements list.
PINV2 : PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CHn output pin polar inverse Disabled
#1 : 1
PWMx_CHn output pin polar inverse Enabled
End of enumeration elements list.
PINV3 : PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CHn output pin polar inverse Disabled
#1 : 1
PWMx_CHn output pin polar inverse Enabled
End of enumeration elements list.
PINV4 : PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CHn output pin polar inverse Disabled
#1 : 1
PWMx_CHn output pin polar inverse Enabled
End of enumeration elements list.
PINV5 : PWM PIN Polar Inverse Control\nThe register controls polarity state of PWMx_CHn output pin. Each bit n controls the corresponding PWM channel n.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CHn output pin polar inverse Disabled
#1 : 1
PWMx_CHn output pin polar inverse Enabled
End of enumeration elements list.
PWM Output Enable Register
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POEN0 : PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CHn pin at tri-state
#1 : 1
PWMx_CHn pin in output mode
End of enumeration elements list.
POEN1 : PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CHn pin at tri-state
#1 : 1
PWMx_CHn pin in output mode
End of enumeration elements list.
POEN2 : PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CHn pin at tri-state
#1 : 1
PWMx_CHn pin in output mode
End of enumeration elements list.
POEN3 : PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CHn pin at tri-state
#1 : 1
PWMx_CHn pin in output mode
End of enumeration elements list.
POEN4 : PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CHn pin at tri-state
#1 : 1
PWMx_CHn pin in output mode
End of enumeration elements list.
POEN5 : PWMx_CHn Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CHn pin at tri-state
#1 : 1
PWMx_CHn pin in output mode
End of enumeration elements list.
PWM Software Brake Control Register
address_offset : 0xDC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BRKETRG0 : PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n.\nNote: This register is write protected. Refer to REGWRPROT register.
bits : 0 - 0 (1 bit)
access : write-only
BRKETRG2 : PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n.\nNote: This register is write protected. Refer to REGWRPROT register.
bits : 1 - 1 (1 bit)
access : write-only
BRKETRG4 : PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n.\nNote: This register is write protected. Refer to REGWRPROT register.
bits : 2 - 2 (1 bit)
access : write-only
BRKLTRG0 : PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n.\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : write-only
BRKLTRG2 : PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n.\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : write-only
BRKLTRG4 : PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn bits to 1 in PWM_INTSTS1 register. Each bit n controls the corresponding PWM pair n.\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 10 - 10 (1 bit)
access : write-only
PWM Interrupt Enable Register 0
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZIEN0 : PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
ZIEN1 : PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
ZIEN2 : PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
ZIEN3 : PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
ZIEN4 : PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
ZIEN5 : PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
IFAIEN0_1 : PWM Channel 0/1 Interrupt Flag Accumulator Interrupt Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Flag accumulator interrupt Disabled
#1 : 1
Interrupt Flag accumulator interrupt Enabled
End of enumeration elements list.
PIEN0 : PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
PIEN1 : PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
PIEN2 : PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
PIEN3 : PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
PIEN4 : PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
PIEN5 : PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
IFAIEN2_3 : PWM Channel 2/3 Interrupt Flag Accumulator Interrupt Enable Bit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Flag accumulator interrupt Disabled
#1 : 1
Interrupt Flag accumulator interrupt Enabled
End of enumeration elements list.
CMPUIEN0 : PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN1 : PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN2 : PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN3 : PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN4 : PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN5 : PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
IFAIEN4_5 : PWM Channel 4/5 Interrupt Flag Accumulator Interrupt Enable Bit
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Flag accumulator interrupt Disabled
#1 : 1
Interrupt Flag accumulator interrupt Enabled
End of enumeration elements list.
CMPDIEN0 : PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN1 : PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN2 : PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN3 : PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN4 : PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN5 : PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
PWM Interrupt Enable Register 1
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKEIEN0_1 : PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-detect Brake interrupt for channel0/1 Disabled
#1 : 1
Edge-detect Brake interrupt for channel0/1 Enabled
End of enumeration elements list.
BRKEIEN2_3 : PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-detect Brake interrupt for channel2/3 Disabled
#1 : 1
Edge-detect Brake interrupt for channel2/3 Enabled
End of enumeration elements list.
BRKEIEN4_5 : PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-detect Brake interrupt for channel4/5 Disabled
#1 : 1
Edge-detect Brake interrupt for channel4/5 Enabled
End of enumeration elements list.
BRKLIEN0_1 : PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Level-detect Brake interrupt for channel0/1 Disabled
#1 : 1
Level-detect Brake interrupt for channel0/1 Enabled
End of enumeration elements list.
BRKLIEN2_3 : PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Level-detect Brake interrupt for channel2/3 Disabled
#1 : 1
Level-detect Brake interrupt for channel2/3 Enabled
End of enumeration elements list.
BRKLIEN4_5 : PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Level-detect Brake interrupt for channel4/5 Disabled
#1 : 1
Level-detect Brake interrupt for channel4/5 Enabled
End of enumeration elements list.
PWM Interrupt Flag Register 0
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZIF0 : PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
bits : 0 - 0 (1 bit)
access : read-write
ZIF1 : PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
bits : 1 - 1 (1 bit)
access : read-write
ZIF2 : PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
bits : 2 - 2 (1 bit)
access : read-write
ZIF3 : PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
bits : 3 - 3 (1 bit)
access : read-write
ZIF4 : PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
bits : 4 - 4 (1 bit)
access : read-write
ZIF5 : PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
bits : 5 - 5 (1 bit)
access : read-write
IFAIF0_1 : PWM Channel 0/1 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFSEL0_1 bits in PWM_IFA register, software can clear this bit by writing 1 to it.
bits : 7 - 7 (1 bit)
access : read-write
PIF0 : PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]), software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n.
bits : 8 - 8 (1 bit)
access : read-write
PIF1 : PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]), software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n.
bits : 9 - 9 (1 bit)
access : read-write
PIF2 : PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]), software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n.
bits : 10 - 10 (1 bit)
access : read-write
PIF3 : PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]), software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n.
bits : 11 - 11 (1 bit)
access : read-write
PIF4 : PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]), software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n.
bits : 12 - 12 (1 bit)
access : read-write
PIF5 : PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PERIOD(PWM_PERIODn[15:0]), software can write 1 to clear this bit to zero. Each bit n controls the corresponding PWM channel n.
bits : 13 - 13 (1 bit)
access : read-write
IFAIF2_3 : PWM Channel 2/3 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFSEL2_3 bits in PWM_IFA register, software can clear this bit by writing 1 to it.
bits : 15 - 15 (1 bit)
access : read-write
CMPUIF0 : PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4.
bits : 16 - 16 (1 bit)
access : read-write
CMPUIF1 : PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4.
bits : 17 - 17 (1 bit)
access : read-write
CMPUIF2 : PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4.
bits : 18 - 18 (1 bit)
access : read-write
CMPUIF3 : PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4.
bits : 19 - 19 (1 bit)
access : read-write
CMPUIF4 : PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4.
bits : 20 - 20 (1 bit)
access : read-write
CMPUIF5 : PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4.
bits : 21 - 21 (1 bit)
access : read-write
IFAIF4_5 : PWM Channel 4/5 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFSEL4_5 bits in PWM_IFA register, software can clear this bit by writing 1 to it.
bits : 23 - 23 (1 bit)
access : read-write
CMPDIF0 : PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
bits : 24 - 24 (1 bit)
access : read-write
CMPDIF1 : PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
bits : 25 - 25 (1 bit)
access : read-write
CMPDIF2 : PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
bits : 26 - 26 (1 bit)
access : read-write
CMPDIF3 : PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
bits : 27 - 27 (1 bit)
access : read-write
CMPDIF4 : PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
bits : 28 - 28 (1 bit)
access : read-write
CMPDIF5 : PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches CMP(PWM_CMPDATn[15:0]), software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMP equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
bits : 29 - 29 (1 bit)
access : read-write
PWM Interrupt Flag Register 1
address_offset : 0xEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKEIF0 : PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n edge-detect brake event do not happened
#1 : 1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKEIF1 : PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n edge-detect brake event do not happened
#1 : 1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKEIF2 : PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n edge-detect brake event do not happened
#1 : 1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKEIF3 : PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n edge-detect brake event do not happened
#1 : 1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKEIF4 : PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n edge-detect brake event do not happened
#1 : 1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKEIF5 : PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n edge-detect brake event do not happened
#1 : 1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKLIFn : PWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n level-detect brake event do not happened
#1 : 1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKESTS0 : PWM Channel N Edge-detect Brake Status
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n edge-detect brake state is released
#1 : 1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state, writing 1 to clear
End of enumeration elements list.
BRKESTS1 : PWM Channel N Edge-detect Brake Status
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n edge-detect brake state is released
#1 : 1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state, writing 1 to clear
End of enumeration elements list.
BRKESTS2 : PWM Channel N Edge-detect Brake Status
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n edge-detect brake state is released
#1 : 1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state, writing 1 to clear
End of enumeration elements list.
BRKESTS3 : PWM Channel N Edge-detect Brake Status
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n edge-detect brake state is released
#1 : 1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state, writing 1 to clear
End of enumeration elements list.
BRKESTS4 : PWM Channel N Edge-detect Brake Status
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n edge-detect brake state is released
#1 : 1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state, writing 1 to clear
End of enumeration elements list.
BRKESTS5 : PWM Channel N Edge-detect Brake Status
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n edge-detect brake state is released
#1 : 1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state, writing 1 to clear
End of enumeration elements list.
BRKLSTS0 : PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel n level-detect brake state is released
#1 : 1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
End of enumeration elements list.
BRKLSTS1 : PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel n level-detect brake state is released
#1 : 1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
End of enumeration elements list.
BRKLSTS2 : PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel n level-detect brake state is released
#1 : 1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
End of enumeration elements list.
BRKLSTS3 : PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel n level-detect brake state is released
#1 : 1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
End of enumeration elements list.
BRKLSTS4 : PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel n level-detect brake state is released
#1 : 1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
End of enumeration elements list.
BRKLSTS5 : PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel n level-detect brake state is released
#1 : 1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the PWM channel n at brake state
End of enumeration elements list.
PWM Interrupt Flag Accumulator Register
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFCNT0_1 : PWM Channel 0/1 Interrupt Flag Counter\nThe register sets the count number which defines how many times of PWM Channel 0/1 period occurs to set IFAIF0_1 bit to request the PWM period interrupt. \nPWM flag will be set in every IFCNT0_1 [3:0] times of PWM period
bits : 0 - 3 (4 bit)
access : read-write
IFSEL0_1 : PWM Channel 0/1 Interrupt Flag Accumulator Source Select
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 0
CNT equal to Zero in channel 0
#001 : 1
CNT equal to PERIOD in channel 0
#010 : 2
CNT equal to CMPU in channel 0
#011 : 3
CNT equal to CMPD in channel 0
#100 : 4
CNT equal to Zero in channel 1
#101 : 5
CNT equal to PERIOD in channel 1
#110 : 6
CNT equal to CMPU in channel 1
#111 : 7
CNT equal to CMPD in channel 1
End of enumeration elements list.
IFAEN0_1 : PWM Channel 0/1 Interrupt Flag Accumulator Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel 0/1 interrupt flag accumulator Disabled
#1 : 1
PWM Channel 0/1 interrupt flag accumulator Enabled
End of enumeration elements list.
IFCNT2_3 : PWM Channel 2/3 Interrupt Flag Counter\nThe register sets the count number which defines how many times of PWM Channel 2/3 period occurs to set IFAIF2_3 bit to request the PWM period interrupt. \nPWM flag will be set in every IFCNT2_3[3:0] times of PWM period.
bits : 8 - 11 (4 bit)
access : read-write
IFSEL2_3 : PWM Channel 2/3 Interrupt Flag Accumulator Source Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
CNT equal to Zero in channel 2
#001 : 1
CNT equal to PERIOD in channel 2
#010 : 2
CNT equal to CMPU in channel 2
#011 : 3
CNT equal to CMPD in channel 2
#100 : 4
CNT equal to Zero in channel 3
#101 : 5
CNT equal to PERIOD in channel 3
#110 : 6
CNT equal to CMPU in channel 3
#111 : 7
CNT equal to CMPD in channel 3
End of enumeration elements list.
IFAEN2_3 : PWM Channel 2/3 Interrupt Flag Accumulator Enable Bit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel 2/3 interrupt flag accumulator Disabled
#1 : 1
PWM Channel 2/3 interrupt flag accumulator Enabled
End of enumeration elements list.
IFCNT4_5 : PWM Channel 4/5 Interrupt Flag Counter\nThe register sets the count number which defines how many times of PWM Channel 4/5 period occurs to set IFAIF4_5 bit to request the PWM period interrupt. \nPWM flag will be set in every IFCNT4_5[3:0] times of PWM period.
bits : 16 - 19 (4 bit)
access : read-write
IFSEL4_5 : PWM Channel 4/5 Interrupt Flag Accumulator Source Select
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
CNT equal to Zero in channel 4
#001 : 1
CNT equal to PERIOD in channel 4
#010 : 2
CNT equal to CMPU in channel 4
#011 : 3
CNT equal to CMPD in channel 4
#100 : 4
CNT equal to Zero in channel 5
#101 : 5
CNT equal to PERIOD in channel 5
#110 : 6
CNT equal to CMPU in channel 5
#111 : 7
CNT equal to CMPD in channel 5
End of enumeration elements list.
IFAEN4_5 : PWM Channel 4/5 Interrupt Flag Accumulator Enable Bit
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel 4/5 interrupt flag accumulator Disabled
#1 : 1
PWM Channel 4/5 interrupt flag accumulator Enabled
End of enumeration elements list.
PWM Trigger ADC Source Select Register 0
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL0 : PWM_CH0 Trigger ADC Source Select
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_CH0 zero point
#0001 : 1
PWM_CH0 period point
#0010 : 2
PWM_CH0 zero or period point
#0011 : 3
PWM_CH0 up-count compared point
#0100 : 4
PWM_CH0 down-count compared point
#0101 : 5
PWM_CH1 zero point
#0110 : 6
PWM_CH1 period point
#0111 : 7
PWM_CH1 zero or period point
#1000 : 8
PWM_CH1 up-count compared point
#1001 : 9
PWM_CH1 down-count compared point
#1010 : 10
PWM_CH0 up-count free trigger compared point
#1011 : 11
PWM_CH0 down-count free trigger compared point
#1100 : 12
PWM_CH2 up-count free trigger compared point
#1101 : 13
PWM_CH2 down-count free trigger compared point
#1110 : 14
PWM_CH4 up-count free trigger compared point
#1111 : 15
PWM_CH4 down-count free trigger compared point
End of enumeration elements list.
TRGEN0 : PWM_CH0 Trigger ADC enable bit
bits : 7 - 7 (1 bit)
access : read-write
TRGSEL1 : PWM_CH1 Trigger ADC Source Select
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_CH0 zero point
#0001 : 1
PWM_CH0 period point
#0010 : 2
PWM_CH0 zero or period point
#0011 : 3
PWM_CH0 up-count compared point
#0100 : 4
PWM_CH0 down-count compared point
#0101 : 5
PWM_CH1 zero point
#0110 : 6
PWM_CH1 period point
#0111 : 7
PWM_CH1 zero or period point
#1000 : 8
PWM_CH1 up-count compared point
#1001 : 9
PWM_CH1 down-count compared point
#1010 : 10
PWM_CH0 up-count free trigger compared point
#1011 : 11
PWM_CH0 down-count free trigger compared point
#1100 : 12
PWM_CH2 up-count free trigger compared point
#1101 : 13
PWM_CH2 down-count free trigger compared point
#1110 : 14
PWM_CH4 up-count free trigger compared point
#1111 : 15
PWM_CH4 down-count free trigger compared point
End of enumeration elements list.
TRGEN1 : PWM_CH1 Trigger ADC enable bit
bits : 15 - 15 (1 bit)
access : read-write
TRGSEL2 : PWM_CH2 Trigger ADC Source Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_CH2 zero point
#0001 : 1
PWM_CH2 period point
#0010 : 2
PWM_CH2 zero or period point
#0011 : 3
PWM_CH2 up-count compared point
#0100 : 4
PWM_CH2 down-count compared point
#0101 : 5
PWM_CH3 zero point
#0110 : 6
PWM_CH3 period point
#0111 : 7
PWM_CH3 zero or period point
#1000 : 8
PWM_CH3 up-count compared point
#1001 : 9
PWM_CH3 down-count compared point
#1010 : 10
PWM_CH0 up-count free trigger compared point
#1011 : 11
PWM_CH0 down-count free trigger compared point
#1100 : 12
PWM_CH2 up-count free trigger compared point
#1101 : 13
PWM_CH2 down-count free trigger compared point
#1110 : 14
PWM_CH4 up-count free trigger compared point
#1111 : 15
PWM_CH4 down-count free trigger compared point
End of enumeration elements list.
TRGEN2 : PWM_CH2 Trigger ADC enable bit
bits : 23 - 23 (1 bit)
access : read-write
TRGSEL3 : PWM_CH3 Trigger ADC Source Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_CH2 zero point
#0001 : 1
PWM_CH2 period point
#0010 : 2
PWM_CH2 zero or period point
#0011 : 3
PWM_CH2 up-count compared point
#0100 : 4
PWM_CH2 down-count compared point
#0101 : 5
PWM_CH3 zero point
#0110 : 6
PWM_CH3 period point
#0111 : 7
PWM_CH3 zero or period point
#1000 : 8
PWM_CH3 up-count compared point
#1001 : 9
PWM_CH3 down-count compared point
#1010 : 10
PWM_CH0 up-count free trigger compared point
#1011 : 11
PWM_CH0 down-count free trigger compared point
#1100 : 12
PWM_CH2 up-count free trigger compared point
#1101 : 13
PWM_CH2 down-count free trigger compared point
#1110 : 14
PWM_CH4 up-count free trigger compared point
#1111 : 15
PWM_CH4 down-count free trigger compared point
End of enumeration elements list.
TRGEN3 : PWM_CH3 Trigger ADC enable bit
bits : 31 - 31 (1 bit)
access : read-write
PWM Trigger ADC Source Select Register 1
address_offset : 0xFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL4 : PWM_CH4 Trigger ADC Source Select
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_CH4 zero point
#0001 : 1
PWM_CH4 period point
#0010 : 2
PWM_CH4 zero or period point
#0011 : 3
PWM_CH4 up-count compared point
#0100 : 4
PWM_CH4 down-count compared point
#0101 : 5
PWM_CH5 zero point
#0110 : 6
PWM_CH5 period point
#0111 : 7
PWM_CH5 zero or period point
#1000 : 8
PWM_CH5 up-count compared point
#1001 : 9
PWM_CH5 down-count compared point
#1010 : 10
PWM_CH0 up-count free trigger compared point
#1011 : 11
PWM_CH0 down-count free trigger compared point
#1100 : 12
PWM_CH2 up-count free trigger compared point
#1101 : 13
PWM_CH2 down-count free trigger compared point
#1110 : 14
PWM_CH4 up-count free trigger compared point
#1111 : 15
PWM_CH4 down-count free trigger compared point
End of enumeration elements list.
TRGEN4 : PWM_CH4 Trigger ADC enable bit
bits : 7 - 7 (1 bit)
access : read-write
TRGSEL5 : PWM_CH5 Trigger ADC Source Select
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_CH4 zero point
#0001 : 1
PWM_CH4 period point
#0010 : 2
PWM_CH4 zero or period point
#0011 : 3
PWM_CH4 up-count compared point
#0100 : 4
PWM_CH4 down-count compared point
#0101 : 5
PWM_CH5 zero point
#0110 : 6
PWM_CH5 period point
#0111 : 7
PWM_CH5 zero or period point
#1000 : 8
PWM_CH5 up-count compared point
#1001 : 9
PWM_CH5 down-count compared point
#1010 : 10
PWM_CH0 up-count free trigger compared point
#1011 : 11
PWM_CH0 down-count free trigger compared point
#1100 : 12
PWM_CH2 up-count free trigger compared point
#1101 : 13
PWM_CH2 down-count free trigger compared point
#1110 : 14
PWM_CH4 up-count free trigger compared point
#1111 : 15
PWM_CH4 down-count free trigger compared point
End of enumeration elements list.
TRGEN5 : PWM_CH5 Trigger ADC enable bit
bits : 15 - 15 (1 bit)
access : read-write
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