\n
address_offset : 0x0 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
RTC Initiation Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT_ACTIVE : RTC Active Status (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
RTC is at reset state
#1 : 1
RTC is at normal active state
End of enumeration elements list.
INIT : RTC Initiation\nWhen RTC block is first powered on, RTC is at reset state. User has to write a special number 0xA5EB1357 to INIT to make RTC leaving reset state. Once the INIT is written as 0xA5EB1357 the RTC will be at normal active state permanently.\nThe INIT[31:1] is a write-only field and read value will be always 0.
bits : 1 - 31 (31 bit)
access : read-write
RTC Calendar Loading Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAY : 1-Day Calendar Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write
TENDAY : 10-Day Calendar Digit (0~3)
bits : 4 - 5 (2 bit)
access : read-write
MON : 1-Month Calendar Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write
TENMON : 10-Month Calendar Digit (0~1)
bits : 12 - 12 (1 bit)
access : read-write
YEAR : 1-Year Calendar Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write
TENYEAR : 10-Year Calendar Digit (0~9)
bits : 20 - 23 (4 bit)
access : read-write
RTC 32 KHz Oscillator Control Register
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GAIN : Oscillator Gain Option\nUser can select oscillator gain according to crystal external loading and operating temperature range. The larger gain value corresponding to stronger driving capability and higher power consumption.
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
#000 : 0
L0 mode
#001 : 1
L1 mode
#010 : 2
L2 mode
#011 : 3
L3 mode
#100 : 4
L4 mode
#101 : 5
L5 mode
#110 : 6
L6 mode
#111 : 7
L7 mode (Default)
End of enumeration elements list.
RTC X32KO Pin Control Register
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPMODE : I/O Pin Operation Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
X32KO (PF.0) is in Input mode without pull-up resistor
#01 : 1
X32KO (PF.0) is in Push-pull output mode
#10 : 2
X32KO (PF.0) is in Open-drain output mode
#11 : 3
X32KO (PF.0) is in Input mode with pull-up resistor
End of enumeration elements list.
DOUT : I/O Pin Output Data
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
X32KO (PF.0) will drive low in output mode
#1 : 1
X32KO (PF.0) will drive high in output mode
End of enumeration elements list.
CTLSEL : I/O Pin State Backup Selection\nWhen low speed 32 kHz oscillator (LXT) is disabled, X32KO pin can be used as GPIO PF.0 function. User can program CTLSEL to decide X32KO (PF.0) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTOCTL register.\nNote: CTLSEL will be set to 1 automatically by hardware when system power is turned off and RTC is at normal active state, ACTIVE (RTC_INIT[0]) is 1.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
X32KO (PF.0) pin I/O function is controlled by GPIO module
#1 : 1
X32KO (PF.0) pin I/O function is controlled by OPMODE and DOUT in RTC_LXTOCT at VBAT power domain
End of enumeration elements list.
RTC X32KI Pin Control Register
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPMODE : I/O Pin Operation Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
X32KI (PF.1) is in Input mode without pull-up resistor
#01 : 1
X32KI (PF.1) is in Push-pull output mode
#10 : 2
X32KI (PF.1) is in Open-drain output mode
#11 : 3
X32KI (PF.1) is in Input mode with pull-up resistor
End of enumeration elements list.
DOUT : IO Pin Output Data
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
X32KI (PF.1) will drive low in output mode
#1 : 1
X32KI (PF.1) will drive high in output mode
End of enumeration elements list.
CTLSEL : I/O Pin State Backup Selection\nWhen low speed 32 kHz oscillator (LXT) is disabled, X32KO pin can be used as GPIO PF.1 function. User can program CTLSEL to decide X32KI (PF.1) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL register.\nNote: CTLSEL will be set to 1 automatically by hardware when system power is turned off and RTC is at normal active state, ACTIVE (RTC_INIT[0]) is 1.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
X32KI (PF.1) pin I/O function is controlled by GPIO module
#1 : 1
X32KI (PF.1) pin I/O function is controlled by OPMODE and DOUT in RTC_LXTICTL at VBAT power domain
End of enumeration elements list.
RTC PF.2 Pin Control Register
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPMODE : I/O Pin Operation Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
PF.2 is in Input mode without pull-up resistor
#01 : 1
PF.2 is in Push-pull output mode
#10 : 2
PF.2 is in Open-drain output mode
#11 : 3
PF.2 is in Input mode with pull-up resistor
End of enumeration elements list.
DOUT : I/O Pin Output Data
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO PF.2 will drive low in output mode
#1 : 1
GPIO PF.2 will drive high in output mode
End of enumeration elements list.
CTLSEL : I/O Pin State Backup Selection\nUser can program CTLSEL to decide GPIO PF.2 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL register.\nNote: CTLSEL will be set to 1 automatically by hardware when system power is turned off and RTC is at normal active state, ACTIVE (RTC_INIT[0]) is 1.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO PF.2 pin I/O function is controlled by GPIO module
#1 : 1
GPIO PF.2 pin I/O function is controlled by OPMODE and DOUT in RTC_PF2CTL at VBAT power domain
End of enumeration elements list.
RTC Daylight Saving Time Control Register
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDHR : Add 1 Hour
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Indicates RTC hour digit has been added one hour for summer time change
End of enumeration elements list.
SUBHR : Subtract 1 Hour
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Indicates RTC hour digit has been subtracted one hour for winter time change
End of enumeration elements list.
DSBAK : Daylight Saving Back
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Daylight Saving Time function is not performed
#1 : 1
Daylight Saving Time function is performed
End of enumeration elements list.
RTC Time Scale Selection Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
_24HEN : 24-hour / 12-hour Time Scale Selection\nIndicates that RTC_TIME and RTC_TALM register are in 24-hour time scale or 12-hour time scale
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
12-hour time scale with AM and PM indication selected
#1 : 1
24-hour time scale selected
End of enumeration elements list.
RTC Day of the Week Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WEEKDAY : Day of the Week Register \nNote: RTC will not check WEEKDAY setting with RTC_CAL is reasonable or not.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Sunday
#001 : 1
Monday
#010 : 2
Tuesday
#011 : 3
Wednesday
#100 : 4
Thursday
#101 : 5
Friday
#110 : 6
Saturday
#111 : 7
Reserved.
End of enumeration elements list.
RTC Time Alarm Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC : 1-Sec Time Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write
TENSEC : 10-Sec Time Digit of Alarm Setting (0~5)
bits : 4 - 6 (3 bit)
access : read-write
MIN : 1-Min Time Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write
TENMIN : 10-Min Time Digit of Alarm Setting (0~5)
bits : 12 - 14 (3 bit)
access : read-write
HR : 1-Hour Time Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write
TENHR : 10-Hour Time Digit of Alarm Setting (0~2)When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
bits : 20 - 21 (2 bit)
access : read-write
RTC Calendar Alarm Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAY : 1-Day Calendar Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write
TENDAY : 10-Day Calendar Digit of Alarm Setting (0~3)
bits : 4 - 5 (2 bit)
access : read-write
MON : 1-Month Calendar Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write
TENMON : 10-Month Calendar Digit of Alarm Setting (0~1)
bits : 12 - 12 (1 bit)
access : read-write
YEAR : 1-Year Calendar Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write
TENYEAR : 10-Year Calendar Digit of Alarm Setting (0~9)
bits : 20 - 23 (4 bit)
access : read-write
RTC Leap Year Indicaton Register
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LEAPYEAR : Leap Year Indication Register (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
This year is not a leap year
#1 : 1
This year is leap year
End of enumeration elements list.
RTC Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALMIEN : Alarm Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC alarm interrupt Disabled
#1 : 1
RTC alarm interrupt Enabled
End of enumeration elements list.
TICKIEN : Time Tick Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC time tick interrupt Disabled
#1 : 1
RTC time tick interrupt Enabled
End of enumeration elements list.
RTC Interrupt Status Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALMIF : RTC Alarm Interrupt Flag\nWhen current RTC counter in RTC_TIME and RTC_CAL are matched RTC alarm settings in RTC_TALM and RTC_CALM, ALMIF will be set to 1 and an alarm interrupt signal will be generated if ALMIEN (RTC_INTEN[0]) is enabled. Chip will also be waken up when alarm interrupt signal occurred if chip is running at Power-down mode.\nNote: Writing 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Alarm condition is not matched
#1 : 1
Alarm condition is matched
End of enumeration elements list.
TICKIF : RTC Time Tick Interrupt Flag\nWhen RTC time tick event happened, TICKIF will be set to 1 and a time tick interrupt signal will be generated if TICKIEN (RTC_INTEN[1]) is enabled. Chip will also be waken up when time tick interrupt signal occurred if chip is running at Power-down mode.\nNote: Writing 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tick condition did not occur
#1 : 1
Tick condition occurred
End of enumeration elements list.
RTC Time Tick Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TICK : Time Tick Register\nThese bits are used to select RTC time tick period for periodic time tick interrupt request.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Time tick is 1 second
#001 : 1
Time tick is 1/2 second
#010 : 2
Time tick is 1/4 second
#011 : 3
Time tick is 1/8 second
#100 : 4
Time tick is 1/16 second
#101 : 5
Time tick is 1/32 second
#110 : 6
Time tick is 1/64 second
#111 : 7
Time tick is 1/128 second
End of enumeration elements list.
RTC Time Alarm Mask Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSEC : Mask 1-Sec Time Digit of alarm setting (0~9)
bits : 0 - 0 (1 bit)
access : read-write
MTENSEC : Mask 10-Sec Time Digit of alarm setting (0~5)
bits : 1 - 1 (1 bit)
access : read-write
MMIN : Mask 1-Min Time Digit of alarm setting (0~9)
bits : 2 - 2 (1 bit)
access : read-write
MTENMIN : Mask 10-Min Time Digit of alarm setting (0~5)
bits : 3 - 3 (1 bit)
access : read-write
MHR : Mask 1-hour Time Digit of Alarm Setting (0~9)\nNote: MHR function is only for 24-hour time scale mode.
bits : 4 - 4 (1 bit)
access : read-write
MTENHR : Mask 10-hour Time Digit of Alarm Setting (0~2)\nNote: MTENHR function is only for 24-hour time scale mode.
bits : 5 - 5 (1 bit)
access : read-write
RTC Calendar Alarm Mask Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDAY : Mask 1-Day Calendar Digit of alarm setting (0~9)
bits : 0 - 0 (1 bit)
access : read-write
MTENDAY : Mask 10-Day Calendar Digit of alarm setting (0~3)
bits : 1 - 1 (1 bit)
access : read-write
MMON : Mask 1-Month Calendar Digit of alarm setting (0~9)
bits : 2 - 2 (1 bit)
access : read-write
MTENMON : Mask 10-Month Calendar Digit of alarm setting (0~1)
bits : 3 - 3 (1 bit)
access : read-write
MYEAR : Mask 1-Year Calendar Digit of alarm setting (0~9)
bits : 4 - 4 (1 bit)
access : read-write
MTENYEAR : Mask 10-Year Calendar Digit of alarm setting (0~9)
bits : 5 - 5 (1 bit)
access : read-write
RTC Access Enable Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RWEN : RTC Register Access Enable Password (Write Only)\nWriting 0xA965 to this field will enable RTC register access period and keep 1024 RTC clocks.\nNote: Writing others vaule will clear RWENF and disable RTC register access function immediately.
bits : 0 - 15 (16 bit)
access : write-only
RWENF : RTC Register Access Enable Bit (Read Only)
Note1: This bit will be set after RWEN is load a 0xA965, and be cleared automatically after 1024 RTC clocks expired.
Note2: RWENF will be mask to 0 during RTCBUSY is 1, and first turn on RTCCKEN (CLK_APBCLK[1]) also.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
RTC register read/write Disabled
#1 : 1
RTC register read/write Enabled
End of enumeration elements list.
RTCBUSY : RTC Write Busy Flag\nThis bit indicates RTC registers are writable or not.\nNote: RTCBUSY falg will be set when execute write RTC register command exceed 6 times within 1120 PCLK cycles.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC register write Disabled
#1 : 1
RTC register write Enabled
End of enumeration elements list.
RTC Frequency Compensation Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQADJ : Frequency Compensation Value\nUser has to get actual clock frequency of LXT, LXT frequency.\nNote: This formula is suitable only when RTCSEL (CLK_CLKSEL2[18]) is 0, RTC clock source is from LXT.
bits : 0 - 21 (22 bit)
access : read-write
RTC Time Loading Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC : 1-Sec Time Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write
TENSEC : 10-Sec Time Digit (0~5)
bits : 4 - 6 (3 bit)
access : read-write
MIN : 1-Min Time Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write
TENMIN : 10-Min Time Digit (0~5)
bits : 12 - 14 (3 bit)
access : read-write
HR : 1-Hour Time Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write
TENHR : 10-hour Time Digit (0~2)\nNote: When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication, RTC_TIME[21] is 0 means AM hour and RTC_TIME[21] is 1 means PM hour.
bits : 20 - 21 (2 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.