Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x68 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x140 Bytes (0x0)
size : 0x58 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x19C Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
Timer0 Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
bits : 0 - 7 (8 bit)
access : read-write
INTRGEN : Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function.\nNote: For Timer1/3, this bit is ignored and the read back value is always 0.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inter-Timer Trigger Capture mode Disabled
#1 : 1
Inter-Timer Trigger Capture mode Enabled
End of enumeration elements list.
PERIOSEL : Periodic Mode Behavior Selection Enable Bit
If the updated CMPDAT value CNT, CNT will be reset to default value.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
The behavior selection in periodic mode Disabled
#1 : 1
The behavior selection in periodic mode Enabled
End of enumeration elements list.
TGLPINSEL : Toggle-output Pin Select
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Toggle mode output to Tx (Timer Event Counter Pin)
#1 : 1
Toggle mode output to Tx_EXT (Timer External Capture Pin)
End of enumeration elements list.
CAPSRC : Capture Pin Source Selection
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture Function source is from Tx_EXT (x= 0~3) pin
#1 : 1
Capture Function source is from internal ACMP output signal. User can set ACMPSSEL (TIMERx_EXTCTL[8]) to decide which internal ACMP output signal as timer capture source
End of enumeration elements list.
WKEN : Wake-up Function Enable Bit\nIf this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake-up function Disabled if timer interrupt signal generated
#1 : 1
Wake-up function Enabled if timer interrupt signal generated
End of enumeration elements list.
EXTCNTEN : Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Event counter mode Disabled
#1 : 1
Event counter mode Enabled
End of enumeration elements list.
ACTSTS : Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
24-bit up counter is not active
#1 : 1
24-bit up counter is active
End of enumeration elements list.
OPMODE : Timer Counting Mode Select
bits : 27 - 28 (2 bit)
access : read-write
Enumeration:
#00 : 0
The Timer controller is operated in One-shot mode
#01 : 1
The Timer controller is operated in Periodic mode
#10 : 2
The Timer controller is operated in Toggle-output mode
#11 : 3
The Timer controller is operated in Continuous Counting mode
End of enumeration elements list.
INTEN : Timer Interrupt Enable Bit\nNote: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer time-out interrupt Disabled
#1 : 1
Timer time-out interrupt Enabled
End of enumeration elements list.
CNTEN : Timer Counting Enable Bit\nNote3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enabe/disable command is completed or not.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stop/Suspend counting
#1 : 1
Start counting
End of enumeration elements list.
ICEDEBUG : ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode acknowledgement effects TIMER counting
#1 : 1
ICE debug mode acknowledgement Disabled
End of enumeration elements list.
Timer0 Capture Data Register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPDAT : Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
bits : 0 - 23 (24 bit)
access : read-only
Timer1 Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 Comparator Register
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 Interrupt Status Register
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 Data Register
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 Capture Data Register
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 External Control Register
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 External Interrupt Status Register
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 Trigger Control Register
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 Alternative Control Register
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer0 External Control Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTPHASE : Timer External Count Phase
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
A falling edge of external counting pin will be counted
#1 : 1
A rising edge of external counting pin will be counted
End of enumeration elements list.
CAPEN : Timer External Capture Pin Enable Bit\nThis bit enables the Tx_EXT capture pin input function.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tx_EXT (x= 0~3) pin Disabled
#1 : 1
Tx_EXT (x= 0~3) pin Enabled
End of enumeration elements list.
CAPFUNCS : Capture Function Selection
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
External Capture Mode Enabled
#1 : 1
External Reset Mode Enabled
End of enumeration elements list.
CAPIEN : Timer External Capture Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tx_EXT (x= 0~3) pin detection Interrupt Disabled
#1 : 1
Tx_EXT (x= 0~3) pin detection Interrupt Enabled
End of enumeration elements list.
CAPDBEN : Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of Tx_EXT pin or ACMP output is detected with de-bounce circuit.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled
#1 : 1
Tx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled
End of enumeration elements list.
CNTDBEN : Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of Tx pin is detected with de-bounce circuit.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tx (x= 0~3) pin de-bounce Disabled
#1 : 1
Tx (x= 0~3) pin de-bounce Enabled
End of enumeration elements list.
ACMPSSEL : ACMP Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture Function source is from internal ACMP0 output signal
#1 : 1
Capture Function source is from internal ACMP1 output signal
End of enumeration elements list.
CAPEDGE : Timer External Capture Pin Edge Detect\nWhen first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Capture event occurred when detect falling edge transfer on Tx_EXT (x= 0~3) pin
#001 : 1
Capture event occurred when detect rising edge transfer on Tx_EXT (x= 0~3) pin
#010 : 2
Capture event occurred when detect both falling and rising edge transfer on Tx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer
#011 : 3
Capture event occurred when detect both rising and falling edge transfer on Tx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer.
#110 : 6
First capture event occurred at falling edge, follows capture events are at rising edge transfer on Tx_EXT (x= 0~3) pin
#111 : 7
First capture event occurred at rising edge, follows capture events are at falling edge transfer on Tx_EXT (x= 0~3) pin
End of enumeration elements list.
ECNTSSEL : Event Counter Source Selection to Trigger Event Counter Function
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Event Counter input source is from Tx (x= 0~3) pin
#1 : 1
Reserved.
End of enumeration elements list.
Timer1 PWM Control Register
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM Counter Clock Source Register
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM Counter Clock Pre-scale Register
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM Clear Counter Register
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM Period Register
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM Comparator Register
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM Dead-time Control Register
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM Counter Register
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM Output Mask Enable Register
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM Output Mask Data Control Register
address_offset : 0x164 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM Brake Pin Noise Filter Register
address_offset : 0x168 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM System Fail Brake Control Register
address_offset : 0x16C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM Brake Control Register
address_offset : 0x170 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM Pin Output Polar Control Register
address_offset : 0x174 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM Pin Output Enable Register
address_offset : 0x178 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM Software Trigger Brake Control Register
address_offset : 0x17C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer0 External Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPIF : Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tx_EXT (x= 0~3) pin interrupt did not occur
#1 : 1
Tx_EXT (x= 0~3) pin interrupt occurred
End of enumeration elements list.
Timer1 PWM Interrupt Enable Register 0
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM Interrupt Enable Register 1
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM Interrupt Status Register 0
address_offset : 0x188 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM Interrupt Status Register 1
address_offset : 0x18C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM ADC Trigger Source Select Register
address_offset : 0x190 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM Synchronous Control Register
address_offset : 0x194 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM Status Register
address_offset : 0x19C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM Period Buffer Register
address_offset : 0x1A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 PWM Comparator Buffer Register
address_offset : 0x1A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer0 Trigger Control Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSSEL : Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time-out interrupt signal is used to internal trigger PWM, PDMA, and ADC
#1 : 1
Capture interrupt signal is used to internal trigger PWM, PDMA, and ADC
End of enumeration elements list.
TRGPWM : Trigger PWM Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be as PWM counter clock source.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer interrupt trigger PWM Disabled
#1 : 1
Timer interrupt trigger PWM Enabled
End of enumeration elements list.
TRGADC : Trigger ADC Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be triggered ADC conversion.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer interrupt trigger ADC Disabled
#1 : 1
Timer interrupt trigger ADC Enabled
End of enumeration elements list.
TRGPDMA : Trigger PDMA Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer interrupt trigger PDMA Disabled
#1 : 1
Timer interrupt trigger PDMA Enabled
End of enumeration elements list.
Timer0 Alternative Control Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FUNCSEL : Function Selection\nNote: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer controller is used as timer function
#1 : 1
Timer controller is used as PWM function
End of enumeration elements list.
Timer0 Comparator Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPDAT : Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
bits : 0 - 23 (24 bit)
access : read-write
Timer0 PWM Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTEN : PWM Counter Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM counter and clock prescale Stop Running
#1 : 1
PWM counter and clock prescale Start Running
End of enumeration elements list.
CNTTYPE : PWM Counter Behavior Type
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up count type
#01 : 1
Down count type
#10 : 2
Up-down count type
#11 : 3
Reserved.
End of enumeration elements list.
CNTMODE : PWM Counter Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-reload mode
#1 : 1
One-shot mode
End of enumeration elements list.
CTRLD : Center Re-load\nIn up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period.
bits : 8 - 8 (1 bit)
access : read-write
IMMLDEN : Immediately Load Enable Bit\nNote: If IMMLDEN is enabled, CTRLD will be invalid.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled. If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period
#1 : 1
PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP
End of enumeration elements list.
OUTMODE : PWM Output Mode\nThis bit controls the output mode of corresponding PWM channel.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM independent mode
#1 : 1
PWM complementary mode
End of enumeration elements list.
DBGHALT : ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. \nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode counter halt Disabled
#1 : 1
ICE debug mode counter halt Enabled
End of enumeration elements list.
DBGTRIOFF : ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode acknowledgement effects PWM output
#1 : 1
ICE debug mode acknowledgement Disabled
End of enumeration elements list.
Timer0 PWM Counter Clock Source Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSRC : PWM Counter Clock Source Select\nThe PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event.\nNote: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
TMRx_CLK
#001 : 1
Internal TIMER0 time-out or capture event
#010 : 2
Internal TIMER1 time-out or capture event
#011 : 3
Internal TIMER2 time-out or capture event
#100 : 4
Internal TIMER3 time-out or capture event
End of enumeration elements list.
Timer0 PWM Counter Clock Pre-scale Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKPSC : PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0, then there is no scaling in PWM counter clock source.
bits : 0 - 11 (12 bit)
access : read-write
Timer0 PWM Clear Counter Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTCLR : Clear PWM Counter Control Bit\nIt is automatically cleared by hardware.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type
End of enumeration elements list.
Timer0 PWM Period Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD, and restarts from 0.\nIn down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD.\nIn up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.\nIn up and down count type:\nNote: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type.
bits : 0 - 15 (16 bit)
access : read-write
Timer0 PWM Comparator Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP : PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger ADC to start convert.
bits : 0 - 15 (16 bit)
access : read-write
Timer0 PWM Dead-time Control Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCNT : Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following two formulas: \nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 11 (12 bit)
access : read-write
DTEN : Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect)\nDead-time insertion function is only active when PWM complementary mode is enabled. If dead- time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay.\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-time insertion Disabled on the pin pair
#1 : 1
Dead-time insertion Enabled on the pin pair
End of enumeration elements list.
DTCKSEL : Dead-time Clock Select (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-time clock source from TMRx_PWMCLK without counter clock prescale
#1 : 1
Dead-time clock source from TMRx_PWMCLK with counter clock prescale
End of enumeration elements list.
Timer0 PWM Counter Register
address_offset : 0x5C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter.
bits : 0 - 15 (16 bit)
access : read-only
DIRF : PWM Counter Direction Indicator Flag (Read Only)
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Counter is active in down counting
#1 : 1
Counter is active in up counting
End of enumeration elements list.
Timer0 PWM Output Mask Enable Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSKEN0 : PWMx_CH0 Output Mask Enable Bit\nThe PWMx_CH0 output signal will be masked when this bit is enabled. The PWMx_CH0 will output MSKDAT0 (TIMER_PWMMSK[0]) data.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CH0 output signal is non-masked
#1 : 1
PWMx_CH0 output signal is masked and output MSKDAT0 data
End of enumeration elements list.
MSKEN1 : PWMx_CH1 Output Mask Enable Bit\nThe PWMx_CH1 output signal will be masked when this bit is enabled. The PWMx_CH1 will output MSKDAT1 (TIMER_PWMMSK[1]) data.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CH1 output signal is non-masked
#1 : 1
PWMx_CH1 output signal is masked and output MSKDAT1 data
End of enumeration elements list.
Timer0 PWM Output Mask Data Control Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSKDAT0 : PWMx_CH0 Output Mask Data Control Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic Low to PWMx_CH0
#1 : 1
Output logic High to PWMx_CH0
End of enumeration elements list.
MSKDAT1 : PWMx_CH1 Output Mask Data Control Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic Low to PWMx_CH1
#1 : 1
Output logic High to PWMx_CH1
End of enumeration elements list.
Timer0 PWM Brake Pin Noise Filter Register
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKNFEN : Brake Pin Noise Filter Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin noise filter detect of TM_BRAKEx Disabled
#1 : 1
Pin noise filter detect of TM_BRAKEx Enabled
End of enumeration elements list.
BRKNFSEL : Brake Pin Noise Filter Clock Selection
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
#000 : 0
Noise filter clock is PCLKx
#001 : 1
Noise filter clock is PCLKx/2
#010 : 2
Noise filter clock is PCLKx/4
#011 : 3
Noise filter clock is PCLKx/8
#100 : 4
Noise filter clock is PCLKx/16
#101 : 5
Noise filter clock is PCLKx/32
#110 : 6
Noise filter clock is PCLKx/64
#111 : 7
Noise filter clock is PCLKx/128
End of enumeration elements list.
BRKFCNT : Brake Pin Noise Filter Count\nThe fields is used to control the active noise filter sample time.
bits : 4 - 6 (3 bit)
access : read-write
BRKPINV : Brake Pin Detection Control Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake pin event will be detected if TM_BRAKEx pin status transfer from low to high in edge-detect, or pin status is high in level-detect
#1 : 1
Brake pin event will be detected if TM_BRAKEx pin status transfer from high to low in edge-detect, or pin status is low in level-detect
End of enumeration elements list.
BKPINSRC : Brake Pin Source Select
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Brake pin source comes from TM_BRAKE0
#01 : 1
Brake pin source comes from TM_BRAKE1
#10 : 2
Brake pin source comes from TM_BRAKE2
#11 : 3
Brake pin source comes from TM_BRAKE3
End of enumeration elements list.
Timer0 PWM System Fail Brake Control Register
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSSBRKEN : Clock Security System Detection Trigger PWM Brake Function Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function triggered by clock fail detection Disabled
#1 : 1
Brake Function triggered by clock fail detection Enabled
End of enumeration elements list.
BODBRKEN : Brown-out Detection Trigger PWM Brake Function Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function triggered by BOD event Disabled
#1 : 1
Brake Function triggered by BOD event Enabled
End of enumeration elements list.
CORBRKEN : Core Lockup Detection Trigger PWM Brake Function Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function triggered by core lockup event Disabled
#1 : 1
Brake Function triggered by core lockup event Enabled
End of enumeration elements list.
Timer0 PWM Brake Control Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPO0EBEN : Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This register is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal ACMP0_O signal as edge-detect brake source Disabled
#1 : 1
Internal ACMP0_O signal as edge-detect brake source Enabled
End of enumeration elements list.
CPO1EBEN : Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote2: This register is write protected. Refer to SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal ACMP1_O signal as edge-detect brake source Disabled
#1 : 1
Internal ACMP1_O signal as edge-detect brake source Enabled
End of enumeration elements list.
BRKPEEN : Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
TM_BRAKEx pin event as edge-detect brake source Disabled
#1 : 1
TM_BRAKEx pin event as edge-detect brake source Enabled
End of enumeration elements list.
SYSEBEN : Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
System fail condition as edge-detect brake source Disabled
#1 : 1
System fail condition as edge-detect brake source Enabled
End of enumeration elements list.
CPO0LBEN : Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP0_O signal from low to high will be detected as brake event.\nNote2: This register is write protected. Refer to SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal ACMP0_O signal as level-detect brake source Disabled
#1 : 1
Internal ACMP0_O signal as level-detect brake source Enabled
End of enumeration elements list.
CPO1LBEN : Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote1: Only internal ACMP1_O signal from low to high will be detected as brake event.\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal ACMP1_O signal as level-detect brake source Disabled
#1 : 1
Internal ACMP1_O signal as level-detect brake source Enabled
End of enumeration elements list.
BRKPLEN : Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
TM_BRAKEx pin event as level-detect brake source Disabled
#1 : 1
TM_BRAKEx pin event as level-detect brake source Enabled
End of enumeration elements list.
SYSLBEN : Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
System fail condition as level-detect brake source Disabled
#1 : 1
System fail condition as level-detect brake source Enabled
End of enumeration elements list.
BRKAEVEN : PWM Brake Action Select for PWMx_CH0 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
TIMERx_PWM brake event will not affect PWMx_CH0 output
#01 : 1
PWMx_CH0 output tri-state when TIMERx_PWM brake event happened
#10 : 2
PWMx_CH0 output low level when TIMERx_PWM brake event happened
#11 : 3
PWMx_CH0 output high level when TIMERx_PWM brake event happened
End of enumeration elements list.
BRKAODD : PWM Brake Action Select for PWMx_CH1 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
TIMERx_PWM brake event will not affect PWMx_CH1 output
#01 : 1
PWMx_CH1 output tri-state when TIMERx_PWM brake event happened
#10 : 2
PWMx_CH1 output low level when TIMERx_PWM brake event happened
#11 : 3
PWMx_CH1 output high level when TIMERx_PWM brake event happened
End of enumeration elements list.
Timer0 PWM Pin Output Polar Control Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PINV0 : PWMx_CH0 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH0 output pin.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CH0 output pin polar inverse Disabled
#1 : 1
PWMx_CH0 output pin polar inverse Enabled
End of enumeration elements list.
PINV1 : PWMx_CH1 Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_CH1 output pin.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CH1 output pin polar inverse Disabled
#1 : 1
PWMx_CH1 output pin polar inverse Enabled
End of enumeration elements list.
Timer0 PWM Pin Output Enable Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POEN0 : PWMx_CH0 Output Pin Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CH0 pin at tri-state mode
#1 : 1
PWMx_CH0 pin in output mode
End of enumeration elements list.
POEN1 : PWMx_CH1 Output Pin Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CH1 pin at tri-state mode
#1 : 1
PWMx_CH1 pin in output mode
End of enumeration elements list.
Timer0 PWM Software Trigger Brake Control Register
address_offset : 0x7C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BRKETRG : Software Trigger Edge-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. \nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : write-only
BRKLTRG : Software Trigger Level-detect Brake Source (Write Only) (Write Protect)\nWrite 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. \nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : write-only
Timer0 Interrupt Status Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIF : Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
CNT value matches the CMPDAT value
End of enumeration elements list.
TWKF : Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer does not cause CPU wake-up
#1 : 1
CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated
End of enumeration elements list.
Timer0 PWM Interrupt Enable Register 0
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZIEN : PWM Zero Point Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
PIEN : PWM Period Point Interrupt Enable Bit\nNote: In up-down count type, period point means the center point of current PWM period.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
CMPUIEN : PWM Compare Up Count Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPDIEN : PWM Compare Down Count Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
Timer0 PWM Interrupt Enable Register 1
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKEIEN : PWM Edge-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM edge-detect brake interrupt Disabled
#1 : 1
PWM edge-detect brake interrupt Enabled
End of enumeration elements list.
BRKLIEN : PWM Level-detect Brake Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM level-detect brake interrupt Disabled
#1 : 1
PWM level-detect brake interrupt Enabled
End of enumeration elements list.
Timer0 PWM Interrupt Status Register 0
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZIF : PWM Zero Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches zero.\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
PIF : PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote1: When in up-down count type, PIF flag means the center point flag of current PWM period.\nNote2: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
CMPUIF : PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type..\nNote2: This bit is cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write
CMPDIF : PWM Compare Down Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP.\nNote1: If CMP equal to PERIOD, there is no CMPDIF flag in down count type.\nNote2: This bit is cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write
Timer0 PWM Interrupt Status Register 1
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKEIF0 : Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CH0 edge-detect brake event did not happen
#1 : 1
PWMx_CH0 edge-detect brake event happened
End of enumeration elements list.
BRKEIF1 : Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected. Refer to SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CH1 edge-detect brake event did not happen
#1 : 1
PWMx_CH1 edge-detect brake event happened
End of enumeration elements list.
BRKLIF0 : Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected. Refer to SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CH0 level-detect brake event did not happen
#1 : 1
PWMx_CH0 level-detect brake event happened
End of enumeration elements list.
BRKLIF1 : Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect)\nNote1: This bit is cleared by writing 1 to it.\nNote2: This register is write protected. Refer to SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_CH1 level-detect brake event did not happen
#1 : 1
PWMx_CH1 level-detect brake event happened
End of enumeration elements list.
BRKESTS0 : Edge -detect Brake Status of PWMx_CH0 (Read Only)\nNote: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWMx_CH0 edge-detect brake state is released
#1 : 1
PWMx_CH0 at edge-detect brake state
End of enumeration elements list.
BRKESTS1 : Edge-detect Brake Status of PWMx_CH1 (Read Only)\nNote: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWMx_CH1 edge-detect brake state is released
#1 : 1
PWMx_CH1 at edge-detect brake state
End of enumeration elements list.
BRKLSTS0 : Level-detect Brake Status of PWMx_CH0 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period.
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWMx_CH0 level-detect brake state is released
#1 : 1
PWMx_CH0 at level-detect brake state
End of enumeration elements list.
BRKLSTS1 : Level-detect Brake Status of PWMx_CH1 (Read Only)\nNote: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period.
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWMx_CH1 level-detect brake state is released
#1 : 1
PWMx_CH1 at level-detect brake state
End of enumeration elements list.
Timer0 PWM ADC Trigger Source Select Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL : PWM Counter Event Source Select to Trigger ADC Conversion
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Trigger ADC conversion at zero point (ZIF)
#001 : 1
Trigger ADC conversion at period point (PIF)
#010 : 2
Trigger ADC conversion at zero or period point (ZIF or PIF)
#011 : 3
Trigger ADC conversion at compare up count point (CMPUIF)
#100 : 4
Trigger ADC conversion at compare down count point (CMPDIF)
End of enumeration elements list.
TRGEN : PWM Counter Event Trigger ADC Conversion Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM counter event trigger ADC conversion Disabled
#1 : 1
PWM counter event trigger ADC conversion Enabled
End of enumeration elements list.
Timer0 PWM Synchronous Control Register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCMODE : PWM Synchronous Mode Enable Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
PWM synchronous function Disabled
#01 : 1
PWM synchronous counter start function Enabled
#10 : 2
Reserved.
#11 : 3
PWM synchronous counter clear function Enabled
End of enumeration elements list.
SYNCSRC : PWM Synchronous Counter Start/Clear Source Select\nNote1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIME0_PWMSCTL[8], TIME1_PWMSCTL[8], TIME2_PWMSCTL[8] and TIME3_PWMSCTL[8] should be 0.\nNote2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIME0_PWMSCTL[8] and TIME1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIME3_PWMSCTL[8] should be set 1.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN
#1 : 1
Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN
End of enumeration elements list.
Timer0 PWM Synchronous Trigger Register
address_offset : 0x98 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
STRGEN : PWM Counter Synchronous Trigger Enable Bit (Write Only)\nPMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting.\nNote: This bit is only available in TIMER0 and TIMER2.
bits : 0 - 0 (1 bit)
access : write-only
Timer0 PWM Status Register
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTMAXF : PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM counter value never reached its maximum value 0xFFFF
#1 : 1
PWM counter value has reached its maximum value
End of enumeration elements list.
ADCTRGF : Trigger ADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM counter event trigger ADC start conversion has not occurred
#1 : 1
PWM counter event trigger ADC start conversion has occurred
End of enumeration elements list.
Timer0 PWM Period Buffer Register
address_offset : 0xA0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PBUF : PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register.
bits : 0 - 15 (16 bit)
access : read-only
Timer0 PWM Comparator Buffer Register
address_offset : 0xA4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMPBUF : PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register.
bits : 0 - 15 (16 bit)
access : read-only
Timer0 Data Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Timer Data Register\nRead operation:\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24-bit event input counter value.\nWrite operation:\nWriting any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter.
bits : 0 - 23 (24 bit)
access : read-write
RSTACT : Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress. Once the counter reset operation done, timer clear this bit to 0 automatically.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Reset operation is done
#1 : 1
Reset operation triggered by writing TIMERx_CNT is in progress
End of enumeration elements list.
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