UI2C_CTL

UI2C_LINECTL

UI2C_TXDAT

UI2C_RXDAT

UI2C_DEVADDR0

UI2C_DEVADDR1

UI2C_ADDRMSK0

UI2C_ADDRMSK1

UI2C_WKCTL

UI2C_WKSTS

UI2C_PROTCTL

UI2C_PROTIEN

UI2C_PROTSTS

UI2C_BRGEN

UI2C_ADMAT

UI2C_TMCTL

FUNMODE : Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

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LSB : LSB First Transmission Selection
bits : 0 - 0 (1 bit)
access : read-write

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DWIDTH : Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].\nNote: In I2C protocol, the length must be configured as 8 bits.
bits : 8 - 11 (4 bit)
access : read-write

TXDAT : Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission.
bits : 0 - 15 (16 bit)
access : write-only

RXDAT : Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote 1: In I2C protocol, only use RXDAT[7:0]..
bits : 0 - 15 (16 bit)
access : read-only

DEVADDR : Device Address\nIn I2C protocol, this bit field contains the programmed slave address. If the first received address byte is b1111 0AAX, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0].\nNote: When I2C operating in 7-bit address mode, only use DEVADDR[6:0]
bits : 0 - 9 (10 bit)
access : read-write

ADDRMSK : USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
bits : 0 - 9 (10 bit)
access : read-write

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WKEN : Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

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WKADDREN : Wake-up Address Match Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

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WKF : Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

GCFUNC : General Call Function
bits : 0 - 0 (1 bit)
access : read-write

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AA : Assert Acknowledge Control
bits : 1 - 1 (1 bit)
access : read-write

STO : I2C STOP Control
bits : 2 - 2 (1 bit)
access : read-write

STA : I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
bits : 3 - 3 (1 bit)
access : read-write

ADDR10EN : Address 10-bit Function Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

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PTRG : I2C Protocol Trigger\nWhen a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.
bits : 5 - 5 (1 bit)
access : read-write

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SCLOUTEN : SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt.
bits : 8 - 8 (1 bit)
access : read-write

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MONEN : Monitor Mode Enable Bit\nThis bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.\nNote: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line.
bits : 9 - 9 (1 bit)
access : read-write

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TOCNT : Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode.
bits : 16 - 25 (10 bit)
access : read-write

PROTEN : I2C Protocol Enable Bit
bits : 31 - 31 (1 bit)
access : read-write

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TOIEN : Time-out Interrupt Enable Control\nIn I2C protocol, this bit enables the interrupt generation in case of a time-out event.
bits : 0 - 0 (1 bit)
access : read-write

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STARIEN : Start Condition Received Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a start condition is detected.
bits : 1 - 1 (1 bit)
access : read-write

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STORIEN : Stop Condition Received Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a stop condition is detected.
bits : 2 - 2 (1 bit)
access : read-write

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NACKIEN : Non - Acknowledge Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master.
bits : 3 - 3 (1 bit)
access : read-write

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ARBLOIEN : Arbitration Lost Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected.
bits : 4 - 4 (1 bit)
access : read-write

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ERRIEN : Error Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])).
bits : 5 - 5 (1 bit)
access : read-write

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ACKIEN : Acknowledge Interrupt Enable Control\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
bits : 6 - 6 (1 bit)
access : read-write

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TOIF : Time-out Interrupt Flag\nNote: It is cleared by software writing one into this bit
bits : 5 - 5 (1 bit)
access : read-write

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ONBUSY : On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected
bits : 6 - 6 (1 bit)
access : read-write

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STARIF : Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode.\nIt is cleared by software writing one into this bit
bits : 8 - 8 (1 bit)
access : read-write

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STORIF : Stop Condition Received Interrupt Flag\nIt is cleared by software writing one into this bit
bits : 9 - 9 (1 bit)
access : read-write

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NACKIF : Non - Acknowledge Received Interrupt Flag\nIt is cleared by software writing one into this bit
bits : 10 - 10 (1 bit)
access : read-write

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ARBLOIF : Arbitration Lost Interrupt Flag\nIt is cleared by software writing one into this bit
bits : 11 - 11 (1 bit)
access : read-write

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ERRIF : Error Interrupt Flag\nIt is cleared by software writing one into this bit\nNote: This bit is set when slave mode, user must write one into STO register to the defined 'not addressed' slave mode.
bits : 12 - 12 (1 bit)
access : read-write

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ACKIF : Acknowledge Received Interrupt Flag\nIt is cleared by software writing one into this bit
bits : 13 - 13 (1 bit)
access : read-write

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SLASEL : Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
bits : 14 - 14 (1 bit)
access : read-write

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SLAREAD : Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
bits : 15 - 15 (1 bit)
access : read-write

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WKAKDONE : Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKUPIF is set.
bits : 16 - 16 (1 bit)
access : read-write

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WRSTSWK : Read/Write Status Bit in Address Wakeup Frame
bits : 17 - 17 (1 bit)
access : read-write

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BUSHANG : Bus Hang-up\nThis bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL signal.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
bits : 18 - 18 (1 bit)
access : read-write

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ERRARBLO : Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
bits : 19 - 19 (1 bit)
access : read-write

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RCLKSEL : Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK).
bits : 0 - 0 (1 bit)
access : read-write

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PTCLKSEL : Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK).
bits : 1 - 1 (1 bit)
access : read-write

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SPCLKSEL : Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
bits : 2 - 3 (2 bit)
access : read-write

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TMCNTEN : Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.
bits : 4 - 4 (1 bit)
access : read-write

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TMCNTSRC : Time Measurement Counter Clock Source Selection
bits : 5 - 5 (1 bit)
access : read-write

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PDSCNT : Pre-divider for Sample Counter
bits : 8 - 9 (2 bit)
access : read-write

DSCNT : Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
bits : 10 - 14 (5 bit)
access : read-write

CLKDIV : Clock Divider\nNote: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UI2C_PROTCTL[24:16]) to calculate the precise baud rate.
bits : 16 - 25 (10 bit)
access : read-write

ADMAT0 : USCI Address 0 Match Status Register\nWhen address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

ADMAT1 : USCI Address 1 Match Status Register\nWhen address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

STCTL : Setup Time Configure Control Register\nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode..
bits : 0 - 5 (6 bit)
access : read-write

HTCTL : Hold Time Configure Control Register\nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode.
bits : 6 - 11 (6 bit)
access : read-write