Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1EC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x24 Bytes (0x0)
size : 0x4C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xDC Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1F8 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
Part Device Identification Number Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDID : Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only
Peripheral Reset Control Register 2
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SC0RST : SC0 Controller Reset
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SC0 controller normal operation
#1 : 1
SC0 controller reset
End of enumeration elements list.
SC1RST : SC1 Controller Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
SC1 controller normal operation
#1 : 1
SC1 controller reset
End of enumeration elements list.
SC2RST : SC2 Controller Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
SC2 controller normal operation
#1 : 1
SC2 controller reset
End of enumeration elements list.
SPI3RST : SPI3 Controller Reset
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI3 controller normal operation
#1 : 1
SPI3 controller reset
End of enumeration elements list.
USCI0RST : USCI0 Controller Reset
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
USCI0 controller normal operation
#1 : 1
USCI0 controller reset
End of enumeration elements list.
USCI1RST : USCI1 Controller Reset
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
USCI1 controller normal operation
#1 : 1
USCI1 controller reset
End of enumeration elements list.
DACRST : DAC Controller Reset
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC controller normal operation
#1 : 1
DAC controller reset
End of enumeration elements list.
EPWM0RST : EPWM0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM0 controller normal operation
#1 : 1
EPWM0 controller reset
End of enumeration elements list.
EPWM1RST : EPWM1 Controller Reset
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM1 controller normal operation
#1 : 1
EPWM1 controller reset
End of enumeration elements list.
BPWM0RST : BPWM0 Controller Reset
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM0 controller normal operation
#1 : 1
BPWM0 controller reset
End of enumeration elements list.
BPWM1RST : BPWM1 Controller Reset
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM1 controller normal operation
#1 : 1
BPWM1 controller reset
End of enumeration elements list.
QEI0RST : QEI0 Controller Reset
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
QEI0 controller normal operation
#1 : 1
QEI0 controller reset
End of enumeration elements list.
QEI1RST : QEI1 Controller Reset
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
QEI1 controller normal operation
#1 : 1
QEI1 controller reset
End of enumeration elements list.
ECAP0RST : ECAP0 Controller Reset
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
ECAP0 controller normal operation
#1 : 1
ECAP0 controller reset
End of enumeration elements list.
ECAP1RST : ECAP1 Controller Reset
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
ECAP1 controller normal operation
#1 : 1
ECAP1 controller reset
End of enumeration elements list.
Register Lock Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGLCTL : Register Lock Control Code \nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h', '16h', '88h' to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.\n\nREGLCTL[0]\nRegister Lock Control Disable Index
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : 0
Write-protection Enabled for writing protected registers. Any write to the protected register is ignored
1 : 1
Write-protection Disabled for writing protected registers
End of enumeration elements list.
Brown-out Detector Control Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BODEN : Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector function Disabled
#1 : 1
Brown-out Detector function Enabled
End of enumeration elements list.
BODRSTEN : Brown-out Reset Enable Bit (Write Protect)
The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit .
Note1:
While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if AVDD.than BODVL, BOD interrupt will keep till to the BODIF set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out 'INTERRUPT' function Enabled
#1 : 1
Brown-out 'RESET' function Enabled
End of enumeration elements list.
BODIF : Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting
#1 : 1
When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled
End of enumeration elements list.
BODLPM : Brown-out Detector Low Power Mode (Write Protect)\nNote1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
BOD operate in normal mode (default)
#1 : 1
BOD Low Power mode Enabled
End of enumeration elements list.
BODOUT : Brown-out Detector Output Status\nIt means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled, this bit always responds 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector output status is 0
#1 : 1
Brown-out Detector output status is 1
End of enumeration elements list.
LVREN : Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote1: After enabling the bit, the LVR function will be active with 200us delay for LVR output stable (default).\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low Voltage Reset function Disabled
#1 : 1
Low Voltage Reset function Enabled
End of enumeration elements list.
BODDGSEL : Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
BOD output is sampled by LIRC clock
#001 : 1
4 system clock (HCLK)
#010 : 2
8 system clock (HCLK)
#011 : 3
16 system clock (HCLK)
#100 : 4
32 system clock (HCLK)
#101 : 5
64 system clock (HCLK)
#110 : 6
128 system clock (HCLK)
#111 : 7
256 system clock (HCLK)
End of enumeration elements list.
LVRDGSEL : LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Without de-glitch function
#001 : 1
4 system clock (HCLK)
#010 : 2
8 system clock (HCLK)
#011 : 3
16 system clock (HCLK)
#100 : 4
32 system clock (HCLK)
#101 : 5
64 system clock (HCLK)
#110 : 6
128 system clock (HCLK)
#111 : 7
256 system clock (HCLK)
End of enumeration elements list.
BODVL : Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by flash controller user configuration register CBOV (CONFIG0 [23:21]).\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
Brown-out Detector threshold voltage is 1.6V
#001 : 1
Brown-out Detector threshold voltage is 1.8V
#010 : 2
Brown-out Detector threshold voltage is 2.0V
#011 : 3
Brown-out Detector threshold voltage is 2.2V
#100 : 4
Brown-out Detector threshold voltage is 2.4V
#101 : 5
Brown-out Detector threshold voltage is 2.6V
#110 : 6
Brown-out Detector threshold voltage is 2.8V
#111 : 7
Brown-out Detector threshold voltage is 3.0V
End of enumeration elements list.
Internal Voltage Source Control Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTEMPEN : Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result. Please refer to ADC function chapter for details.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Temperature sensor function Disabled (default)
#1 : 1
Temperature sensor function Enabled
End of enumeration elements list.
VBATUGEN : VBAT Unity Gain Buffer Enable Bit\nThis bit is used to enable/disable VBAT unity gain buffer function.\nNote: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
VBAT unity gain buffer function Disabled (default)
#1 : 1
VBAT unity gain buffer function Enabled
End of enumeration elements list.
Power-on Reset Controller Register 1
address_offset : 0x1EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POROFF : Power-on Reset Enable Bit (Write Protect)
When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.
Note: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 15 (16 bit)
access : read-write
Power Level Control Register
address_offset : 0x1F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSEL : Power Level Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Set to Power level 0 (PL0)
#01 : 1
Set to Power level 1 (PL1)
End of enumeration elements list.
MVRS : Main Voltage Regulator Type Select (Write Protect)\nThis bit filed sets main voltage regulator type.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set main voltage regulator to LDO
#1 : 1
Set main voltage regulator to DCDC
End of enumeration elements list.
LVSSTEP : LDO Voltage Scaling Step (Write Protect)\nThe LVSSTEP value is LDO voltage rising step.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 21 (6 bit)
access : read-write
LVSPRD : LDO Voltage Scaling Period (Write Protect)\nThe LVSPRD value is the period of each LDO voltage rising step.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 24 - 31 (8 bit)
access : read-write
Power Level Status Register
address_offset : 0x1FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLCBUSY : Power Level Change Busy Bit (Read Only)\nThis bit is set by hardware when power level is changing . After power level change is completed, this bit will be cleared automatically by hardware.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Power level change is completed
#1 : 1
Power level change is ongoing
End of enumeration elements list.
MVRCBUSY : Main Voltage Regulator Type Change Busy Bit (Read Only)\nThis bit is set by hardware when main voltage regulator type is changing. After main voltage regulator type change is completed, this bit will be cleared automatically by hardware.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Main voltage regulator type change is completed
#1 : 1
Main voltage regulator type change is ongoing
End of enumeration elements list.
MVRCERR : Main Voltage Regulator Type Change Error Bit (Write Protect)\nThis bit Is set by Hardware When Main Voltage Regulator Type Change From LDO to DCDC Error Occurred\nThis bit is set to 1 when main voltage regulator type change from LDO to DCDC error, the following conditions will cause change errors\n1.System change to DC-DC mode but LDO change voltage process not finish\n2.Detect inductor fail.\n\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No main voltage regulator type change error.\nNo effect
#1 : 1
Main voltage regulator type change to DCDC error occurred.\nClears MVRCERR to 0
End of enumeration elements list.
LCONS : Inductor for DC-dC Connect Status (Read Only) \nNote: This bit is 1 when main viltage regulator is LDO.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
Inductor connect between Vsw and LDO_CAP pin
#1 : 1
No Inductor connect between Vsw and LDO_CAP pin
End of enumeration elements list.
PDINVTRF : Power-down Mode Invalid Transition Flag (Write Protect)\nThis bit is set by hardware if the requested active DCDC mode to Power-down mode transition is invalid. This transition request will be aborted by hardware. The bit can be cleared by software.\nRead:\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Power-dwon mode invalid transition.\nNo effect
#1 : 1
Power-dwon mode invalid transition occurred.\nClears this bit to 0
End of enumeration elements list.
PLSTATUS : Power Level Status (Read Only)\nThis bit field reflect the current power level.
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
#00 : 0
Power level is PL0
#01 : 1
Power level is PL1
End of enumeration elements list.
CURMVR : Current Main Voltage Regulator Type (Read Only)\nThis bit field reflects current main voltage regulator type.
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
Current main voltage regulator in active and Idle mode is LDO
#1 : 1
Current main voltage regulator in active mode and Idle is DCDC
End of enumeration elements list.
Power-on Reset Controller Register 0
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORMASK : Power-on Reset Mask Enable Bit (Write Protect)
When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can mask internal POR signal to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.
Note: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 15 (16 bit)
access : read-write
VREF Control Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREFCTL : VREF Control Bits (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
#00000 : 0
VREF is from external pin
#00011 : 3
VREF is internal 1.6V
#00111 : 7
VREF is internal 2.0V
#01011 : 11
VREF is internal 2.5V
#01111 : 15
VREF is internal 3.0V
End of enumeration elements list.
IBIASSEL : VREF Bias Current Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bias current from MEGBIAS
#1 : 1
Bias current from internal
End of enumeration elements list.
PRELOADSEL : Pre-load Timing Selection (Write Protect)\nNote: These bits is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
pre-load time is 60us for 0.1uF Capacitor
#01 : 1
pre-load time is 310us for 1uF Capacitor
#10 : 2
pre-load time is 2100us for 4.7uF Capacitor
#11 : 3
pre-load time is 2850us for 10uF Capacitor
End of enumeration elements list.
USB PHY Control Register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBROLE : USB Role Option (Write Protect)\nThese two bits are used to select the role of USB.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Standard USB Device mode
#01 : 1
Standard USB Host mode
#10 : 2
ID dependent mode
#11 : 3
On-The-Go device mode (default)
End of enumeration elements list.
SBO : Note: This bit must always be kept 1. If set to 0, the result is unpredictable.
bits : 2 - 2 (1 bit)
access : read-write
OTGPHYEN : USB OTG PHY Enable \nThis bit is used to enable/disable OTG PHY function.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
OTG PHY function Disabled (default)
#1 : 1
OTG PHY function Enabled
End of enumeration elements list.
GPIOA Low Byte Multiple Function Control Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA0MFP : PA.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PA.0
#0011 : 3
QSPI0_MOSI0
#0100 : 4
SPI0_MOSI
#0110 : 6
SC0_CLK
#0111 : 7
UART0_RXD
#1000 : 8
UART1_nRTS
#1001 : 9
I2C2_SDA
#1100 : 12
BPWM0_CH0
#1101 : 13
EPWM0_CH5
#1111 : 15
DAC0_ST
End of enumeration elements list.
PA1MFP : PA.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PA.1
#0011 : 3
QSPI0_MISO0
#0100 : 4
SPI0_MISO
#0110 : 6
SC0_DAT
#0111 : 7
UART0_TXD
#1000 : 8
UART1_nCTS
#1001 : 9
I2C2_SCL
#1100 : 12
BPWM0_CH1
#1101 : 13
EPWM0_CH4
#1111 : 15
DAC1_ST
End of enumeration elements list.
PA2MFP : PA.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PA.2
#0011 : 3
QSPI0_CLK
#0100 : 4
SPI0_CLK
#0110 : 6
SC0_RST
#0111 : 7
UART4_RXD
#1000 : 8
UART1_RXD
#1001 : 9
I2C1_SDA
#1100 : 12
BPWM0_CH2
#1101 : 13
EPWM0_CH3
End of enumeration elements list.
PA3MFP : PA.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PA.3
#0011 : 3
QSPI0_SS
#0100 : 4
SPI0_SS
#0110 : 6
SC0_PWR
#0111 : 7
UART4_TXD
#1000 : 8
UART1_TXD
#1001 : 9
I2C1_SCL
#1100 : 12
BPWM0_CH3
#1101 : 13
EPWM0_CH2
#1110 : 14
QEI0_B
End of enumeration elements list.
PA4MFP : PA.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PA.4
#0011 : 3
QSPI0_MOSI1
#0100 : 4
SPI0_I2SMCLK
#0110 : 6
SC0_nCD
#0111 : 7
UART0_nRTS
#1000 : 8
UART5_RXD
#1001 : 9
I2C0_SDA
#1010 : 10
CAN0_RXD
#1100 : 12
BPWM0_CH4
#1101 : 13
EPWM0_CH1
#1110 : 14
QEI0_A
End of enumeration elements list.
PA5MFP : PA.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PA.5
#0011 : 3
QSPI0_MISO1
#0100 : 4
SPI1_I2SMCLK
#0110 : 6
SC2_nCD
#0111 : 7
UART0_nCTS
#1000 : 8
UART5_TXD
#1001 : 9
I2C0_SCL
#1010 : 10
CAN0_TXD
#1100 : 12
BPWM0_CH5
#1101 : 13
EPWM0_CH0
#1110 : 14
QEI0_INDEX
End of enumeration elements list.
PA6MFP : PA.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PA.6
#0010 : 2
EBI_AD6
#0100 : 4
SPI1_SS
#0110 : 6
SC2_CLK
#0111 : 7
UART0_RXD
#1000 : 8
I2C1_SDA
#1011 : 11
EPWM1_CH5
#1100 : 12
BPWM1_CH3
#1101 : 13
ACMP1_WLAT
#1110 : 14
TM3
#1111 : 15
INT0
End of enumeration elements list.
PA7MFP : PA.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PA.7
#0010 : 2
EBI_AD7
#0100 : 4
SPI1_CLK
#0110 : 6
SC2_DAT
#0111 : 7
UART0_TXD
#1000 : 8
I2C1_SCL
#1011 : 11
EPWM1_CH4
#1100 : 12
BPWM1_CH2
#1101 : 13
ACMP0_WLAT
#1110 : 14
TM2
#1111 : 15
INT1
End of enumeration elements list.
GPIOA High Byte Multiple Function Control Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA8MFP : PA.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PA.8
#0010 : 2
EBI_ALE
#0011 : 3
SC2_CLK
#0100 : 4
SPI2_MOSI
#0110 : 6
USCI0_CTL1
#0111 : 7
UART1_RXD
#1001 : 9
BPWM0_CH3
#1010 : 10
QEI1_B
#1011 : 11
ECAP0_IC2
#1101 : 13
TM3_EXT
#1111 : 15
INT4
End of enumeration elements list.
PA9MFP : PA.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PA.9
#0010 : 2
EBI_MCLK
#0011 : 3
SC2_DAT
#0100 : 4
SPI2_MISO
#0110 : 6
USCI0_DAT1
#0111 : 7
UART1_TXD
#1001 : 9
BPWM0_CH2
#1010 : 10
QEI1_A
#1011 : 11
ECAP0_IC1
#1101 : 13
TM2_EXT
End of enumeration elements list.
PA10MFP : PA.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PA.10
#0001 : 1
ACMP1_P0
#0010 : 2
EBI_nWR
#0011 : 3
SC2_RST
#0100 : 4
SPI2_CLK
#0110 : 6
USCI0_DAT0
#0111 : 7
I2C2_SDA
#1001 : 9
BPWM0_CH1
#1010 : 10
QEI1_INDEX
#1011 : 11
ECAP0_IC0
#1101 : 13
TM1_EXT
#1110 : 14
DAC0_ST
End of enumeration elements list.
PA11MFP : PA.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PA.11
#0001 : 1
ACMP0_P0
#0010 : 2
EBI_nRD
#0011 : 3
SC2_PWR
#0100 : 4
SPI2_SS
#0110 : 6
USCI0_CLK
#0111 : 7
I2C2_SCL
#1001 : 9
BPWM0_CH0
#1010 : 10
EPWM0_SYNC_OUT
#1101 : 13
TM0_EXT
#1110 : 14
DAC1_ST
End of enumeration elements list.
PA12MFP : PA.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PA.12
#0010 : 2
I2S0_BCLK
#0011 : 3
UART4_TXD
#0100 : 4
I2C1_SCL
#0101 : 5
SPI2_SS
#0110 : 6
CAN0_TXD
#0111 : 7
SC2_PWR
#1011 : 11
BPWM1_CH2
#1100 : 12
QEI1_INDEX
#1110 : 14
USB_VBUS
End of enumeration elements list.
PA13MFP : PA.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PA.13
#0010 : 2
I2S0_MCLK
#0011 : 3
UART4_RXD
#0100 : 4
I2C1_SDA
#0101 : 5
SPI2_CLK
#0110 : 6
CAN0_RXD
#0111 : 7
SC2_RST
#1011 : 11
BPWM1_CH3
#1100 : 12
QEI1_A
#1110 : 14
USB_D-
End of enumeration elements list.
PA14MFP : PA.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PA.14
#0010 : 2
I2S0_DI
#0011 : 3
UART0_TXD
#0101 : 5
SPI2_MISO
#0110 : 6
I2C2_SCL
#0111 : 7
SC2_DAT
#1011 : 11
BPWM1_CH4
#1100 : 12
QEI1_B
#1110 : 14
USB_D+
End of enumeration elements list.
PA15MFP : PA.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PA.15
#0010 : 2
I2S0_DO
#0011 : 3
UART0_RXD
#0101 : 5
SPI2_MOSI
#0110 : 6
I2C2_SDA
#0111 : 7
SC2_CLK
#1011 : 11
BPWM1_CH5
#1100 : 12
EPWM0_SYNC_IN
#1110 : 14
USB_OTG_ID
End of enumeration elements list.
GPIOB Low Byte Multiple Function Control Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB0MFP : PB.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PB.0
#0001 : 1
EADC0_CH0
#0010 : 2
EBI_ADR9
#0011 : 3
SD0_CMD
#0111 : 7
UART2_RXD
#1000 : 8
SPI0_I2SMCLK
#1001 : 9
I2C1_SDA
#1011 : 11
EPWM0_CH5
#1100 : 12
EPWM1_CH5
#1101 : 13
EPWM0_BRAKE1
End of enumeration elements list.
PB1MFP : PB.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PB.1
#0001 : 1
EADC0_CH1
#0010 : 2
EBI_ADR8
#0011 : 3
SD0_CLK
#0101 : 5
SPI1_I2SMCLK
#0110 : 6
SPI3_I2SMCLK
#0111 : 7
UART2_TXD
#1000 : 8
USCI1_CLK
#1001 : 9
I2C1_SCL
#1010 : 10
I2S0_LRCK
#1011 : 11
EPWM0_CH4
#1100 : 12
EPWM1_CH4
#1101 : 13
EPWM0_BRAKE0
End of enumeration elements list.
PB2MFP : PB.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PB.2
#0001 : 1
EADC0_CH2\nACMP0_P1
#0010 : 2
EBI_ADR3
#0011 : 3
SD0_DAT0
#0101 : 5
SPI1_SS
#0110 : 6
UART1_RXD
#0111 : 7
UART5_nCTS
#1000 : 8
USCI1_DAT0
#1001 : 9
SC0_PWR
#1010 : 10
I2S0_DO
#1011 : 11
EPWM0_CH3
#1110 : 14
TM3
#1111 : 15
INT3
End of enumeration elements list.
PB3MFP : PB.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PB.3
#0001 : 1
EADC0_CH3\nACMP0_N
#0010 : 2
EBI_ADR2
#0011 : 3
SD0_DAT1
#0101 : 5
SPI1_CLK
#0110 : 6
UART1_TXD
#0111 : 7
UART5_nRTS
#1000 : 8
USCI1_DAT1
#1001 : 9
SC0_RST
#1010 : 10
I2S0_DI
#1011 : 11
EPWM0_CH2
#1110 : 14
TM2
#1111 : 15
INT2
End of enumeration elements list.
PB4MFP : PB.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PB.4
#0001 : 1
EADC0_CH4\nACMP1_P1
#0010 : 2
EBI_ADR1
#0011 : 3
SD0_DAT2
#0101 : 5
SPI1_MOSI
#0110 : 6
I2C0_SDA
#0111 : 7
UART5_RXD
#1000 : 8
USCI1_CTL1
#1001 : 9
SC0_DAT
#1010 : 10
I2S0_MCLK
#1011 : 11
EPWM0_CH1
#1110 : 14
TM1
#1111 : 15
INT1
End of enumeration elements list.
PB5MFP : PB.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PB.5
#0001 : 1
EADC0_CH5\nACMP1_N
#0010 : 2
EBI_ADR0
#0011 : 3
SD0_DAT3
#0101 : 5
SPI1_MISO
#0110 : 6
I2C0_SCL
#0111 : 7
UART5_TXD
#1000 : 8
USCI1_CTL0
#1001 : 9
SC0_CLK
#1010 : 10
I2S0_BCLK
#1011 : 11
EPWM0_CH0
#1110 : 14
TM0
#1111 : 15
INT0
End of enumeration elements list.
PB6MFP : PB.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PB.6
#0001 : 1
EADC0_CH6
#0010 : 2
EBI_nWRH
#0100 : 4
USCI1_DAT1
#0110 : 6
UART1_RXD
#1000 : 8
EBI_nCS1
#1010 : 10
BPWM1_CH5
#1011 : 11
EPWM1_BRAKE1
#1100 : 12
EPWM1_CH5
#1101 : 13
INT4
#1110 : 14
USB_VBUS_EN
#1111 : 15
ACMP1_O
End of enumeration elements list.
PB7MFP : PB.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PB.7
#0001 : 1
EADC0_CH7
#0010 : 2
EBI_nWRL
#0100 : 4
USCI1_DAT0
#0110 : 6
UART1_TXD
#1000 : 8
EBI_nCS0
#1010 : 10
BPWM1_CH4
#1011 : 11
EPWM1_BRAKE0
#1100 : 12
EPWM1_CH4
#1101 : 13
INT5
#1110 : 14
USB_VBUS_ST
#1111 : 15
ACMP0_O
End of enumeration elements list.
GPIOB High Byte Multiple Function Control Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB8MFP : PB.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PB.8
#0001 : 1
EADC0_CH8
#0010 : 2
EBI_ADR19
#0100 : 4
USCI1_CLK
#0101 : 5
UART0_RXD
#0110 : 6
UART1_nRTS
#0111 : 7
I2C1_SMBSUS
#1010 : 10
BPWM1_CH3
#1011 : 11
SPI3_MOSI
#1101 : 13
INT6
End of enumeration elements list.
PB9MFP : PB.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PB.9
#0001 : 1
EADC0_CH9
#0010 : 2
EBI_ADR18
#0100 : 4
USCI1_CTL1
#0101 : 5
UART0_TXD
#0110 : 6
UART1_nCTS
#0111 : 7
I2C1_SMBAL
#1010 : 10
BPWM1_CH2
#1011 : 11
SPI3_MISO
#1101 : 13
INT7
End of enumeration elements list.
PB10MFP : PB.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PB.10
#0001 : 1
EADC0_CH10
#0010 : 2
EBI_ADR17
#0100 : 4
USCI1_CTL0
#0101 : 5
UART0_nRTS
#0110 : 6
UART4_RXD
#0111 : 7
I2C1_SDA
#1000 : 8
CAN0_RXD
#1010 : 10
BPWM1_CH1
#1011 : 11
SPI3_SS
End of enumeration elements list.
PB11MFP : PB.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PB.11
#0001 : 1
EADC0_CH11
#0010 : 2
EBI_ADR16
#0101 : 5
UART0_nCTS
#0110 : 6
UART4_TXD
#0111 : 7
I2C1_SCL
#1000 : 8
CAN0_TXD
#1001 : 9
SPI0_I2SMCLK
#1010 : 10
BPWM1_CH0
#1011 : 11
SPI3_CLK
End of enumeration elements list.
PB12MFP : PB.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PB.12
#0001 : 1
EADC0_CH12\nDAC0_OUT\nACMP0_P2\nACMP1_P2
#0010 : 2
EBI_AD15
#0011 : 3
SC1_CLK
#0100 : 4
SPI0_MOSI
#0101 : 5
USCI0_CLK
#0110 : 6
UART0_RXD
#0111 : 7
UART3_nCTS
#1000 : 8
I2C2_SDA
#1001 : 9
SD0_nCD
#1011 : 11
EPWM1_CH3
#1101 : 13
TM3_EXT
End of enumeration elements list.
PB13MFP : PB.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PB.13
#0001 : 1
EADC0_CH13\nDAC1_OUT\nACMP0_P3\nACMP1_P3
#0010 : 2
EBI_AD14
#0011 : 3
SC1_DAT
#0100 : 4
SPI0_MISO
#0101 : 5
USCI0_DAT0
#0110 : 6
UART0_TXD
#0111 : 7
UART3_nRTS
#1000 : 8
I2C2_SCL
#1011 : 11
EPWM1_CH2
#1101 : 13
TM2_EXT
End of enumeration elements list.
PB14MFP : PB.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PB.14
#0001 : 1
EADC0_CH14
#0010 : 2
EBI_AD13
#0011 : 3
SC1_RST
#0100 : 4
SPI0_CLK
#0101 : 5
USCI0_DAT1
#0110 : 6
UART0_nRTS
#0111 : 7
UART3_RXD
#1000 : 8
I2C2_SMBSUS
#1011 : 11
EPWM1_CH1
#1101 : 13
TM1_EXT
#1110 : 14
CLKO
#1111 : 15
USB_VBUS_ST
End of enumeration elements list.
PB15MFP : PB.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PB.15
#0001 : 1
EADC0_CH15
#0010 : 2
EBI_AD12
#0011 : 3
SC1_PWR
#0100 : 4
SPI0_SS
#0101 : 5
USCI0_CTL1
#0110 : 6
UART0_nCTS
#0111 : 7
UART3_TXD
#1000 : 8
I2C2_SMBAL
#1011 : 11
EPWM1_CH0
#1101 : 13
TM0_EXT
#1110 : 14
USB_VBUS_EN
End of enumeration elements list.
System Reset Status Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORF : POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from POR or CHIPRST
#1 : 1
Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system
End of enumeration elements list.
PINRF : nRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from nRESET pin
#1 : 1
Pin nRESET had issued the reset signal to reset the system
End of enumeration elements list.
WDTRF : WDT Reset Flag\nThe WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\nNote1: Write 1 to clear this bit to 0.\nNote2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from watchdog timer or window watchdog timer
#1 : 1
The watchdog timer or window watchdog timer had issued the reset signal to reset the system
End of enumeration elements list.
LVRF : LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from LVR
#1 : 1
LVR controller had issued the reset signal to reset the system
End of enumeration elements list.
BODRF : BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from BOD
#1 : 1
The BOD had issued the reset signal to reset the system
End of enumeration elements list.
SYSRF : System Reset Flag\nThe system reset flag is set by the 'Reset Signal' from the Cortex-M23 Core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from the Cortex-M23
#1 : 1
The Cortex-M23 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M23 core
End of enumeration elements list.
CPURF : CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset the Cortex-M23 core and Flash Memory Controller (FMC).\nNote: Write 1 to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from CPU
#1 : 1
The Cortex-M23 Core and FMC are reset by software setting CPURST to 1
End of enumeration elements list.
CPULKRF : CPU Lockup Reset Flag\nThe CPU Lockup reset flag is set by hardware if Cortex-M23 lockup happened.\nNote1: Write 1 to clear this bit to 0.\nNote2: When CPU lockup happened under ICE is connected, This flag will set to 1 but chip will not reset.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from CPU lockup happened
#1 : 1
The Cortex-M23 lockup happened and chip is reset
End of enumeration elements list.
GPIOC Low Byte Multiple Function Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC0MFP : PC.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PC.0
#0010 : 2
EBI_AD0
#0100 : 4
QSPI0_MOSI0
#0101 : 5
SC1_CLK
#0110 : 6
I2S0_LRCK
#0111 : 7
SPI1_SS
#1000 : 8
UART2_RXD
#1001 : 9
I2C0_SDA
#1100 : 12
EPWM1_CH5
#1110 : 14
ACMP1_O
End of enumeration elements list.
PC1MFP : PC.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PC.1
#0010 : 2
EBI_AD1
#0100 : 4
QSPI0_MISO0
#0101 : 5
SC1_DAT
#0110 : 6
I2S0_DO
#0111 : 7
SPI1_CLK
#1000 : 8
UART2_TXD
#1001 : 9
I2C0_SCL
#1100 : 12
EPWM1_CH4
#1110 : 14
ACMP0_O
End of enumeration elements list.
PC2MFP : PC.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PC.2
#0010 : 2
EBI_AD2
#0100 : 4
QSPI0_CLK
#0101 : 5
SC1_RST
#0110 : 6
I2S0_DI
#0111 : 7
SPI1_MOSI
#1000 : 8
UART2_nCTS
#1001 : 9
I2C0_SMBSUS
#1011 : 11
UART3_RXD
#1100 : 12
EPWM1_CH3
End of enumeration elements list.
PC3MFP : PC.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PC.3
#0010 : 2
EBI_AD3
#0100 : 4
QSPI0_SS
#0101 : 5
SC1_PWR
#0110 : 6
I2S0_MCLK
#0111 : 7
SPI1_MISO
#1000 : 8
UART2_nRTS
#1001 : 9
I2C0_SMBAL
#1011 : 11
UART3_TXD
#1100 : 12
EPWM1_CH2
End of enumeration elements list.
PC4MFP : PC.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PC.4
#0010 : 2
EBI_AD4
#0100 : 4
QSPI0_MOSI1
#0101 : 5
SC1_nCD
#0110 : 6
I2S0_BCLK
#0111 : 7
SPI1_I2SMCLK
#1000 : 8
UART2_RXD
#1001 : 9
I2C1_SDA
#1010 : 10
CAN0_RXD
#1011 : 11
UART4_RXD
#1100 : 12
EPWM1_CH1
End of enumeration elements list.
PC5MFP : PC.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PC.5
#0010 : 2
EBI_AD5
#0100 : 4
QSPI0_MISO1
#1000 : 8
UART2_TXD
#1001 : 9
I2C1_SCL
#1010 : 10
CAN0_TXD
#1011 : 11
UART4_TXD
#1100 : 12
EPWM1_CH0
End of enumeration elements list.
PC6MFP : PC.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PC.6
#0010 : 2
EBI_AD8
#0100 : 4
SPI1_MOSI
#0101 : 5
UART4_RXD
#0110 : 6
SC2_RST
#0111 : 7
UART0_nRTS
#1000 : 8
I2C1_SMBSUS
#1011 : 11
EPWM1_CH3
#1100 : 12
BPWM1_CH1
#1110 : 14
TM1
#1111 : 15
INT2
End of enumeration elements list.
PC7MFP : PC.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PC.7
#0010 : 2
EBI_AD9
#0100 : 4
SPI1_MISO
#0101 : 5
UART4_TXD
#0110 : 6
SC2_PWR
#0111 : 7
UART0_nCTS
#1000 : 8
I2C1_SMBAL
#1011 : 11
EPWM1_CH2
#1100 : 12
BPWM1_CH0
#1110 : 14
TM0
#1111 : 15
INT3
End of enumeration elements list.
GPIOC High Byte Multiple Function Control Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC8MFP : PC.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PC.8
#0010 : 2
EBI_ADR16
#0100 : 4
I2C0_SDA
#0101 : 5
UART4_nCTS
#1000 : 8
UART1_RXD
#1011 : 11
EPWM1_CH1
#1100 : 12
BPWM1_CH4
End of enumeration elements list.
PC9MFP : PC.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PC.9
#0010 : 2
EBI_ADR7
#0110 : 6
SPI3_SS
#0111 : 7
UART3_RXD
#1100 : 12
EPWM1_CH3
End of enumeration elements list.
PC10MFP : PC.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PC.10
#0010 : 2
EBI_ADR6
#0110 : 6
SPI3_CLK
#0111 : 7
UART3_TXD
#1011 : 11
ECAP1_IC0
#1100 : 12
EPWM1_CH2
End of enumeration elements list.
PC11MFP : PC.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PC.11
#0010 : 2
EBI_ADR5
#0011 : 3
UART0_RXD
#0100 : 4
I2C0_SDA
#0110 : 6
SPI3_MOSI
#1011 : 11
ECAP1_IC1
#1100 : 12
EPWM1_CH1
#1110 : 14
ACMP1_O
End of enumeration elements list.
PC12MFP : PC.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PC.12
#0010 : 2
EBI_ADR4
#0011 : 3
UART0_TXD
#0100 : 4
I2C0_SCL
#0110 : 6
SPI3_MISO
#1001 : 9
SC0_nCD
#1011 : 11
ECAP1_IC2
#1100 : 12
EPWM1_CH0
#1110 : 14
ACMP0_O
End of enumeration elements list.
PC13MFP : PC.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PC.13
#0010 : 2
EBI_ADR10
#0011 : 3
SC2_nCD
#0100 : 4
SPI2_I2SMCLK
#0110 : 6
USCI0_CTL0
#0111 : 7
UART2_TXD
#1001 : 9
BPWM0_CH4
#1101 : 13
CLKO
#1110 : 14
EADC0_ST
End of enumeration elements list.
GPIOD Low Byte Multiple Function Control Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD0MFP : PD.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PD.0
#0010 : 2
EBI_AD13
#0011 : 3
USCI0_CLK
#0100 : 4
SPI0_MOSI
#0101 : 5
UART3_RXD
#0110 : 6
I2C2_SDA
#0111 : 7
SC2_CLK
#1110 : 14
TM2
End of enumeration elements list.
PD1MFP : PD.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PD.1
#0010 : 2
EBI_AD12
#0011 : 3
USCI0_DAT0
#0100 : 4
SPI0_MISO
#0101 : 5
UART3_TXD
#0110 : 6
I2C2_SCL
#0111 : 7
SC2_DAT
End of enumeration elements list.
PD2MFP : PD.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PD.2
#0010 : 2
EBI_AD11
#0011 : 3
USCI0_DAT1
#0100 : 4
SPI0_CLK
#0101 : 5
UART3_nCTS
#0111 : 7
SC2_RST
#1001 : 9
UART0_RXD
End of enumeration elements list.
PD3MFP : PD.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PD.3
#0010 : 2
EBI_AD10
#0011 : 3
USCI0_CTL1
#0100 : 4
SPI0_SS
#0101 : 5
UART3_nRTS
#0110 : 6
USCI1_CTL0
#0111 : 7
SC2_PWR
#1000 : 8
SC1_nCD
#1001 : 9
UART0_TXD
End of enumeration elements list.
PD4MFP : PD.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PD.4
#0011 : 3
USCI0_CTL0
#0100 : 4
I2C1_SDA
#0101 : 5
SPI1_SS
#0110 : 6
USCI1_CTL1
#1000 : 8
SC1_CLK
#1110 : 14
USB_VBUS_ST
End of enumeration elements list.
PD5MFP : PD.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PD.5
#0100 : 4
I2C1_SCL
#0101 : 5
SPI1_CLK
#0110 : 6
USCI1_DAT0
#1000 : 8
SC1_DAT
End of enumeration elements list.
PD6MFP : PD.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PD.6
#0011 : 3
UART1_RXD
#0100 : 4
I2C0_SDA
#0101 : 5
SPI1_MOSI
#0110 : 6
USCI1_DAT1
#1000 : 8
SC1_RST
End of enumeration elements list.
PD7MFP : PD.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PD.7
#0011 : 3
UART1_TXD
#0100 : 4
I2C0_SCL
#0101 : 5
SPI1_MISO
#0110 : 6
USCI1_CLK
#1000 : 8
SC1_PWR
End of enumeration elements list.
GPIOD High Byte Multiple Function Control Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD8MFP : PD.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PD.8
#0010 : 2
EBI_AD6
#0011 : 3
I2C2_SDA
#0100 : 4
UART2_nRTS
End of enumeration elements list.
PD9MFP : PD.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PD.9
#0010 : 2
EBI_AD7
#0011 : 3
I2C2_SCL
#0100 : 4
UART2_nCTS
End of enumeration elements list.
PD10MFP : PD.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PD.10
#0010 : 2
EBI_nCS2
#0011 : 3
UART1_RXD
#0100 : 4
CAN0_RXD
#1010 : 10
QEI0_B
#1111 : 15
INT7
End of enumeration elements list.
PD11MFP : PD.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PD.11
#0010 : 2
EBI_nCS1
#0011 : 3
UART1_TXD
#0100 : 4
CAN0_TXD
#1010 : 10
QEI0_A
#1111 : 15
INT6
End of enumeration elements list.
PD12MFP : PD.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PD.12
#0010 : 2
EBI_nCS0
#0111 : 7
UART2_RXD
#1001 : 9
BPWM0_CH5
#1010 : 10
QEI0_INDEX
#1101 : 13
CLKO
#1110 : 14
EADC0_ST
#1111 : 15
INT5
End of enumeration elements list.
PD13MFP : PD.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PD.13
#0010 : 2
EBI_AD10
#0011 : 3
SD0_nCD
#0100 : 4
SPI0_I2SMCLK
#0101 : 5
SPI1_I2SMCLK
#0111 : 7
SC2_nCD
End of enumeration elements list.
PD14MFP : PD.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PD.14
#0010 : 2
EBI_nCS0
#0011 : 3
SPI3_I2SMCLK
#0100 : 4
SC1_nCD
#0101 : 5
USCI0_CTL0
#0110 : 6
SPI0_I2SMCLK
#1011 : 11
EPWM0_CH4
End of enumeration elements list.
GPIOE Low Byte Multiple Function Control Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE0MFP : PE.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PE.0
#0010 : 2
EBI_AD11
#0011 : 3
QSPI0_MOSI0
#0100 : 4
SC2_CLK
#0101 : 5
I2S0_MCLK
#0110 : 6
SPI1_MOSI
#0111 : 7
UART3_RXD
#1000 : 8
I2C1_SDA
#1001 : 9
UART4_nRTS
End of enumeration elements list.
PE1MFP : PE.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PE.1
#0010 : 2
EBI_AD10
#0011 : 3
QSPI0_MISO0
#0100 : 4
SC2_DAT
#0101 : 5
I2S0_BCLK
#0110 : 6
SPI1_MISO
#0111 : 7
UART3_TXD
#1000 : 8
I2C1_SCL
#1001 : 9
UART4_nCTS
End of enumeration elements list.
PE2MFP : PE.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PE.2
#0010 : 2
EBI_ALE
#0011 : 3
SD0_DAT0
#0101 : 5
SPI3_MOSI
#0110 : 6
SC0_CLK
#0111 : 7
USCI0_CLK
#1011 : 11
QEI0_B
#1100 : 12
EPWM0_CH5
#1101 : 13
BPWM0_CH0
End of enumeration elements list.
PE3MFP : PE.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PE.3
#0010 : 2
EBI_MCLK
#0011 : 3
SD0_DAT1
#0101 : 5
SPI3_MISO
#0110 : 6
SC0_DAT
#0111 : 7
USCI0_DAT0
#1011 : 11
QEI0_A
#1100 : 12
EPWM0_CH4
#1101 : 13
BPWM0_CH1
End of enumeration elements list.
PE4MFP : PE.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PE.4
#0010 : 2
EBI_nWR
#0011 : 3
SD0_DAT2
#0101 : 5
SPI3_CLK
#0110 : 6
SC0_RST
#0111 : 7
USCI0_DAT1
#1011 : 11
QEI0_INDEX
#1100 : 12
EPWM0_CH3
#1101 : 13
BPWM0_CH2
End of enumeration elements list.
PE5MFP : PE.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PE.5
#0010 : 2
EBI_nRD
#0011 : 3
SD0_DAT3
#0101 : 5
SPI3_SS
#0110 : 6
SC0_PWR
#0111 : 7
USCI0_CTL1
#1011 : 11
QEI1_B
#1100 : 12
EPWM0_CH2
#1101 : 13
BPWM0_CH3
End of enumeration elements list.
PE6MFP : PE.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PE.6
#0011 : 3
SD0_CLK
#0101 : 5
SPI3_I2SMCLK
#0110 : 6
SC0_nCD
#0111 : 7
USCI0_CTL0
#1000 : 8
UART5_RXD
#1011 : 11
QEI1_A
#1100 : 12
EPWM0_CH1
#1101 : 13
BPWM0_CH4
End of enumeration elements list.
PE7MFP : PE.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PE.7
#0011 : 3
SD0_CMD
#1000 : 8
UART5_TXD
#1011 : 11
QEI1_INDEX
#1100 : 12
EPWM0_CH0
#1101 : 13
BPWM0_CH5
End of enumeration elements list.
GPIOE High Byte Multiple Function Control Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE8MFP : PE.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PE.8
#0010 : 2
EBI_ADR10
#0100 : 4
I2S0_BCLK
#0101 : 5
SPI2_CLK
#0110 : 6
USCI1_CTL1
#0111 : 7
UART2_TXD
#1010 : 10
EPWM0_CH0
#1011 : 11
EPWM0_BRAKE0
#1100 : 12
ECAP0_IC0
#1110 : 14
TRACE_DATA3
End of enumeration elements list.
PE9MFP : PE.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PE.9
#0010 : 2
EBI_ADR11
#0100 : 4
I2S0_MCLK
#0101 : 5
SPI2_MISO
#0110 : 6
USCI1_CTL0
#0111 : 7
UART2_RXD
#1010 : 10
EPWM0_CH1
#1011 : 11
EPWM0_BRAKE1
#1100 : 12
ECAP0_IC1
#1110 : 14
TRACE_DATA2
End of enumeration elements list.
PE10MFP : PE.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PE.10
#0010 : 2
EBI_ADR12
#0100 : 4
I2S0_DI
#0101 : 5
SPI2_MOSI
#0110 : 6
USCI1_DAT0
#0111 : 7
UART3_TXD
#1010 : 10
EPWM0_CH2
#1011 : 11
EPWM1_BRAKE0
#1100 : 12
ECAP0_IC2
#1110 : 14
TRACE_DATA1
End of enumeration elements list.
PE11MFP : PE.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PE.11
#0010 : 2
EBI_ADR13
#0100 : 4
I2S0_DO
#0101 : 5
SPI2_SS
#0110 : 6
USCI1_DAT1
#0111 : 7
UART3_RXD
#1000 : 8
UART1_nCTS
#1010 : 10
EPWM0_CH3
#1011 : 11
EPWM1_BRAKE1
#1101 : 13
ECAP1_IC2
#1110 : 14
TRACE_DATA0
End of enumeration elements list.
PE12MFP : PE.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PE.12
#0010 : 2
EBI_ADR14
#0100 : 4
I2S0_LRCK
#0101 : 5
SPI2_I2SMCLK
#0110 : 6
USCI1_CLK
#1000 : 8
UART1_nRTS
#1010 : 10
EPWM0_CH4
#1101 : 13
ECAP1_IC1
#1110 : 14
TRACE_CLK
End of enumeration elements list.
PE13MFP : PE.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PE.13
#0010 : 2
EBI_ADR15
#0100 : 4
I2C0_SCL
#0101 : 5
UART4_nRTS
#1000 : 8
UART1_TXD
#1010 : 10
EPWM0_CH5
#1011 : 11
EPWM1_CH0
#1100 : 12
BPWM1_CH5
#1101 : 13
ECAP1_IC0
End of enumeration elements list.
PE14MFP : PE.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PE.14
#0010 : 2
EBI_AD8
#0011 : 3
UART2_TXD
#0100 : 4
CAN0_TXD
End of enumeration elements list.
PE15MFP : PE.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PE.15
#0010 : 2
EBI_AD9
#0011 : 3
UART2_RXD
#0100 : 4
CAN0_RXD
End of enumeration elements list.
GPIOF Low Byte Multiple Function Control Register
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF0MFP : PF.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PF.0
#0010 : 2
UART1_TXD
#0011 : 3
I2C1_SCL
#1100 : 12
BPWM1_CH0
#1110 : 14
ICE_DAT
End of enumeration elements list.
PF1MFP : PF.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PF.1
#0010 : 2
UART1_RXD
#0011 : 3
I2C1_SDA
#1100 : 12
BPWM1_CH1
#1110 : 14
ICE_CLK
End of enumeration elements list.
PF2MFP : PF.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PF.2
#0010 : 2
EBI_nCS1
#0011 : 3
UART0_RXD
#0100 : 4
I2C0_SDA
#0101 : 5
QSPI0_CLK
#1010 : 10
XT1_OUT
#1011 : 11
BPWM1_CH1
End of enumeration elements list.
PF3MFP : PF.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PF.3
#0010 : 2
EBI_nCS0
#0011 : 3
UART0_TXD
#0100 : 4
I2C0_SCL
#1010 : 10
XT1_IN
#1011 : 11
BPWM1_CH0
End of enumeration elements list.
PF4MFP : PF.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PF.4
#0010 : 2
UART2_TXD
#0100 : 4
UART2_nRTS
#1000 : 8
BPWM0_CH5
#1010 : 10
X32_OUT
End of enumeration elements list.
PF5MFP : PF.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PF.5
#0010 : 2
UART2_RXD
#0100 : 4
UART2_nCTS
#1000 : 8
BPWM0_CH4
#1001 : 9
EPWM0_SYNC_OUT
#1010 : 10
X32_IN
#1011 : 11
EADC0_ST
End of enumeration elements list.
PF6MFP : PF.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PF.6
#0010 : 2
EBI_ADR19
#0011 : 3
SC0_CLK
#0100 : 4
I2S0_LRCK
#0101 : 5
SPI0_MOSI
#0110 : 6
UART4_RXD
#0111 : 7
EBI_nCS0
#1010 : 10
TAMPER0
End of enumeration elements list.
PF7MFP : PF.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PF.7
#0010 : 2
EBI_ADR18
#0011 : 3
SC0_DAT
#0100 : 4
I2S0_DO
#0101 : 5
SPI0_MISO
#0110 : 6
UART4_TXD
#1010 : 10
TAMPER1
End of enumeration elements list.
GPIOF High Byte Multiple Function Control Register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF8MFP : PF.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PF.8
#0010 : 2
EBI_ADR17
#0011 : 3
SC0_RST
#0100 : 4
I2S0_DI
#0101 : 5
SPI0_CLK
#1010 : 10
TAMPER2
End of enumeration elements list.
PF9MFP : PF.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PF.9
#0010 : 2
EBI_ADR16
#0011 : 3
SC0_PWR
#0100 : 4
I2S0_MCLK
#0101 : 5
SPI0_SS
#1010 : 10
TAMPER3
End of enumeration elements list.
PF10MFP : PF.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PF.10
#0010 : 2
EBI_ADR15
#0011 : 3
SC0_nCD
#0100 : 4
I2S0_BCLK
#0101 : 5
SPI0_I2SMCLK
#1010 : 10
TAMPER4
End of enumeration elements list.
PF11MFP : PF.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PF.11
#0010 : 2
EBI_ADR14
#0011 : 3
SPI2_MOSI
#1010 : 10
TAMPER5
#1101 : 13
TM3
End of enumeration elements list.
GPIOG Low Byte Multiple Function Control Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG2MFP : PG.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PG.2
#0010 : 2
EBI_ADR11
#0011 : 3
SPI2_SS
#0100 : 4
I2C0_SMBAL
#0101 : 5
I2C1_SCL
#1101 : 13
TM0
End of enumeration elements list.
PG3MFP : PG.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PG.3
#0010 : 2
EBI_ADR12
#0011 : 3
SPI2_CLK
#0100 : 4
I2C0_SMBSUS
#0101 : 5
I2C1_SDA
#1101 : 13
TM1
End of enumeration elements list.
PG4MFP : PG.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PG.4
#0010 : 2
EBI_ADR13
#0011 : 3
SPI2_MISO
#1101 : 13
TM2
End of enumeration elements list.
GPIOG High Byte Multiple Function Control Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG8MFP : PG.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PG9MFP : PG.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PG.9
#0010 : 2
EBI_AD0
#1100 : 12
BPWM0_CH5
End of enumeration elements list.
PG10MFP : PG.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PG.10
#0010 : 2
EBI_AD1
#1100 : 12
BPWM0_CH4
End of enumeration elements list.
PG11MFP : PG.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PG.11
#0010 : 2
EBI_AD2
#1100 : 12
BPWM0_CH3
End of enumeration elements list.
PG12MFP : PG.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PG.12
#0010 : 2
EBI_AD3
#1100 : 12
BPWM0_CH2
End of enumeration elements list.
PG13MFP : PG.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PG.13
#0010 : 2
EBI_AD4
#1100 : 12
BPWM0_CH1
End of enumeration elements list.
PG14MFP : PG.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PG.14
#0010 : 2
EBI_AD5
#1100 : 12
BPWM0_CH0
End of enumeration elements list.
PG15MFP : PG.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PG.15
#1110 : 14
CLKO
#1111 : 15
EADC0_ST
End of enumeration elements list.
GPIOH Low Byte Multiple Function Control Register
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PH4MFP : PH.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PH.4
#0010 : 2
EBI_ADR3
#0011 : 3
SPI1_MISO
End of enumeration elements list.
PH5MFP : PH.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PH.5
#0010 : 2
EBI_ADR2
#0011 : 3
SPI1_MOSI
End of enumeration elements list.
PH6MFP : PH.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PH.6
#0010 : 2
EBI_ADR1
#0011 : 3
SPI1_CLK
End of enumeration elements list.
PH7MFP : PH.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PH.7
#0010 : 2
EBI_ADR0
#0011 : 3
SPI1_SS
End of enumeration elements list.
GPIOH High Byte Multiple Function Control Register
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PH8MFP : PH.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PH.8
#0010 : 2
EBI_AD12
#0011 : 3
QSPI0_CLK
#0100 : 4
SC2_PWR
#0101 : 5
I2S0_DI
#0110 : 6
SPI1_CLK
#0111 : 7
UART3_nRTS
#1000 : 8
I2C1_SMBAL
#1001 : 9
I2C2_SCL
#1010 : 10
UART1_TXD
End of enumeration elements list.
PH9MFP : PH.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PH.9
#0010 : 2
EBI_AD13
#0011 : 3
QSPI0_SS
#0100 : 4
SC2_RST
#0101 : 5
I2S0_DO
#0110 : 6
SPI1_SS
#0111 : 7
UART3_nCTS
#1000 : 8
I2C1_SMBSUS
#1001 : 9
I2C2_SDA
#1010 : 10
UART1_RXD
End of enumeration elements list.
PH10MFP : PH.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PH.10
#0010 : 2
EBI_AD14
#0011 : 3
QSPI0_MISO1
#0100 : 4
SC2_nCD
#0101 : 5
I2S0_LRCK
#0110 : 6
SPI1_I2SMCLK
#0111 : 7
UART4_TXD
#1000 : 8
UART0_TXD
End of enumeration elements list.
PH11MFP : PH.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PH.11
#0010 : 2
EBI_AD15
#0011 : 3
QSPI0_MOSI1
#0111 : 7
UART4_RXD
#1000 : 8
UART0_RXD
#1011 : 11
EPWM0_CH5
End of enumeration elements list.
Peripheral Reset Control Register 0
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIPRST : Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.\nAbout the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip normal operation
#1 : 1
Chip one-shot reset
End of enumeration elements list.
CPURST : Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Processor core normal operation
#1 : 1
Processor core one-shot reset
End of enumeration elements list.
PDMA0RST : PDMA0 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA0 (always secure) . User needs to set this bit to 0 to release from reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA0 controller normal operation
#1 : 1
PDMA0 controller reset
End of enumeration elements list.
EBIRST : EBI Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the EBI. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI controller normal operation
#1 : 1
EBI controller reset
End of enumeration elements list.
USBHRST : USB Host Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the USB Host. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB Host controller normal operation
#1 : 1
USB Host controller reset
End of enumeration elements list.
SDH0RST : SDHOST0 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the SDHOST0 controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
SDHOST0 controller normal operation
#1 : 1
SDHOST0 controller reset
End of enumeration elements list.
CRCRST : CRC Calculation Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
CRC calculation controller normal operation
#1 : 1
CRC calculation controller reset
End of enumeration elements list.
CRPTRST : CRYPTO Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the CRYPTO controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
CRYPTO controller normal operation
#1 : 1
CRYPTO controller reset
End of enumeration elements list.
PDMA1RST : PDMA1 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA1. User needs to set this bit to 0 to release from reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA1 controller normal operation
#1 : 1
PDMA1 controller reset
End of enumeration elements list.
GPIOA Multiple Function Output Select Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MFOS0 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS1 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS2 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS3 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS4 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS5 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS6 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS7 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS8 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS9 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS10 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS11 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS12 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS13 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS14 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS15 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
GPIOB Multiple Function Output Select Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOC Multiple Function Output Select Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOD Multiple Function Output Select Register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOE Multiple Function Output Select Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOF Multiple Function Output Select Register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOG Multiple Function Output Select Register
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOH Multiple Function Output Select Register
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Peripheral Reset Control Register 1
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIORST : GPIO Controller Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO controller normal operation
#1 : 1
GPIO controller reset
End of enumeration elements list.
TMR0RST : Timer0 Controller Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 controller normal operation
#1 : 1
Timer0 controller reset
End of enumeration elements list.
TMR1RST : Timer1 Controller Reset
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 controller normal operation
#1 : 1
Timer1 controller reset
End of enumeration elements list.
TMR2RST : Timer2 Controller Reset
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 controller normal operation
#1 : 1
Timer2 controller reset
End of enumeration elements list.
TMR3RST : Timer3 Controller Reset
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer3 controller normal operation
#1 : 1
Timer3 controller reset
End of enumeration elements list.
ACMP01RST : Analog Comparator 0/1 Controller Reset
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog Comparator 0/1 controller normal operation
#1 : 1
Analog Comparator 0/1 controller reset
End of enumeration elements list.
I2C0RST : I2C0 Controller Reset
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C0 controller normal operation
#1 : 1
I2C0 controller reset
End of enumeration elements list.
I2C1RST : I2C1 Controller Reset
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C1 controller normal operation
#1 : 1
I2C1 controller reset
End of enumeration elements list.
I2C2RST : I2C2 Controller Reset
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C2 controller normal operation
#1 : 1
I2C2 controller reset
End of enumeration elements list.
QSPI0RST : QSPI0 Controller Reset
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
QSPI0 controller normal operation
#1 : 1
QSPI0 controller reset
End of enumeration elements list.
SPI0RST : SPI0 Controller Reset
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI0 controller normal operation
#1 : 1
SPI0 controller reset
End of enumeration elements list.
SPI1RST : SPI1 Controller Reset
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI1 controller normal operation
#1 : 1
SPI1 controller reset
End of enumeration elements list.
SPI2RST : SPI2 Controller Reset
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI2 controller normal operation
#1 : 1
SPI2 controller reset
End of enumeration elements list.
UART0RST : UART0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 controller normal operation
#1 : 1
UART0 controller reset
End of enumeration elements list.
UART1RST : UART1 Controller Reset
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 controller normal operation
#1 : 1
UART1 controller reset
End of enumeration elements list.
UART2RST : UART2 Controller Reset
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART2 controller normal operation
#1 : 1
UART2 controller reset
End of enumeration elements list.
UART3RST : UART3 Controller Reset
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART3 controller normal operation
#1 : 1
UART3 controller reset
End of enumeration elements list.
UART4RST : UART4 Controller Reset
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART4 controller normal operation
#1 : 1
UART4 controller reset
End of enumeration elements list.
UART5RST : UART5 Controller Reset
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART5 controller normal operation
#1 : 1
UART5 controller reset
End of enumeration elements list.
CAN0RST : CAN0 Controller Reset
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
CAN0 controller normal operation
#1 : 1
CAN0 controller reset
End of enumeration elements list.
OTGRST : OTG Controller Reset
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
OTG controller normal operation
#1 : 1
OTG controller reset
End of enumeration elements list.
USBDRST : USBD Controller Reset
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
USBD controller normal operation
#1 : 1
USBD controller reset
End of enumeration elements list.
EADCRST : EADC Controller Reset
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
EADC controller normal operation
#1 : 1
EADC controller reset
End of enumeration elements list.
I2S0RST : I2S0 Controller Reset
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2S0 controller normal operation
#1 : 1
I2S0 controller reset
End of enumeration elements list.
TRNGRST : TRNG Controller Reset
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
TRNG controller normal operation
#1 : 1
TRNG controller reset
End of enumeration elements list.
System SRAM Interrupt Enable Control Register
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERRIEN : SRAM Parity Check Error Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SRAM parity check error interrupt Disabled
#1 : 1
SRAM parity check error interrupt Enabled
End of enumeration elements list.
System SRAM Parity Error Status Register
address_offset : 0xC4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERRIF : SRAM Parity Check Error Flag\nThis bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No System SRAM parity error
#1 : 1
System SRAM parity error occur
End of enumeration elements list.
System SRAM Parity Check Error Address Register
address_offset : 0xC8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERRADDR : System SRAM Parity Error Address\nThis register shows system SRAM parity error byte address.
bits : 0 - 31 (32 bit)
access : read-only
System SRAM Power Mode Control Register
address_offset : 0xDC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STACK : System SRAM Stack Position (Write Protect)\nThis field must config the system SRAM marco that first SRAM address accessed by CPU in power-on process.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 3 (4 bit)
access : read-write
RETCNT : SRAM Retention Count (Write Protect)\nThis field can config SRAM marco retention time in unit of HIRC period.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
one HIRC period
#01 : 1
two HIRC periods
#10 : 2
three HIRC periods
#11 : 3
four HIRC periods
End of enumeration elements list.
SRAM0PM0 : Bank0 SRAM Power Mode Select 0 (Write Protect)\nThis field can control bank0 sram (32k) power mode in system enter power down mode for range 0x2000_0000 - 0x2000_1FFF.\nNote1: Bank 0 SRAM is always operating in power shut down mode for system enter Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Normal mode
#01 : 1
Retention mode
#10 : 2
Power shut down mode
#11 : 3
Reserved (Write Ignore)
End of enumeration elements list.
SRAM0PM1 : Bank0 SRAM Power Mode Select 1 (Write Protect)\nThis field can control bank0 sram (32k) power mode in system enter power down mode for range 0x2000_2000 - 0x2000_3FFF.\nNote1: Bank 0 SRAM is always operating in power shut down mode for system enter Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Normal mode
#01 : 1
Retention mode
#10 : 2
Power shut down mode
#11 : 3
Reserved (Write Ignore)
End of enumeration elements list.
SRAM0PM2 : Bank0 SRAM Power Mode Select 2 (Write Protect)\nThis field can control bank0 sram (32k) power mode in system enter power down mode for range 0x2004_0000 - 0x2000_5FFF.\nNote1: Bank 0 SRAM is always operating in power shut down mode for system enter Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
Normal mode
#01 : 1
Retention mode
#10 : 2
Power shut down mode
#11 : 3
Reserved (Write Ignore)
End of enumeration elements list.
SRAM0PM3 : Bank0 SRAM Power Mode Select 3 (Write Protect)\nThis field can control bank0 sram (32k) power mode in system enter power down mode for range 0x2006_0000 - 0x2000_7FFF.\nNote1: Bank 0 SRAM is always operating in power shut down mode for system enter Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 0
Normal mode
#01 : 1
Retention mode
#10 : 2
Power shut down mode
#11 : 3
Reserved (Write Ignore)
End of enumeration elements list.
SRAM1PM0 : Bank1 SRAM Power Mode Select 0 (Write Protect)\nThis field can control bank1 sram (64k) power mode in system enter power down mode for range 0x2000_8000 - 0x2000_BFFF.\nNote1: Bank 1 SRAM is always operating in power shut down mode for system enter StandbyPower-down Mode (SPD) and Deep Power-down Mode (DPD). \nNote2: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Normal mode
#01 : 1
Retention mode
#10 : 2
Power shut down mode
#11 : 3
Reserved (Write Ignore)
End of enumeration elements list.
SRAM1PM1 : Bank1 SRAM Power Mode Select 1 (Write Protect)\nThis field can control bank1 sram (64k) power mode in system enter power down mode for range 0x2000_C000 - 0x2000_FFFF.\nNote1: Bank 1 SRAM is always operating in power shut down mode for system enter StandbyPower-down Mode (SPD) and Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
Normal mode
#01 : 1
Retention mode
#10 : 2
Power shut down mode
#11 : 3
Reserved (Write Ignore)
End of enumeration elements list.
SRAM1PM2 : Bank1 SRAM Power Mode Select 2 (Write Protect)\nThis field can control bank1 sram (64k) power mode in system enter power down mode for range 0x2001_0000 - 0x2001_3FFF.\nNote1: Bank 1 SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Normal mode
#01 : 1
Retention mode
#10 : 2
Power shut down mode
#11 : 3
Reserved (Write Ignore)
End of enumeration elements list.
SRAM1PM3 : Bank1 SRAM Power Mode Select 3 (Write Protect)\nThis field can control bank1 sram (64k) power mode in system enter power down mode for range 0x2001_4000 - 0x2001_7FFF.\nNote1: Bank 1 SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and Deep Power-down Mode (DPD).\nNote:2 Thiese bits are write protected. Refer to the SYS_REGLCTL register.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
Normal mode
#01 : 1
Retention mode
#10 : 2
Power shut down mode
#11 : 3
Reserved (Write Ignore)
End of enumeration elements list.
Peripheral SRAM Power Mode Control Register
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAN : CAN SRAM Power Mode Select (Write Protect)\nThis field can control CAN sram power mode for system enter power down mode.\nNote1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Normal mode
#01 : 1
Retention mode
#10 : 2
Power shut down mode
#11 : 3
Reserved.
End of enumeration elements list.
USBD : USB Device SRAM Power Mode Select (Write Protect)\nThis field can control USB device sram power mode for system enter power down mode.\nNote1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Normal mode
#01 : 1
Retention mode
#10 : 2
Power shut down mode
#11 : 3
Reserved (Write Ignore)
End of enumeration elements list.
PDMA0 : PDMA SRAM Power Mode Select (Write Protect)\nThis field can control PDMA0 (always secure) sram power mode for system enter power down mode.\nNote1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Normal mode
#01 : 1
Retention mode
#10 : 2
Power shut down mode
#11 : 3
Reserved (Write Ignore)
End of enumeration elements list.
PDMA1 : PDMA SRAM Power Mode Select (Write Protect)\nThis field can control PDMA1 sram power mode for system enter power down mode.\nNote1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Normal mode
#01 : 1
Retention mode
#10 : 2
Power shut down mode
#11 : 3
Reserved (Write Ignore)
End of enumeration elements list.
FMC : FMC SRAM Power Mode Select (Write Protect)\nThis field can control FMC cache sram power mode for system enter power down mode.\nNote1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and Deep Power-down Mode (DPD).\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Normal mode
#01 : 1
Retention mode
#10 : 2
Power shut down mode
#11 : 3
Reserved (Write Ignore)
End of enumeration elements list.
HIRC 48M Trim Control Register
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQSEL : Trim Frequency Selection\nThis field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Disable HIRC auto trim function
#01 : 1
Enable HIRC auto trim function and trim HIRC to 48 MHz
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
LOOPSEL : Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim value calculation is based on average difference in 4 clocks of reference clock
#01 : 1
Trim value calculation is based on average difference in 8 clocks of reference clock
#10 : 2
Trim value calculation is based on average difference in 16 clocks of reference clock
#11 : 3
Trim value calculation is based on average difference in 32 clocks of reference clock
End of enumeration elements list.
RETRYCNT : Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim retry count limitation is 64 loops
#01 : 1
Trim retry count limitation is 128 loops
#10 : 2
Trim retry count limitation is 256 loops
#11 : 3
Trim retry count limitation is 512 loops
End of enumeration elements list.
CESTOPEN : Clock Error Stop Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The trim operation is keep going if clock is inaccuracy
#1 : 1
The trim operation is stopped if clock is inaccuracy
End of enumeration elements list.
REFCKSEL : Reference Clock Selection
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
HIRC trim 48M reference clock is from external 32.768 kHz crystal oscillator
#1 : 1
HIRC trim 48M reference clock is from internal USB synchronous mode
End of enumeration elements list.
HIRC 48M Trim Interrupt Enable Register
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFAILIEN : Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_TCTL48M[1:0]).\nIf this bit is high and TFAILIF(SYS_TSTS48M [1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable TFAILIF(SYS_TISTS48M [1]) status to trigger an interrupt to CPU
#1 : 1
Enable TFAILIF(SYS_TISTS48M[1]) status to trigger an interrupt to CPU
End of enumeration elements list.
CLKEIEN : Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_TISTS48M [2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable CLKERRIF(SYS_TISTS48M [2]) status to trigger an interrupt to CPU
#1 : 1
Enable CLKERRIF(SYS_TISTS48M [2]) status to trigger an interrupt to CPU
End of enumeration elements list.
HIRC 48M Trim Interrupt Status Register
address_offset : 0xEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQLOCK : HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.\nWrite 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The internal high-speed oscillator frequency doesn't lock at 48 MHz yet
#1 : 1
The internal high-speed oscillator frequency locked at 48 MHz
End of enumeration elements list.
TFAILIF : Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_TCTL48M[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_TIEN48M[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trim value update limitation count does not reach
#1 : 1
Trim value update limitation count reached and HIRC frequency still not locked
End of enumeration elements list.
CLKERRIF : Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_TCTL48M[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_TCTL48M[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_TIEN48M[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock frequency is accuracy
#1 : 1
Clock frequency is inaccuracy
End of enumeration elements list.
HIRC 12M Trim Control Register
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQSEL : Trim Frequency Selection\nThis field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Disable HIRC auto trim function
#01 : 1
Enable HIRC auto trim function and trim HIRC to 12 MHz
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
LOOPSEL : Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim value calculation is based on average difference in 4 clocks of reference clock
#01 : 1
Trim value calculation is based on average difference in 8 clocks of reference clock
#10 : 2
Trim value calculation is based on average difference in 16 clocks of reference clock
#11 : 3
Trim value calculation is based on average difference in 32 clocks of reference clock
End of enumeration elements list.
RETRYCNT : Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim retry count limitation is 64 loops
#01 : 1
Trim retry count limitation is 128 loops
#10 : 2
Trim retry count limitation is 256 loops
#11 : 3
Trim retry count limitation is 512 loops
End of enumeration elements list.
CESTOPEN : Clock Error Stop Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The trim operation is keep going if clock is inaccuracy
#1 : 1
The trim operation is stopped if clock is inaccuracy
End of enumeration elements list.
REFCKSEL : Reference Clock Selection
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
HIRC trim reference clock is from external 32.768 kHz crystal oscillator
#1 : 1
HIRC trim reference clock is from internal USB synchronous mode
End of enumeration elements list.
HIRC 12M Trim Interrupt Enable Register
address_offset : 0xF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFAILIEN : Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_TCTL12M[1:0]).\nIf this bit is high and TFAILIF(SYS_TSTS12M[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable TFAILIF(SYS_TISTS12M[1]) status to trigger an interrupt to CPU
#1 : 1
Enable TFAILIF(SYS_TISTS12M[1]) status to trigger an interrupt to CPU
End of enumeration elements list.
CLKEIEN : Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_TISTS12M[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable CLKERRIF(SYS_TISTS12M[2]) status to trigger an interrupt to CPU
#1 : 1
Enable CLKERRIF(SYS_TISTS12M[2]) status to trigger an interrupt to CPU
End of enumeration elements list.
HIRC 12M Trim Interrupt Status Register
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQLOCK : HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.\nWrite 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The internal high-speed oscillator frequency doesn't lock at 12 MHz yet
#1 : 1
The internal high-speed oscillator frequency locked at 12 MHz
End of enumeration elements list.
TFAILIF : Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_TCTL12M[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_TIEN12M[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trim value update limitation count does not reach
#1 : 1
Trim value update limitation count reached and HIRC frequency still not locked
End of enumeration elements list.
CLKERRIF : Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_TCTL12M[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_TCTL12M[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock frequency is accuracy
#1 : 1
Clock frequency is inaccuracy
End of enumeration elements list.
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