\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
NMI Source Interrupt Enable Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BODOUT : BOD NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
BOD NMI source Disabled
#1 : 1
BOD NMI source Enabled
End of enumeration elements list.
IRCINT : IRC TRIM NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
IRC TRIM NMI source Disabled
#1 : 1
IRC TRIM NMI source Enabled
End of enumeration elements list.
PWRWUINT : Power-down Mode Wake-up NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power-down mode wake-up NMI source Disabled
#1 : 1
Power-down mode wake-up NMI source Enabled
End of enumeration elements list.
SRAMPERR : SRAM Parity Check Error NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
SRAM parity check error NMI source Disabled
#1 : 1
SRAM parity check error NMI source Enabled
End of enumeration elements list.
CLKFAIL : Clock Fail Detected NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock fail detected interrupt NMI source Disabled
#1 : 1
Clock fail detected interrupt NMI source Enabled
End of enumeration elements list.
RTCINT : RTC NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC NMI source Disabled
#1 : 1
RTC NMI source Enabled
End of enumeration elements list.
TAMPERINT : Tamper Interrupt NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Backup register tamper detected interrupt NMI source Disabled
#1 : 1
Backup register tamper detected interrupt NMI source Enabled
End of enumeration elements list.
EINT0 : External Interrupt From PA.6, or PB.5 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
External interrupt from PA.6, or PB.5 pin NMI source Disabled
#1 : 1
External interrupt from PA.6, or PB.5 pin NMI source Enabled
End of enumeration elements list.
EINT1 : External Interrupt From PA.7 or PB.4 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
External interrupt from PA.7 or PB.4 pin NMI source Disabled
#1 : 1
External interrupt from PA.7 or P4.4 pin NMI source Enabled
End of enumeration elements list.
EINT2 : External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
External interrupt from PB.3 or PC.6 pin NMI source Disabled
#1 : 1
External interrupt from PB.3 or PC.6 pin NMI source Enabled
End of enumeration elements list.
EINT3 : External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
External interrupt from PB.2 or PC.7pin NMI source Disabled
#1 : 1
External interrupt from PB.2 or PC.7 pin NMI source Enabled
End of enumeration elements list.
EINT4 : External Interrupt From PA.8 or PB.6 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
External interrupt from PA.8 or PB.6 pin NMI source Disabled
#1 : 1
External interrupt from PA.8 or PB.6 pin NMI source Enabled
End of enumeration elements list.
EINT5 : External Interrupt From PB.7 or PD.12 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
External interrupt from PB.7 or PD.12 pin NMI source Disabled
#1 : 1
External interrupt from PB.7 or PD.12 pin NMI source Enabled
End of enumeration elements list.
UART0INT : UART0 NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 NMI source Disabled
#1 : 1
UART0 NMI source Enabled
End of enumeration elements list.
UART1INT : UART1 NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 NMI source Disabled
#1 : 1
UART1 NMI source Enabled
End of enumeration elements list.
EINT6 : External Interrupt From PB.8 or PD.11 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
External interrupt from PB.8 or PD.11 pin NMI source Disabled
#1 : 1
External interrupt from PB.8 or PD.11 pin NMI source Enabled
End of enumeration elements list.
EINT7 : External Interrupt From PB.9 or PD.10 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
External interrupt from PB.9 or PD.10 pin NMI source Disabled
#1 : 1
External interrupt from PB.9 or PD.10 pin NMI source Enabled
End of enumeration elements list.
NMI Source Interrupt Status Register
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BODOUT : BOD Interrupt Flag (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
BOD interrupt is deasserted
#1 : 1
BOD interrupt is asserted
End of enumeration elements list.
IRCINT : IRC TRIM Interrupt Flag (Read Only)
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
HIRC TRIM interrupt is deasserted
#1 : 1
HIRC TRIM interrupt is asserted
End of enumeration elements list.
PWRWUINT : Power-down Mode Wake-up Interrupt Flag (Read Only)
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Power-down mode wake-up interrupt is deasserted
#1 : 1
Power-down mode wake-up interrupt is asserted
End of enumeration elements list.
SRAMPERR : SRAM ParityCheck Error Interrupt Flag (Read Only)
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
SRAM parity check error interrupt is deasserted
#1 : 1
SRAM parity check error interrupt is asserted
End of enumeration elements list.
CLKFAIL : Clock Fail Detected Interrupt Flag (Read Only)
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Clock fail detected interrupt is deasserted
#1 : 1
Clock fail detected interrupt is asserted
End of enumeration elements list.
RTCINT : RTC Interrupt Flag (Read Only)
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
RTC interrupt is deasserted
#1 : 1
RTC interrupt is asserted
End of enumeration elements list.
TAMPERINT : Tamper Interrupt Flag (Read Only)
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Backup register tamper detected interrupt is deasserted
#1 : 1
Backup register tamper detected interrupt is asserted
End of enumeration elements list.
EINT0 : External Interrupt From PA.6, or PB.5 Pin Interrupt Flag (Read Only)
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
External Interrupt from PA.6, or PB.5 interrupt is deasserted
#1 : 1
External Interrupt from PA.6, or PB.5 interrupt is asserted
End of enumeration elements list.
EINT1 : External Interrupt From PA.7, or PB.4 Pin Interrupt Flag (Read Only)
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
External Interrupt from PA.7, or PB.4 interrupt is deasserted
#1 : 1
External Interrupt from PA.7, or PB.4 interrupt is asserted
End of enumeration elements list.
EINT2 : External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only)
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
External Interrupt from PB.3 or PC.6 interrupt is deasserted
#1 : 1
External Interrupt from PB.3 or PC.6 interrupt is asserted
End of enumeration elements list.
EINT3 : External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only)
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
External Interrupt from PB.2 or PC.7 interrupt is deasserted
#1 : 1
External Interrupt from PB.2 or PC.7 interrupt is asserted
End of enumeration elements list.
EINT4 : External Interrupt From PA.8 or PB.6 Pin Interrupt Flag (Read Only)
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
External Interrupt from PA.8 or PB.6 interrupt is deasserted
#1 : 1
External Interrupt from PA.8 or PB.6 interrupt is asserted
End of enumeration elements list.
EINT5 : External Interrupt From PB.7 or PD.12 Pin Interrupt Flag (Read Only)
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
External Interrupt from PB.7 or PD.12 interrupt is deasserted
#1 : 1
External Interrupt from PB.7 or PD.12 interrupt is asserted
End of enumeration elements list.
UART0INT : UART0 Interrupt Flag (Read Only)
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
UART1 interrupt is deasserted
#1 : 1
UART1 interrupt is asserted
End of enumeration elements list.
UART1INT : UART1 Interrupt Flag (Read Only)
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
UART1 interrupt is deasserted
#1 : 1
UART1 interrupt is asserted
End of enumeration elements list.
EINT6 : External Interrupt From PB.8 or PD.11 Pin Interrupt Flag (Read Only)
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
External Interrupt from PB.8 or PD.11 interrupt is deasserted
#1 : 1
External Interrupt from PB.8 or PD.11 interrupt is asserted
End of enumeration elements list.
EINT7 : External Interrupt From PB.9 or PD.10 Pin Interrupt Flag (Read Only)
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
External Interrupt from PB.9 or PD.10 interrupt is deasserted
#1 : 1
External Interrupt from PB.9 or PD.10 interrupt is asserted
End of enumeration elements list.
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