Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x60 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x70 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x90 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x9C Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
System Power-down Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTEN : HXT Enable Bit (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: HXT cannot be disabled and HXTEN will always read as 1 if HCLK clock source is selected from HXT or PLL (clock source from HXT).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
4~24 MHz external high speed crystal (HXT) Disabled
#1 : 1
4~24 MHz external high speed crystal (HXT) Enabled
End of enumeration elements list.
LXTEN : LXT Enable Bit (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: LXT cannot be disabled and LXTEN will always read as 1 if HCLK clock source is selected from LXT when the LXT clock source is selected as extLXT by setting C32KS(RTC_LXTCTL[7]) to 1.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
32.768 kHz external low speed crystal (extLXT) Disabled
#1 : 1
32.768 kHz external low speed crystal (extLXT) Enabled
End of enumeration elements list.
HIRCEN : HIRC Enable Bit (Write Protect)\nThe HCLK default clock source is from HIRC and this bit default value is 1.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: HIRC cannot be disabled and HIRCEN will always read as 1 if Flash access cycle auto-tuning function is enabled or HCLK clock source is selected from HIRC or PLL (clock source from HIRC). Flash access cycle auto-tuning function can be disabled by setting FADIS (FMC_CYCCTL[8]).
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
12 MHz internal high speed RC oscillator (HIRC) Disabled
#1 : 1
12 MHz internal high speed RC oscillator (HIRC) Enabled
End of enumeration elements list.
LIRCEN : LIRC Enable Bit (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: LIRC cannot be disabled and LIRCEN will always read as 1 if HCLK clock source is selected from LIRC.\nNote3: If CWDTEN(CONFIG[31,4:3]) is set to 111, LIRC clock can be enabled or disabled by setting LIRCEN(CLK_PWRCTL[3]).\nIf CWDTEN([31,4:3]) is not set to 111, LIRC cannot be disabled in normal mode. In Power-down mode, LIRC clock is controlled by LIRCEN(CLK_PWRCTL[3]) and CWDTPDEN(CONFIG[30]) setting.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
10 kHz internal low speed RC oscillator (LIRC) Disabled
#1 : 1
10 kHz internal low speed RC oscillator (LIRC) Enabled
End of enumeration elements list.
PDWKIEN : Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote1: The interrupt will occur when both PDWKIF and PDWKIEN are high, after resume from Power-down mode.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power-down mode wake-up interrupt Disabled
#1 : 1
Power-down mode wake-up interrupt Enabled
End of enumeration elements list.
PDWKIF : Power-down Mode Wake-up Interrupt Status\nSet by 'Power-down wake-up event', it indicates that resume from Power-down mode' \nThe flag is set if the EINT7~0, GPIO, UART0~5, USBH, USBD, OTG, CAN0, BOD, ACMP, WDT, SDH0, TMR0~3, I2C0~2, USCI0~1, SPI4, , RTC wake-up occurred.\nNote1: Write 1 to clear the bit to 0.\nNote2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
bits : 6 - 6 (1 bit)
access : read-write
PDEN : System Power-down Enable (Write Protect)\nWhen this bit is set to 1, Power-down mode is enabled and the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.\nWhen chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down.\nIn Power-down mode, HXT, HIRC, HIRC48, PLL and system clock will be disabled and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip operating normally or chip in idle mode because of WFI command
#1 : 1
Chip waits CPU sleep command WFI and then enters Power-down mode
End of enumeration elements list.
HXTGAIN : HXT Gain Control Bit (Write Protect)\nGain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off. \nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
HXT frequency is lower than from 8 MHz
#01 : 1
HXT frequency is from 8 MHz to 12 MHz
#10 : 2
HXT frequency is from 12 MHz to 16 MHz
#11 : 3
HXT frequency is higher than 16 MHz
End of enumeration elements list.
HXTSELTYP : HXT Crystal Type Select Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Select INV type
#1 : 1
Select GM type
End of enumeration elements list.
HXTTBEN : HXT Crystal TURBO Mode (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
HXT Crystal TURBO mode disabled
#1 : 1
HXT Crystal TURBO mode enabled
End of enumeration elements list.
HIRC48EN : HIRC48 Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
48 MHz internal high speed RC oscillator (HIRC48) Disabled
#1 : 1
48 MHz internal high speed RC oscillator (HIRC48) Enabled
End of enumeration elements list.
Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKSEL : HCLK Clock Source Selection (Write Protect)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turned on.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HXT
#001 : 1
Clock source from LXT
#010 : 2
Clock source from PLL
#011 : 3
Clock source from LIRC
#100 : 4
Reserved.
#101 : 5
Clock source from HIRC48
#111 : 7
Clock source from HIRC
End of enumeration elements list.
STCLKSEL : SysTick Clock Source Selection (Write Protect)\nNote2: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HXT
#001 : 1
Clock source from LXT
#010 : 2
Clock source from HXT/2
#011 : 3
Clock source from HCLK/2
#111 : 7
Clock source from HIRC/2
End of enumeration elements list.
USBSEL : USB Clock Source Selection (Write Protect)
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reserved.
#1 : 1
Clock source from PLL
End of enumeration elements list.
SDH0SEL : SDHOST0 Peripheral Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from HXT clock
#01 : 1
Clock source from PLL clock
#10 : 2
Clock source from HCLK
#11 : 3
Clock source from HIRC clock
End of enumeration elements list.
Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTSEL : Watchdog Timer Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved.
#01 : 1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#10 : 2
Clock source from HCLK/2048
#11 : 3
Clock source from 10 kHz internal low speed RC oscillator (LIRC)
End of enumeration elements list.
TMR0SEL : TIMER0 Clock Source Selection
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT)
#001 : 1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK0
#011 : 3
Clock source from external clock TM0 pin
#101 : 5
Clock source from 10 kHz internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from 12 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
TMR1SEL : TIMER1 Clock Source Selection
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT)
#001 : 1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK0
#011 : 3
Clock source from external clock TM1 pin
#101 : 5
Clock source from 10 kHz internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from 12 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
TMR2SEL : TIMER2 Clock Source Selection
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT)
#001 : 1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK1
#011 : 3
Clock source from external clock TM2 pin
#101 : 5
Clock source from 10 kHz internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from 12 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
TMR3SEL : TIMER3 Clock Source Selection
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT)
#001 : 1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK1
#011 : 3
Clock source from external clock TM3 pin
#101 : 5
Clock source from 10 kHz internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from 12 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
UART0SEL : UART0 Clock Source Selection
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#11 : 3
Clock source from 12 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
UART1SEL : UART1 Clock Source Selection
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#11 : 3
Clock source from 12 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
CLKOSEL : Clock Output Clock Source Selection
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT)
#01 : 1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#10 : 2
Clock source from HCLK
#11 : 3
Clock source from 12 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
WWDTSEL : Window Watchdog Timer Clock Source Selection (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#10 : 2
Clock source from HCLK/2048
#11 : 3
Clock source from 10 kHz internal low speed RC oscillator (LIRC)
End of enumeration elements list.
Clock Source Select Control Register 2
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM0SEL : EPWM0 Clock Source Selection (Read Only)\nThe peripheral clock source of EPWM0 is defined by EPWM0SEL.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#1 : 1
Clock source from PCLK0
End of enumeration elements list.
EPWM1SEL : EPWM1 Clock Source Selection (Read Only)\nThe peripheral clock source of EPWM1 is defined by EPWM1SEL.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#1 : 1
Clock source from PCLK1
End of enumeration elements list.
QSPI0SEL : QSPI0 Clock Source Selection
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from PCLK0
#11 : 3
Clock source from 12 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
SPI0SEL : SPI0 Clock Source Selection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from PCLK1
#11 : 3
Clock source from 12 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
SPI1SEL : SPI1 Clock Source Selection
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from PCLK0
#11 : 3
Clock source from 12 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
BPWM0SEL : BPWM0 Clock Source Selection (Read Only)\nThe peripheral clock source of BPWM0 is defined by BPWM0SEL.
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#1 : 1
Clock source from PCLK0
End of enumeration elements list.
BPWM1SEL : BPWM1 Clock Source Selection (Read Only)\nThe peripheral clock source of BPWM1 is defined by BPWM1SEL.
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#1 : 1
Clock source from PCLK1
End of enumeration elements list.
SPI2SEL : SPI2 Clock Source Selection
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from PCLK1
#11 : 3
Clock source from 12 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
SPI3SEL : SPI3 Clock Source Selection
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from PCLK0
#11 : 3
Clock source from 12 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
Clock Source Select Control Register 3
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SC0SEL : Smart Card 0 (SC0) Clock Source Selection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from PCLK0
#11 : 3
Clock source from 12 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
SC1SEL : Smart Card 1 (SC1) Clock Source Selection
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from PCLK1
#11 : 3
Clock source from 12 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
SC2SEL : Smart Card 2 (SC2) Clock Source Selection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from PCLK0
#11 : 3
Clock source from 12 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
RTCSEL : RTC Clock Source Selection
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#1 : 1
Clock source from 10 kHz internal low speed RC oscillator (LIRC)
End of enumeration elements list.
I2S0SEL : I2S0 Clock Source Selection
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from HXT clock
#01 : 1
Clock source from PLL clock
#10 : 2
Clock source from PCLK0
#11 : 3
Clock source from HIRC clock
End of enumeration elements list.
UART2SEL : UART2 Clock Source Selection
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#11 : 3
Clock source from 12 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
UART3SEL : UART3 Clock Source Selection
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#11 : 3
Clock source from 12 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
UART4SEL : UART4 Clock Source Selection
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#11 : 3
Clock source from 12 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
UART5SEL : UART5 Clock Source Selection
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from 4~24 MHz external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#11 : 3
Clock source from 12 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
Clock Divider Number Register 0
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source
bits : 0 - 3 (4 bit)
access : read-write
USBDIV : USB Clock Divide Number From PLL Clock
bits : 4 - 7 (4 bit)
access : read-write
UART0DIV : UART0 Clock Divide Number From UART0 Clock Source
bits : 8 - 11 (4 bit)
access : read-write
UART1DIV : UART1 Clock Divide Number From UART1 Clock Source
bits : 12 - 15 (4 bit)
access : read-write
EADCDIV : EADC Clock Divide Number From EADC Clock Source
bits : 16 - 23 (8 bit)
access : read-write
SDH0DIV : SDHOST0 Clock Divide Number From SDHOST0 Clock Source
bits : 24 - 31 (8 bit)
access : read-write
Clock Divider Number Register 1
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SC0DIV : Smart Card 0 (SC0) Clock Divide Number From SC0 Clock Source
bits : 0 - 7 (8 bit)
access : read-write
SC1DIV : Smart Card 1 (SC1) Clock Divide Number From SC1 Clock Source
bits : 8 - 15 (8 bit)
access : read-write
SC2DIV : Smart Card 2 (SC2) Clock Divide Number From SC2 Clock Source
bits : 16 - 23 (8 bit)
access : read-write
Clock Divider Number Register 4
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART2DIV : UART2 Clock Divide Number From UART2 Clock Source
bits : 0 - 3 (4 bit)
access : read-write
UART3DIV : UART3 Clock Divide Number From UART3 Clock Source
bits : 4 - 7 (4 bit)
access : read-write
UART4DIV : UART4 Clock Divide Number From UART4 Clock Source
bits : 8 - 11 (4 bit)
access : read-write
UART5DIV : UART5 Clock Divide Number From UART5 Clock Source
bits : 12 - 15 (4 bit)
access : read-write
APB Clock Divider Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APB0DIV : APB0 Clock Divider\nAPB0 clock can be divided from HCLK
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
PCLK0 frequency is HCLK
#001 : 1
PCLK0 frequency is 1/2 HCLK
#010 : 2
PCLK0 frequency is 1/4 HCLK
#011 : 3
PCLK0 frequency is 1/8 HCLK
#100 : 4
PCLK0 frequency is 1/16 HCLK
#101 : 5
PCLK0 frequency is 1/32 HCLK
End of enumeration elements list.
APB1DIV : APB1 Clock Divider\nAPB1 clock can be divided from HCLK
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 0
PCLK1 frequency is HCLK
#001 : 1
PCLK1 frequency is 1/2 HCLK
#010 : 2
PCLK1 frequency is 1/4 HCLK
#011 : 3
PCLK1 frequency is 1/8 HCLK
#100 : 4
PCLK1 frequency is 1/16 HCLK
#101 : 5
PCLK1 frequency is 1/32 HCLK
End of enumeration elements list.
AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA0CKEN : PDMA0 Controller Clock Enable Bit (Secure)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA0 peripheral clock Disabled
#1 : 1
PDMA0 peripheral clock Enabled
End of enumeration elements list.
PDMA1CKEN : PDMA1 Controller Clock Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA1 peripheral clock Disabled
#1 : 1
PDMA1 peripheral clock Enabled
End of enumeration elements list.
ISPCKEN : Flash ISP Controller Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash ISP peripheral clock Disabled
#1 : 1
Flash ISP peripheral clock Enabled
End of enumeration elements list.
EBICKEN : EBI Controller Clock Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI peripheral clock Disabled
#1 : 1
EBI peripheral clock Enabled
End of enumeration elements list.
SDH0CKEN : SDHOST0 Controller Clock Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
SDHOST0 peripheral clock Disabled
#1 : 1
SDHOST0 peripheral clock Enabled
End of enumeration elements list.
CRCCKEN : CRC Generator Controller Clock Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
CRC peripheral clock Disabled
#1 : 1
CRC peripheral clock Enabled
End of enumeration elements list.
CRPTCKEN : Cryptographic Accelerator Clock Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Cryptographic Accelerator clock Disabled
#1 : 1
Cryptographic Accelerator clock Enabled
End of enumeration elements list.
FMCIDLE : Flash Memory Controller Clock Enable Bit in IDLE Mode
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
FMC clock Disabled when chip is under IDLE mode
#1 : 1
FMC clock Enabled when chip is under IDLE mode
End of enumeration elements list.
USBHCKEN : USB HOST 1.1 Controller Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB HOST 1.1 peripheral clock Disabled
#1 : 1
USB HOST 1.1 peripheral clock Enabled
End of enumeration elements list.
PLL Control Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBDIV : PLL Feedback Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 8 (9 bit)
access : read-write
INDIV : PLL Input Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 9 - 13 (5 bit)
access : read-write
OUTDIV : PLL Output Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 14 - 15 (2 bit)
access : read-write
PD : Power-down Mode (Write Protect)\nNote1: If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is enable (in normal mode)
#1 : 1
PLL is disable (in Power-down mode) (default)
End of enumeration elements list.
BP : PLL Bypass Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is in normal mode (default)
#1 : 1
PLL clock output is same as PLL input clock FIN
End of enumeration elements list.
OE : PLL OE (FOUT Enable) Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL FOUT Enabled
#1 : 1
PLL FOUT is fixed low
End of enumeration elements list.
PLLSRC : PLL Source Clock Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT)
#1 : 1
PLL source clock from 12 MHz internal high-speed oscillator (HIRC)
End of enumeration elements list.
STBSEL : PLL Stable Counter Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL stable time is 1200 PLL source clock (suitable for source clock is equal to or less than 12 MHz)
#1 : 1
PLL stable time is 2400 PLL source clock (suitable for source clock is larger than 12 MHz)
End of enumeration elements list.
Clock Status Monitor Register
address_offset : 0x50 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HXTSTB : HXT Clock Source Stable Flag (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled
#1 : 1
4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled
End of enumeration elements list.
LXTSTB : LXT Clock Source Stable Flag (Read Only)\nLXT clock source can be selected as extLXT or LIRC32 by setting C32KS(RTC_LXTCTL[7]). If C32KS is set to 0, the LXT stable flag is set when extLXT clock source is stable. If C32KS is set to 1, the LXT stable flag is set when LIRC32 clock source is stable.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled
#1 : 1
32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled
End of enumeration elements list.
PLLSTB : Internal PLL Clock Source Stable Flag (Read Only)
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal PLL clock is not stable or disabled
#1 : 1
Internal PLL clock is stable and enabled
End of enumeration elements list.
LIRCSTB : LIRC Clock Source Stable Flag (Read Only)
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled
#1 : 1
10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled
End of enumeration elements list.
HIRCSTB : HIRC Clock Source Stable Flag (Read Only)
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled
#1 : 1
12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled
End of enumeration elements list.
HIRC48STB : HIRC48 Clock Source Stable Flag (Read Only)
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
48 MHz internal high speed RC oscillator (HIRC48) clock is not stable or disabled
#1 : 1
48 MHz internal high speed RC oscillator (HIRC48) clock is stable and enabled
End of enumeration elements list.
CLKSFAIL : Clock Switching Fail Flag (Read Only) \nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nNote: This bit is read only. After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Clock switching success
#1 : 1
Clock switching failure
End of enumeration elements list.
EXTLXTSTB : EXTLXT Clock Source Stable Flag (Read Only)
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
32.768 kHz external low speed crystal oscillator (extLXT) clock is not stable or disabled
#1 : 1
32.768 kHz external low speed crystal oscillator (extLXT) clock is stable and enabled
End of enumeration elements list.
LIRC32STB : LIRC32 Clock Source Stable Flag (Read Only)
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
32 kHz internal low speed RC oscillator (LIRC32) clock is not stable or disabled
#1 : 1
32 kHz internal low speed RC oscillator (LIRC32) clock is stable and enabled
End of enumeration elements list.
Clock Output Control Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQSEL : Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write
CLKOEN : Clock Output Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Output function Disabled
#1 : 1
Clock Output function Enabled
End of enumeration elements list.
DIV1EN : Clock Output Divide One Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Output will output clock with source frequency divided by FREQSEL
#1 : 1
Clock Output will output clock with source frequency
End of enumeration elements list.
CLK1HZEN : Clock Output 1Hz Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
1 Hz clock output for 32.768 kHz frequency compensation Disabled
#1 : 1
1 Hz clock output for 32.768 kHz frequency compensation Enabled
End of enumeration elements list.
Clock Fail Detector Control Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTFDEN : HXT Clock Fail Detector Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled
#1 : 1
4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled
End of enumeration elements list.
HXTFIEN : HXT Clock Fail Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled
#1 : 1
4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled
End of enumeration elements list.
LXTFDEN : LXT Clock Fail Detector Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled
#1 : 1
32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled
End of enumeration elements list.
LXTFIEN : LXT Clock Fail Interrupt Enable Bit
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled
#1 : 1
32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled
End of enumeration elements list.
HXTFQDEN : HXT Clock Frequency Monitor Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Disabled
#1 : 1
4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Enabled
End of enumeration elements list.
HXTFQIEN : HXT Clock Frequency Monitor Interrupt Enable Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Disabled
#1 : 1
4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Enabled
End of enumeration elements list.
Clock Fail Detector Status Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTFIF : HXT Clock Fail Interrupt Flag (Write Protect)\nNote1: Write 1 to clear the bit to 0.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
4~24 MHz external high speed crystal oscillator (HXT) clock is normal
#1 : 1
4~24 MHz external high speed crystal oscillator (HXT) clock stops
End of enumeration elements list.
LXTFIF : LXT Clock Fail Interrupt Flag (Write Protect)\nNote1: Write 1 to clear the bit to 0. \nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
32.768 kHz external low speed crystal oscillator (LXT) clock is normal
#1 : 1
32.768 kHz external low speed crystal oscillator (LXT) stops
End of enumeration elements list.
HXTFQIF : HXT Clock Frequency Monitor Interrupt Flag (Write Protect)\nNote1: Write 1 to clear the bit to 0.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
4~24 MHz external high speed crystal oscillator (HXT) clock is normal
#1 : 1
4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal
End of enumeration elements list.
Clock Frequency Detector Upper Boundary Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPERBD : HXT Clock Frequency Detector Upper Boundary\nThe bits define the high value of frequency monitor window.\nWhen HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1.
bits : 0 - 9 (10 bit)
access : read-write
Clock Frequency Detector Lower Boundary Register
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOWERBD : HXT Clock Frequency Detector Lower Boundary\nThe bits define the low value of frequency monitor window.\nWhen HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1.
bits : 0 - 9 (10 bit)
access : read-write
APB Devices Clock Enable Control Register 0
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTCKEN : Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog timer clock Disabled
#1 : 1
Watchdog timer clock Enabled
End of enumeration elements list.
RTCCKEN : Real-time-clock APB Interface Clock Enable Bit\nThis bit is used to control the RTC APB clock only. The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]). It can be selected to 32.768 kHz external low speed crystal (LXT) or 10 kHz internal low speed RC oscillator (LIRC).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC clock Disabled
#1 : 1
RTC clock Enabled
End of enumeration elements list.
TMR0CKEN : Timer0 Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 clock Disabled
#1 : 1
Timer0 clock Enabled
End of enumeration elements list.
TMR1CKEN : Timer1 Clock Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 clock Disabled
#1 : 1
Timer1 clock Enabled
End of enumeration elements list.
TMR2CKEN : Timer2 Clock Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 clock Disabled
#1 : 1
Timer2 clock Enabled
End of enumeration elements list.
TMR3CKEN : Timer3 Clock Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer3 clock Disabled
#1 : 1
Timer3 clock Enabled
End of enumeration elements list.
CLKOCKEN : CLKO Clock Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
CLKO clock Disabled
#1 : 1
CLKO clock Enabled
End of enumeration elements list.
ACMP01CKEN : Analog Comparator 0/1 Clock Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog comparator 0/1 clock Disabled
#1 : 1
Analog comparator 0/1 clock Enabled
End of enumeration elements list.
I2C0CKEN : I2C0 Clock Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C0 clock Disabled
#1 : 1
I2C0 clock Enabled
End of enumeration elements list.
I2C1CKEN : I2C1 Clock Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C1 clock Disabled
#1 : 1
I2C1 clock Enabled
End of enumeration elements list.
I2C2CKEN : I2C2 Clock Enable Bit
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C2 clock Disabled
#1 : 1
I2C2 clock Enabled
End of enumeration elements list.
QSPI0CKEN : QSPI0 Clock Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
QSPI0 clock Disabled
#1 : 1
QSPI0 clock Enabled
End of enumeration elements list.
SPI0CKEN : SPI0 Clock Enable Bit
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI0 clock Disabled
#1 : 1
SPI0 clock Enabled
End of enumeration elements list.
SPI1CKEN : SPI1 Clock Enable Bit
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI1 clock Disabled
#1 : 1
SPI1 clock Enabled
End of enumeration elements list.
SPI2CKEN : SPI2 Clock Enable Bit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI2 clock Disabled
#1 : 1
SPI2 clock Enabled
End of enumeration elements list.
UART0CKEN : UART0 Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 clock Disabled
#1 : 1
UART0 clock Enabled
End of enumeration elements list.
UART1CKEN : UART1 Clock Enable Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 clock Disabled
#1 : 1
UART1 clock Enabled
End of enumeration elements list.
UART2CKEN : UART2 Clock Enable Bit
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART2 clock Disabled
#1 : 1
UART2 clock Enabled
End of enumeration elements list.
UART3CKEN : UART3 Clock Enable Bit
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART3 clock Disabled
#1 : 1
UART3 clock Enabled
End of enumeration elements list.
UART4CKEN : UART4 Clock Enable Bit
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART4 clock Disabled
#1 : 1
UART4 clock Enabled
End of enumeration elements list.
UART5CKEN : UART5 Clock Enable Bit
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART5 clock Disabled
#1 : 1
UART5 clock Enabled
End of enumeration elements list.
CAN0CKEN : CAN0 Clock Enable Bit
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
CAN0 clock Disabled
#1 : 1
CAN0 clock Enabled
End of enumeration elements list.
OTGCKEN : USB OTG Clock Enable Bit
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB OTG clock Disabled
#1 : 1
USB OTG clock Enabled
End of enumeration elements list.
USBDCKEN : USB Device Clock Enable Bit
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB Device clock Disabled
#1 : 1
USB Device clock Enabled
End of enumeration elements list.
EADCCKEN : Enhanced Analog-digital-converter (EADC) Clock Enable Bit
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
EADC clock Disabled
#1 : 1
EADC clock Enabled
End of enumeration elements list.
I2S0CKEN : I2S0 Clock Enable Bit
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2S0 Clock Disabled
#1 : 1
I2S0 Clock Enabled
End of enumeration elements list.
Power Manager Control Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMSEL : Power-down Mode Selection (Write Protect)\nThese bits control chip Power-down mode grade selection when CPU executes WFI/WFE instruction.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Power-down mode is selected (PD)
#001 : 1
Low leakage Power-down mode is selected (LLPD)
#010 : 2
Fast wake-up Power-down (FWPD)
#011 : 3
Ultra low leakage Power-down mode is selected (ULLPD)
#100 : 4
Standby Power-down mode is selected (SPD)
#101 : 5
Reserved.
#110 : 6
Deep Power-down mode is selected (DPD)
#111 : 7
Reserved.
End of enumeration elements list.
WKTMREN : Wake-up Timer Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake-up timer disabled at Deep Power-down mode or Standby Power-down mode
#1 : 1
Wake-up timer enabled at Deep Power-down mode or Standby Power-down mode
End of enumeration elements list.
WKTMRIS : Wake-up Timer Time-out Interval Select (Write Protect)\nThese bits control wake-up timer time-out interval when chip is under Deep Power-down mode or Standby Power-down mode.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
#000 : 0
Time-out interval is 128 OSC10K clocks (12.8ms)
#001 : 1
Time-out interval is 256 OSC10K clocks (25.6ms)
#010 : 2
Time-out interval is 512 OSC10K clocks (51.2ms)
#011 : 3
Time-out interval is 1024 OSC10K clocks (102.4ms)
#100 : 4
Time-out interval is 4096 OSC10K clocks (409.6ms)
#101 : 5
Time-out interval is 8192 OSC10K clocks (819.2ms)
#110 : 6
Time-out interval is 16384 OSC10K clocks (1638.4ms)
#111 : 7
Time-out interval is 65536 OSC10K clocks (6553.6ms)
End of enumeration elements list.
WKPINEN : Wake-up Pin Enable (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Wake-up pin Disabled in Deep Power-down mode
#01 : 1
Wake-up pin rising edge Enabled in Deep Power-down mode
#10 : 2
Wake-up pin falling edge Enabled in Deep Power-down mode
#11 : 3
Wake-up pin both edge Enabled in Deep Power-down mode
End of enumeration elements list.
ACMPSPWK : ACMP Standby Power-down Mode Wake-up Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP wake-up Disabled in Standby Power-down mode
#1 : 1
ACMP wake-up Enabled in Standby Power-down mode
End of enumeration elements list.
RTCWKEN : RTC Wake-up Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC wake-up Disabled in Deep Power-down mode or Standby Power-down mode
#1 : 1
RTC wake-up Enabled at Deep Power-down mode or Standby Power-down mode
End of enumeration elements list.
Power Manager Status Register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PINWK : Pin Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPC.0). This flag is cleared when DPD mode is entered.
bits : 0 - 0 (1 bit)
access : read-only
TMRWK : Timer Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out. This flag is cleared when DPD or SPD mode is entered.
bits : 1 - 1 (1 bit)
access : read-only
RTCWK : RTC Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened. This flag is cleared when DPD or SPD mode is entered.
bits : 2 - 2 (1 bit)
access : read-only
GPAWK : GPA Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPA group pins. This flag is cleared when SPD mode is entered.
bits : 8 - 8 (1 bit)
access : read-only
GPBWK : GPB Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPB group pins. This flag is cleared when SPD mode is entered.
bits : 9 - 9 (1 bit)
access : read-only
GPCWK : GPC Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPC group pins. This flag is cleared when SPD mode is entered.
bits : 10 - 10 (1 bit)
access : read-only
GPDWK : GPD Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPD group pins. This flag is cleared when SPD mode is entered.
bits : 11 - 11 (1 bit)
access : read-only
LVRWK : LVR Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a LVR happened. This flag is cleared when SPD mode is entered.
bits : 12 - 12 (1 bit)
access : read-only
BODWK : BOD Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a BOD happened. This flag is cleared when SPD mode is entered.
bits : 13 - 13 (1 bit)
access : read-only
ACMPWK : ACMP Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a ACMP transition. This flag is cleared when SPD mode is entered.
bits : 14 - 14 (1 bit)
access : read-only
CLRWK : Clear Wake-up Flage\nNote: This bit is auto cleared by hardware.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No clear
#1 : 1
Clear all of wake-up flag
End of enumeration elements list.
Standby Power-down Wake-up De-bounce Control Register
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWKDBCLKSEL : Standby Power-down Wake-up De-bounce Sampling Cycle Selection\nNote: De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC).
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Sample wake-up input once per 1 clocks
#0001 : 1
Sample wake-up input once per 2 clocks
#0010 : 2
Sample wake-up input once per 4 clocks
#0011 : 3
Sample wake-up input once per 8 clocks
#0100 : 4
Sample wake-up input once per 16 clocks
#0101 : 5
Sample wake-up input once per 32 clocks
#0110 : 6
Sample wake-up input once per 64 clocks
#0111 : 7
Sample wake-up input once per 128 clocks
#1000 : 8
Sample wake-up input once per 256 clocks
#1001 : 9
Sample wake-up input once per 2*256 clocks
#1010 : 10
Sample wake-up input once per 4*256 clocks
#1011 : 11
Sample wake-up input once per 8*256 clocks
#1100 : 12
Sample wake-up input once per 16*256 clocks
#1101 : 13
Sample wake-up input once per 32*256 clocks
#1110 : 14
Sample wake-up input once per 64*256 clocks
#1111 : 15
Sample wake-up input once per 128*256 clocks
End of enumeration elements list.
GPA Standby Power-down Wake-up Control Register
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKEN : Standby Power-down Pin Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPA group pin wake-up function Disabled
#1 : 1
GPA group pin wake-up function Enabled
End of enumeration elements list.
PRWKEN : Pin Rising Edge Wake-up Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPA group pin rising edge wake-up function Disabled
#1 : 1
GPA group pin rising edge wake-up function Enabled
End of enumeration elements list.
PFWKEN : Pin Falling Edge Wake-up Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPA group pin falling edge wake-up function Disabled
#1 : 1
GPA group pin falling edge wake-up function Enabled
End of enumeration elements list.
WKPSEL : GPA Standby Power-down Wake-up Pin Select
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPA.0 wake-up function enabled
#0001 : 1
GPA.1 wake-up function enabled
#0010 : 2
GPA.2 wake-up function enabled
#0011 : 3
GPA.3 wake-up function enabled
#0100 : 4
GPA.4 wake-up function enabled
#0101 : 5
GPA.5 wake-up function enabled
#0110 : 6
GPA.6 wake-up function enabled
#0111 : 7
GPA.7 wake-up function enabled
#1000 : 8
GPA.8 wake-up function enabled
#1001 : 9
GPA.9 wake-up function enabled
#1010 : 10
GPA.10 wake-up function enabled
#1011 : 11
GPA.11 wake-up function enabled
#1100 : 12
GPA.12 wake-up function enabled
#1101 : 13
GPA.13 wake-up function enabled
#1110 : 14
GPA.14 wake-up function enabled
#1111 : 15
GPA.15 wake-up function enabled
End of enumeration elements list.
DBEN : GPA Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding IO. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup.The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC).\nThe de-bounce function is valid only for edge triggered.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Standby power-down wake-up pin De-bounce function Disabled
#1 : 1
Standby power-down wake-up pin De-bounce function Enabled
End of enumeration elements list.
GPB Standby Power-down Wake-up Control Register
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKEN : Standby Power-down Pin Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPB group pin wake-up function Disabled
#1 : 1
GPB group pin wake-up function Enabled
End of enumeration elements list.
PRWKEN : Pin Rising Edge Wake-up Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPB group pin rising edge wake-up function Disabled
#1 : 1
GPB group pin rising edge wake-up function Enabled
End of enumeration elements list.
PFWKEN : Pin Falling Edge Wake-up Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPB group pin falling edge wake-up function Disabled
#1 : 1
GPB group pin falling edge wake-up function Enabled
End of enumeration elements list.
WKPSEL : GPB Standby Power-down Wake-up Pin Select
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPB.0 wake-up function enabled
#0001 : 1
GPB.1 wake-up function enabled
#0010 : 2
GPB.2 wake-up function enabled
#0011 : 3
GPB.3 wake-up function enabled
#0100 : 4
GPB.4 wake-up function enabled
#0101 : 5
GPB.5 wake-up function enabled
#0110 : 6
GPB.6 wake-up function enabled
#0111 : 7
GPB.7 wake-up function enabled
#1000 : 8
GPB.8 wake-up function enabled
#1001 : 9
GPB.9 wake-up function enabled
#1010 : 10
GPB.10 wake-up function enabled
#1011 : 11
GPB.11 wake-up function enabled
#1100 : 12
GPB.12 wake-up function enabled
#1101 : 13
GPB.13 wake-up function enabled
#1110 : 14
GPB.14 wake-up function enabled
#1111 : 15
GPB.15 wake-up function enabled
End of enumeration elements list.
DBEN : GPB Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding IO. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup.The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC).\nThe de-bounce function is valid only for edge triggered.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Standby power-down wake-up pin De-bounce function Disabled
#1 : 1
Standby power-down wake-up pin De-bounce function Enabled
End of enumeration elements list.
GPC Standby Power-down Wake-up Control Register
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKEN : Standby Power-down Pin Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPC group pin wake-up function Disabled
#1 : 1
GPC group pin wake-up function Enabled
End of enumeration elements list.
PRWKEN : Pin Rising Edge Wake-up Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPC group pin rising edge wake-up function Disabled
#1 : 1
GPC group pin rising edge wake-up function Enabled
End of enumeration elements list.
PFWKEN : Pin Falling Edge Wake-up Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPC group pin falling edge wake-up function Disabled
#1 : 1
GPC group pin falling edge wake-up function Enabled
End of enumeration elements list.
WKPSEL : GPC Standby Power-down Wake-up Pin Select
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPC.0 wake-up function enabled
#0001 : 1
GPC.1 wake-up function enabled
#0010 : 2
GPC.2 wake-up function enabled
#0011 : 3
GPC.3 wake-up function enabled
#0100 : 4
GPC.4 wake-up function enabled
#0101 : 5
GPC.5 wake-up function enabled
#0110 : 6
GPC.6 wake-up function enabled
#0111 : 7
GPC.7 wake-up function enabled
#1000 : 8
GPC.8 wake-up function enabled
#1001 : 9
GPC.9 wake-up function enabled
#1010 : 10
GPC.10 wake-up function enabled
#1011 : 11
GPC.11 wake-up function enabled
#1100 : 12
GPC.12 wake-up function enabled
#1101 : 13
GPC.13 wake-up function enabled
#1110 : 14
Reserved.
#1111 : 15
Reserved.
End of enumeration elements list.
DBEN : GPC Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding IO. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup.The de-bounce clock source is the 10 kHz internal low speed RC oscillator.\nThe de-bounce function is valid only for edge triggered.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Standby power-down wake-up pin De-bounce function Disabled
#1 : 1
Standby power-down wake-up pin De-bounce function Enabled
End of enumeration elements list.
GPD Standby Power-down Wake-up Control Register
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKEN : Standby Power-down Pin Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPD group pin wake-up function Disabled
#1 : 1
GPD group pin wake-up function Enabled
End of enumeration elements list.
PRWKEN : Pin Rising Edge Wake-up Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPD group pin rising edge wake-up function Disabled
#1 : 1
GPD group pin rising edge wake-up function Enabled
End of enumeration elements list.
PFWKEN : Pin Falling Edge Wake-up Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPD group pin falling edge wake-up function Disabled
#1 : 1
GPD group pin falling edge wake-up function Enabled
End of enumeration elements list.
WKPSEL : GPD Standby Power-down Wake-up Pin Select
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPD.0 wake-up function enabled
#0001 : 1
GPD.1 wake-up function enabled
#0010 : 2
GPD.2 wake-up function enabled
#0011 : 3
GPD.3 wake-up function enabled
#0100 : 4
GPD.4 wake-up function enabled
#0101 : 5
GPD.5 wake-up function enabled
#0110 : 6
GPD.6 wake-up function enabled
#0111 : 7
GPD.7 wake-up function enabled
#1000 : 8
GPD.8 wake-up function enabled
#1001 : 9
GPD.9 wake-up function enabled
#1010 : 10
GPD.10 wake-up function enabled
#1011 : 11
GPD.11 wake-up function enabled
#1100 : 12
GPD.12 wake-up function enabled
#1101 : 13
GPD.13 wake-up function enabled
#1110 : 14
GPD.14 wake-up function enabled
#1111 : 15
Reserved.
End of enumeration elements list.
DBEN : GPD Input Signal De-bounce Enable Bit\nThe DBEN bit is used to enable the de-bounce function for each corresponding IO. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup.The de-bounce clock source is the 10 kHz internal low speed RC oscillator.\nThe de-bounce function is valid only for edge triggered.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Standby power-down wake-up pin De-bounce function Disabled
#1 : 1
Standby power-down wake-up pin De-bounce function Enabled
End of enumeration elements list.
GPIO Standby Power-down Control Register
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOHR : GPIO Hold Release\nWhen GPIO enters standby power-down mode, all I/O status are hold to keep normal operating status. After chip was waked up from standby power-down mode, the I/O still keeps hold status until user sets this bit to release I/O hold status.\nNote: This bit is auto cleared by hardware.
bits : 0 - 0 (1 bit)
access : read-write
HXT Filter Select Control Register
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTFSEL : HXT Filter Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
HXT frequency is larger than 12 MHz
#1 : 1
HXT frequency is less than or equal to 12 MHz
End of enumeration elements list.
APB Devices Clock Enable Control Register 1
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SC0CKEN : Smart Card 0 (SC0) Clock Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SC0 clock Disabled
#1 : 1
SC0 clock Enabled
End of enumeration elements list.
SC1CKEN : Smart Card 1 (SC1) Clock Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
SC1 clock Disabled
#1 : 1
SC1 clock Enabled
End of enumeration elements list.
SC2CKEN : Smart Card 2 (SC2) Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
SC2 clock Disabled
#1 : 1
SC2 clock Enabled
End of enumeration elements list.
SPI3CKEN : SPI3 Clock Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI3 clock Disabled
#1 : 1
SPI3 clock Enabled
End of enumeration elements list.
USCI0CKEN : USCI0 Clock Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
USCI0 clock Disabled
#1 : 1
USCI0 clock Enabled
End of enumeration elements list.
USCI1CKEN : USCI1 Clock Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
USCI1 clock Disabled
#1 : 1
USCI1 clock Enabled
End of enumeration elements list.
DACCKEN : DAC Clock Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC clock Disabled
#1 : 1
DAC clock Enabled
End of enumeration elements list.
EPWM0CKEN : EPWM0 Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM0 clock Disabled
#1 : 1
EPWM0 clock Enabled
End of enumeration elements list.
EPWM1CKEN : EPWM1 Clock Enable Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM1 clock Disabled
#1 : 1
EPWM1 clock Enabled
End of enumeration elements list.
BPWM0CKEN : BPWM0 Clock Enable Bit
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM0 clock Disabled
#1 : 1
BPWM0 clock Enabled
End of enumeration elements list.
BPWM1CKEN : BPWM1 Clock Enable Bit
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM1 clock Disabled
#1 : 1
BPWM1 clock Enabled
End of enumeration elements list.
QEI0CKEN : QEI0 Clock Enable Bit
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
QEI0 clock Disabled
#1 : 1
QEI0 clock Enabled
End of enumeration elements list.
QEI1CKEN : QEI1 Clock Enable Bit
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
QEI1 clock Disabled
#1 : 1
QEI1 clock Enabled
End of enumeration elements list.
TRNGCKEN : TRNG Clock Enable Bit
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
TRNG clock Disabled
#1 : 1
TRNG clock Enabled
End of enumeration elements list.
ECAP0CKEN : ECAP0 Clock Enable Bit
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
ECAP0 clock Disabled
#1 : 1
ECAP0 clock Enabled
End of enumeration elements list.
ECAP1CKEN : ECAP1 Clock Enable Bit
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
ECAP1 clock Disabled
#1 : 1
ECAP1 clock Enabled
End of enumeration elements list.
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