\n

SCU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x200 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x4C byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x74 Bytes (0x0)
size : 0x48 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SCU_PNSSET0 (PNSSET0)

SCU_PNSSET4 (PNSSET4)

SCU_PNSSET5 (PNSSET5)

SCU_PNSSET6 (PNSSET6)

SCU_IONSSET (IONSSET)

SCU_NSMCTL (NSMCTL)

SCU_NSMLOAD (NSMLOAD)

SCU_NSMVAL (NSMVAL)

SCU_NSMSTS (NSMSTS)

SCU_SRAMNSSET (SRAMNSSET)

SCU_FNSADDR (FNSADDR)

SCU_SVIOIEN (SVIOIEN)

SCU_SVINTSTS (SVINTSTS)

SCU_APB0VSRC (APB0VSRC)

SCU_APB0VA (APB0VA)

SCU_APB1VSRC (APB1VSRC)

SCU_PNSSET1 (PNSSET1)

SCU_APB1VA (APB1VA)

SCU_GPIOVSRC (GPIOVSRC)

SCU_GPIOVA (GPIOVA)

SCU_EBIVSRC (EBIVSRC)

SCU_EBIVA (EBIVA)

SCU_USBHVSRC (USBHVSRC)

SCU_USBHVA (USBHVA)

SCU_CRCVSRC (CRCVSRC)

SCU_CRCVA (CRCVA)

SCU_SD0VSRC (SD0VSRC)

SCU_SD0VA (SD0VA)

SCU_PDMA0VSRC (PDMA0VSRC)

SCU_PDMA0VA (PDMA0VA)

SCU_PDMA1VSRC (PDMA1VSRC)

SCU_PNSSET2 (PNSSET2)

SCU_PDMA1VA (PDMA1VA)

SCU_SRAM0VSRC (SRAM0VSRC)

SCU_SRAM0VA (SRAM0VA)

SCU_SRAM1VSRC (SRAM1VSRC)

SCU_SRAM1VA (SRAM1VA)

SCU_FMCVSRC (FMCVSRC)

SCU_FMCVA (FMCVA)

SCU_FLASHVSRC (FLASHVSRC)

SCU_FLASHVA (FLASHVA)

SCU_SCUVSRC (SCUVSRC)

SCU_SCUVA (SCUVA)

SCU_SYSVSRC (SYSVSRC)

SCU_SYSVA (SYSVA)

SCU_CRPTVSRC (CRPTVSRC)

SCU_CRPTVA (CRPTVA)

SCU_PNSSET3 (PNSSET3)


SCU_PNSSET0 (PNSSET0)

Peripheral Non-secure Attribution Set Register0 (0x4000_0000~0x4001_FFFF)
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_PNSSET0 SCU_PNSSET0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBH SDH0 EBI PDMA1

USBH : Set USBH to Non-secure State\nWrite 1 to set USBH to non-secure state. Write 0 has no effect.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

USBH is a secure module (default)

#1 : 1

USBH is a non-secure module

End of enumeration elements list.

SDH0 : Set SDH0 to Non-secure State\nWrite 1 to set SDH0 to non-secure state. Write 0 has no effect.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

SDH0 is a secure module (default)

#1 : 1

SDH0 is a non-secure module

End of enumeration elements list.

EBI : Set EBI to Non-secure State\nWrite 1 to set EBI to non-secure state. Write 0 has no effect.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

EBI is a secure module (default)

#1 : 1

EBI is a non-secure module

End of enumeration elements list.

PDMA1 : Set PDMA1 to Non-secure State\nWrite 1 to set PDMA1 to non-secure state. Write 0 has no effect.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDMA1 is a secure module (default)

#1 : 1

PDMA1 is a non-secure module

End of enumeration elements list.


SCU_PNSSET4 (PNSSET4)

Peripheral Non-secure Attribution Set Register4 (0x4008_0000~0x4009_FFFF)
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_PNSSET4 SCU_PNSSET4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C0 I2C1 I2C2 SC0 SC1 SC2

I2C0 : Set I2C0 to Non-secure State\nWrite 1 to set I2C0 to non-secure state. Write 0 has no effect.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C0 is a secure module (default)

#1 : 1

I2C0 is a non-secure module

End of enumeration elements list.

I2C1 : Set I2C1 to Non-secure State\nWrite 1 to set I2C1 to non-secure state. Write 0 has no effect.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C1 is a secure module (default)

#1 : 1

I2C1 is a non-secure module

End of enumeration elements list.

I2C2 : Set I2C2 to Non-secure State\nWrite 1 to set I2C2 to non-secure state. Write 0 has no effect.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C2 is a secure module (default)

#1 : 1

I2C2 is a non-secure module

End of enumeration elements list.

SC0 : Set SC0 to Non-secure State\nWrite 1 to set SC0 to non-secure state. Write 0 has no effect.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

SC0 is a secure module (default)

#1 : 1

SC0 is a non-secure module

End of enumeration elements list.

SC1 : Set SC1 to Non-secure State\nWrite 1 to set SC1 to non-secure state. Write 0 has no effect.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

SC1 is a secure module (default)

#1 : 1

SC1 is a non-secure module

End of enumeration elements list.

SC2 : Set SC2 to Non-secure State\nWrite 1 to set SC2 to non-secure state. Write 0 has no effect.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

SC2 is a secure module (default)

#1 : 1

SC2 is a non-secure module

End of enumeration elements list.


SCU_PNSSET5 (PNSSET5)

Peripheral Non-secure Attribution Set Register5 (0x400A_0000~0x400B_FFFF)
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_PNSSET5 SCU_PNSSET5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAN0 QEI0 QEI1 ECAP0 ECAP1 TRNG

CAN0 : Set CAN0 to Non-secure State\nWrite 1 to set CAN0 to non-secure state. Write 0 has no effect.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

CAN0 is a secure module (default)

#1 : 1

CAN0 is a non-secure module

End of enumeration elements list.

QEI0 : Set QEI0 to Non-secure State\nWrite 1 to set QEI0 to non-secure state. Write 0 has no effect.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

QEI0 is a secure module (default)

#1 : 1

QEI0 is a non-secure module

End of enumeration elements list.

QEI1 : Set QEI1 to Non-secure State\nWrite 1 to set QEI1 to non-secure state. Write 0 has no effect.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

QEI1 is a secure module (default)

#1 : 1

QEI1 is a non-secure module

End of enumeration elements list.

ECAP0 : Set ECAP0 to Non-secure State\nWrite 1 to set ECAP0 to non-secure state. Write 0 has no effect.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

ECAP0 is a secure module (default)

#1 : 1

ECAP0 is a non-secure module

End of enumeration elements list.

ECAP1 : Set ECAP1 to Non-secure State\nWrite 1 to set ECAP1 to non-secure state. Write 0 has no effect.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

ECAP1 is a secure module (default)

#1 : 1

ECAP1 is a non-secure module

End of enumeration elements list.

TRNG : Set TRNG to Non-secure State\nWrite 1 to set TRNG to non-secure state. Write 0 has no effect.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

TRNG is a secure module (default)

#1 : 1

TRNG is a non-secure module

End of enumeration elements list.


SCU_PNSSET6 (PNSSET6)

Peripheral Non-secure Attribution Set Register6 (0x400C_0000~0x400D_FFFF)
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_PNSSET6 SCU_PNSSET6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBD USCI0 USCI1

USBD : Set USBD to Non-secure State\nWrite 1 to set USBD to non-secure state. Write 0 has no effect.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

USBD is a secure module (default)

#1 : 1

USBD is a non-secure module

End of enumeration elements list.

USCI0 : Set USCI0 to Non-secure State\nWrite 1 to set USCI0 to non-secure state. Write 0 has no effect.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

USCI0 is a secure module (default)

#1 : 1

USCI0 is a non-secure module

End of enumeration elements list.

USCI1 : Set USCI1 to Non-secure State\nWrite 1 to set USCI1 to non-secure state. Write 0 has no effect.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

USCI1 is a secure module (default)

#1 : 1

USCI1 is a non-secure module

End of enumeration elements list.


SCU_IONSSET (IONSSET)

IO Non-secure Attribution Set Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_IONSSET SCU_IONSSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA PB PC PD PE PF PG PH

PA : Set GPIO Port A to Non-scecure State\nWrite 1 to set PA to non-secure state. Write 0 has no effect.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port A is secure (default)

#1 : 1

GPIO port A is non-secure

End of enumeration elements list.

PB : Set GPIO Port B to Non-scecure State\nWrite 1 to set PB to non-secure state. Write 0 has no effect.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port B is secure (default)

#1 : 1

GPIO port B is non-secure

End of enumeration elements list.

PC : Set GPIO Port C to Non-scecure State\nWrite 1 to set PC to non-secure state. Write 0 has no effect.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port C is secure (default)

#1 : 1

GPIO port C is non-secure

End of enumeration elements list.

PD : Set GPIO Port D to Non-scecure State\nWrite 1 to set PD to non-secure state. Write 0 has no effect.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port D is secure (default)

#1 : 1

GPIO port D is non-secure

End of enumeration elements list.

PE : Set GPIO Port E to Non-scecure State\nWrite 1 to set PE to non-secure state. Write 0 has no effect.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port E is secure (default)

#1 : 1

GPIO port E is non-secure

End of enumeration elements list.

PF : Set GPIO Port F to Non-scecure State\nWrite 1 to set PF to non-secure state. Write 0 has no effect.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port F is secure (default)

#1 : 1

GPIO port F is non-secure

End of enumeration elements list.

PG : Set GPIO Port G to Non-scecure State\nWrite 1 to set PG to non-secure state. Write 0 has no effect.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port G is secure (default)

#1 : 1

GPIO port G is non-secure

End of enumeration elements list.

PH : Set GPIO Port H to Non-scecure State\nWrite 1 to set PH to non-secure state. Write 0 has no effect.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port H is secure (default)

#1 : 1

GPIO port H is non-secure

End of enumeration elements list.


SCU_NSMCTL (NSMCTL)

Non-secure State Monitor Control Register
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_NSMCTL SCU_NSMCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESCALE NSMIEN AUTORLD TMRMOD IDLEON DBGON

PRESCALE : Pre-scale Value of Non-secure State Monitor Counter
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0 : 0

Counter Disabled

End of enumeration elements list.

NSMIEN : Non-secure State Monitor Interrupt Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Non-secure state monitor interrupt Disabled

#1 : 1

Non-secure state monitor interrupt Enabled

End of enumeration elements list.

AUTORLD : Auto Reload Non-secure State Monitor Counter When CURRNS Changing to 1
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable clearing non-secure state monitor counter automtically. (default)

#1 : 1

Enable clearing non-secure state monitor counter automatically when the core processor changes from secure state to non-secure state

End of enumeration elements list.

TMRMOD : Non-secure Monitor Mode Enable Bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Monitor mode. The counter will count down when the core processor is in non-secure state. (default)

#1 : 1

Free-counting mode. The counter will keep counting no mater the core processor is in secure or non-secure state

End of enumeration elements list.

IDLEON : Monitor Counter Keep Counting When the Chip is in Idle Mode Enable Bit\nNote: In monitor mode, the counter is always halted when the core processor is in secure state.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

The counter will be halted when the chip is in idle mode

#1 : 1

The counter will keep counting when the chip is in idle mode. (default)

End of enumeration elements list.

DBGON : Monitor Counter Keep Counting When the Chip is in Debug Mode Enable Bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

The counter will be halted when the core processor is halted by ICE. (default)

#1 : 1

The counter will keep counting when the core processor is halted by ICE

End of enumeration elements list.


SCU_NSMLOAD (NSMLOAD)

Non-secure State Monitor Reload Value Register
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_NSMLOAD SCU_NSMLOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RELOAD

RELOAD : Reload Value for Non-secure State Monitor Counter\nThe RELOAD value will be reloaded to the counter whenever the counter counts down to 0.
bits : 0 - 23 (24 bit)
access : read-write


SCU_NSMVAL (NSMVAL)

Non-secure State Monitor Counter Value Register
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_NSMVAL SCU_NSMVAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Counter Value of Non-secure State Monitor Counter\nA write of any value clears the VALUE to 0 and also clears NSMIF.
bits : 0 - 23 (24 bit)
access : read-write


SCU_NSMSTS (NSMSTS)

Non-secure State Monitor Status Register
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_NSMSTS SCU_NSMSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURRNS NSMIF

CURRNS : Current Core Processor Secure/Non-secure State\nNote: This bit can be used to monitor the current secure/non-secure state of the core processor, even if the non-secure state monitor counter is disabled.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Core processor is in secure state

#1 : 1

Core processor is in non-secure state

End of enumeration elements list.

NSMIF : Non-secure State Monitor Interrupt Flag\nNote: This bit is cleared by writing 1.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Counter doesn't count down to 0 since the last NSMIF has been cleared

#1 : 1

Counter counts down to 0

End of enumeration elements list.


SCU_SRAMNSSET (SRAMNSSET)

SRAM Non-secure Attribution Set Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SRAMNSSET SCU_SRAMNSSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SECn

SECn : Set SRAM Section N to Non-scecure State\nWrite 1 to set SRAM section n to non-secure state. Write 0 is ignored. \nSecure SRAM section n is 0x2000_0000+0x2000*n to 0x2000_0000+0x2000*(n+1)-0x1\nNon-secure SRAM section n is 0x3000_0000+0x2000*n to 0x3000_0000+0x2000*(n+1)-0x1
bits : 0 - 11 (12 bit)
access : read-write

Enumeration:

0 : 0

SRAM Section n is secure (default)

1 : 1

SRAM Section n is non-secure

End of enumeration elements list.


SCU_FNSADDR (FNSADDR)

Flash Non-secure Boundary Address Register
address_offset : 0x28 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SCU_FNSADDR SCU_FNSADDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FNSADDR

FNSADDR : Flash Non-secure Boundary Address\nIndicate the base address of Non-secure region set in user configuration. Refer to FMC section for more details.
bits : 0 - 31 (32 bit)
access : read-only


SCU_SVIOIEN (SVIOIEN)

Security Violation Interrupt Enable Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SVIOIEN SCU_SVIOIEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APB0IEN APB1IEN GPIOIEN EBIIEN USBHIEN CRCIEN SDH0IEN PDMA0IEN PDMA1IEN SRAM0IEN SRAM1IEN FMCIEN FLASHIEN SCUIEN SYSIEN CRPTIEN

APB0IEN : APB0 Security Violation Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of APB0 Disabled

#1 : 1

Interrupt triggered from security violation of APB0 Enabled

End of enumeration elements list.

APB1IEN : APB1 Security Violation Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of APB1 Disabled

#1 : 1

Interrupt triggered from security violation of APB1 Enabled

End of enumeration elements list.

GPIOIEN : GPIO Security Violation Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of GPIO Disabled

#1 : 1

Interrupt triggered from security violation of GPIO Enabled

End of enumeration elements list.

EBIIEN : EBI Security Violation Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of EBI Disabled

#1 : 1

Interrupt triggered from security violation of EBI Enabled

End of enumeration elements list.

USBHIEN : USBH Security Violation Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of USB host Disabled

#1 : 1

Interrupt triggered from security violation of USB host Enabled

End of enumeration elements list.

CRCIEN : CRC Security Violation Interrupt Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of CRC Disabled

#1 : 1

Interrupt triggered from security violation of CRC Enabled

End of enumeration elements list.

SDH0IEN : SDH0 Security Violation Interrupt Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of SD host 0 Disabled

#1 : 1

Interrupt triggered from security violation of SD host 0 Enabled

End of enumeration elements list.

PDMA0IEN : PDMA0 Security Violation Interrupt Enable Bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of PDMA0 Disabled

#1 : 1

Interrupt triggered from security violation of PDMA0 Enabled

End of enumeration elements list.

PDMA1IEN : PDMA1 Security Violation Interrupt Enable Bit
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of PDMA1 Disabled

#1 : 1

Interrupt triggered from security violation of PDMA1 Enabled

End of enumeration elements list.

SRAM0IEN : SRAM Bank 0 Security Violation Interrupt Enable Bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of SRAM bank0 Disabled

#1 : 1

Interrupt triggered from security violation of SRAM bank0 Enabled

End of enumeration elements list.

SRAM1IEN : SRAM Bank 1 Security Violation Interrupt Enable Bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of SRAM bank1 Disabled

#1 : 1

Interrupt triggered from security violation of SRAM bank1 Enabled

End of enumeration elements list.

FMCIEN : FMC Security Violation Interrupt Enable Bit
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of FMC Disabled

#1 : 1

Interrupt triggered from security violation of FMC Enabled

End of enumeration elements list.

FLASHIEN : FLASH Security Violation Interrupt Enable Bit
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of Flash data Disabled

#1 : 1

Interrupt triggered from security violation of Flash data Enabled

End of enumeration elements list.

SCUIEN : SCU Security Violation Interrupt Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of SCU Disabled

#1 : 1

Interrupt triggered from security violation of SCU Enabled

End of enumeration elements list.

SYSIEN : SYS Security Violation Interrupt Enable Bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of system manager Disabled

#1 : 1

Interrupt triggered from security violation of system manager Enabled

End of enumeration elements list.

CRPTIEN : CRPT Security Violation Interrupt Enable Bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt triggered from security violation of crypto Disabled

#1 : 1

Interrupt triggered from security violation of crypto Enabled

End of enumeration elements list.


SCU_SVINTSTS (SVINTSTS)

Security Violation Interrupt Status Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SVINTSTS SCU_SVINTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 APB0IF APB1IF GPIOIF EBIIF USBHIF CRCIF SDH0IF PDMA0IF PDMA1IF SRAM0IF SRAM1IF FMCIF FLASHIF SCUIF SYSIF CRPTIF

APB0IF : APB0 Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No APB0 violation interrupt event

#1 : 1

There is APB0 violation interrupt event

End of enumeration elements list.

APB1IF : APB1 Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No APB1 violation interrupt event

#1 : 1

There is APB1 violation interrupt event

End of enumeration elements list.

GPIOIF : GPIO Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No GPIO violation interrupt event

#1 : 1

There is GPIO violation interrupt event

End of enumeration elements list.

EBIIF : EBI Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No EBI violation interrupt event

#1 : 1

There is EBI violation interrupt event

End of enumeration elements list.

USBHIF : USBH Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

No USBH violation interrupt event

#1 : 1

There is USBH violation interrupt event

End of enumeration elements list.

CRCIF : CRC Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

No CRC violation interrupt event

#1 : 1

There is CRC violation interrupt event

End of enumeration elements list.

SDH0IF : SDH0 Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

No SDH0 violation interrupt event

#1 : 1

There is SDH0 violation interrupt event

End of enumeration elements list.

PDMA0IF : PDMA0 Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

No PDMA0 violation interrupt event

#1 : 1

There is PDMA0 violation interrupt event

End of enumeration elements list.

PDMA1IF : PDMA1 Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

No PDMA1 violation interrupt event

#1 : 1

There is PDMA1 violation interrupt event

End of enumeration elements list.

SRAM0IF : SRAM0 Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

No SRAM0 violation interrupt event

#1 : 1

There is SRAM0 violation interrupt event

End of enumeration elements list.

SRAM1IF : SRAM Bank 1 Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

No SRAM1 violation interrupt event

#1 : 1

There is SRAM1 violation interrupt event

End of enumeration elements list.

FMCIF : FMC Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

No FMC violation interrupt event

#1 : 1

There is FMC violation interrupt event

End of enumeration elements list.

FLASHIF : FLASH Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

No FLASH violation interrupt event

#1 : 1

There is FLASH violation interrupt event

End of enumeration elements list.

SCUIF : SCU Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

No SCU violation interrupt event

#1 : 1

There is SCU violation interrupt event

End of enumeration elements list.

SYSIF : SYS Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

No SYS violation interrupt event

#1 : 1

There is SYS violation interrupt event

End of enumeration elements list.

CRPTIF : CRPT Security Violation Interrupt Status\nNote: Write 1 to clear the interrupt flag.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

No CRPT violation interrupt event

#1 : 1

There is CRPT violation interrupt event

End of enumeration elements list.


SCU_APB0VSRC (APB0VSRC)

APB0 Security Policy Violation Source
address_offset : 0x34 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SCU_APB0VSRC SCU_APB0VSRC read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASTER

MASTER : Master Violating Security Policy\nIndicate which master invokes the security violation.\nOthers is undefined.
bits : 0 - 3 (4 bit)
access : read-only

Enumeration:

0x0 : 0

core processor

0x3 : 3

PDMA0

0x4 : 4

SDH0

0x5 : 5

CRYPTO

0x6 : 6

USH

0xb : 11

PDMA1

End of enumeration elements list.


SCU_APB0VA (APB0VA)

APB0 Violation Address
address_offset : 0x38 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SCU_APB0VA SCU_APB0VA read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VIOADDR

VIOADDR : Violation Address\nIndicate the target address of the access, which invokes the security violation.
bits : 0 - 31 (32 bit)
access : read-only


SCU_APB1VSRC (APB1VSRC)

APB1 Security Policy Violation Source
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_APB1VSRC SCU_APB1VSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_PNSSET1 (PNSSET1)

Peripheral Non-secure Attribution Set Register1 (0x4002_0000~0x4003_FFFF)
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_PNSSET1 SCU_PNSSET1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC CRPT

CRC : Set CRC to Non-secure State\nWrite 1 to set CRC to non-secure state. Write 0 has no effect.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

CRC is a secure module (default)

#1 : 1

CRC is a non-secure module

End of enumeration elements list.

CRPT : Set CRPT to Non-secure State\nWrite 1 to set CRPT to non-secure state. Write 0 has no effect.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

CRPT is a secure module (default)

#1 : 1

CRPT is a non-secure module

End of enumeration elements list.


SCU_APB1VA (APB1VA)

APB1 Violation Address
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_APB1VA SCU_APB1VA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_GPIOVSRC (GPIOVSRC)

GPIO Security Policy Violation Source
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_GPIOVSRC SCU_GPIOVSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_GPIOVA (GPIOVA)

GPIO Violation Address
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_GPIOVA SCU_GPIOVA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_EBIVSRC (EBIVSRC)

EBI Security Policy Violation Source
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_EBIVSRC SCU_EBIVSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_EBIVA (EBIVA)

EBI Violation Address
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_EBIVA SCU_EBIVA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_USBHVSRC (USBHVSRC)

USBH Security Policy Violation Source
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_USBHVSRC SCU_USBHVSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_USBHVA (USBHVA)

USBH Violation Address
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_USBHVA SCU_USBHVA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_CRCVSRC (CRCVSRC)

CRC Security Policy Violation Source
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_CRCVSRC SCU_CRCVSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_CRCVA (CRCVA)

CRC Violation Address
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_CRCVA SCU_CRCVA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_SD0VSRC (SD0VSRC)

SDH0 Security Policy Violation Source
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SD0VSRC SCU_SD0VSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_SD0VA (SD0VA)

SDH0 Violation Address
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SD0VA SCU_SD0VA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_PDMA0VSRC (PDMA0VSRC)

PDMA0 Security Policy Violation Source
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_PDMA0VSRC SCU_PDMA0VSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_PDMA0VA (PDMA0VA)

PDMA0 Violation Address
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_PDMA0VA SCU_PDMA0VA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_PDMA1VSRC (PDMA1VSRC)

PDMA1 Security Policy Violation Source
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_PDMA1VSRC SCU_PDMA1VSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_PNSSET2 (PNSSET2)

Peripheral Non-secure Attribution Set Register2 (0x4004_0000~0x4005_FFFF)
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_PNSSET2 SCU_PNSSET2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC EADC ACMP01 DAC I2S0 OTG TMR23 EPWM0 EPWM1 BPWM0 BPWM1

RTC : Set RTC to Non-secure State\nWrite 1 to set RTC to non-secure state. Write 0 has no effect.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC is a secure module (default)

#1 : 1

RTC is a non-secure module

End of enumeration elements list.

EADC : Set EADC to Non-secure State\nWrite 1 to set EADC to non-secure state. Write 0 has no effect.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

EADC is a secure module (default)

#1 : 1

EADC is a non-secure module

End of enumeration elements list.

ACMP01 : Set ACMP01 to Non-secure State\nWrite 1 to set ACMP0, ACMP1 to non-secure state. Write 0 has no effect.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

ACMP0, ACMP1 are secure modules (default)

#1 : 1

ACMP0, ACMP1 are non-secure modules

End of enumeration elements list.

DAC : Set DAC to Non-secure State\nWrite 1 to set DAC to non-secure state. Write 0 has no effect.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

DAC is a secure module (default)

#1 : 1

DAC is a non-secure module

End of enumeration elements list.

I2S0 : Set I2S0 to Non-secure State\nWrite 1 to set I2S0 to non-secure state. Write 0 has no effect.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2S0 is a secure module (default)

#1 : 1

I2S0 is a non-secure module

End of enumeration elements list.

OTG : Set OTG to Non-secure State\nWrite 1 to set OTG to non-secure state. Write 0 has no effect.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

OTG is a secure module (default)

#1 : 1

OTG is a non-secure module

End of enumeration elements list.

TMR23 : Set TMR23 to Non-secure State\nWrite 1 to set TMR23 to non-secure state. Write 0 has no effect.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

TMR23 is a secure module (default)

#1 : 1

TMR23 is a non-secure module

End of enumeration elements list.

EPWM0 : Set EPWM0 to Non-secure State\nWrite 1 to set EPWM0 to non-secure state. Write 0 has no effect.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

EPWM0 is a secure module (default)

#1 : 1

EPWM0 is a non-secure module

End of enumeration elements list.

EPWM1 : Set EPWM1 to Non-secure State\nWrite 1 to set EPWM1 to non-secure state. Write 0 has no effect.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

EPWM1 is a secure module (default)

#1 : 1

EPWM1 is a non-secure module

End of enumeration elements list.

BPWM0 : Set BPWM0 to Non-secure State\nWrite 1 to set BPWM0 to non-secure state. Write 0 has no effect.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

BPWM0 is a secure module (default)

#1 : 1

BPWM0 is a non-secure module

End of enumeration elements list.

BPWM1 : Set BPWM1 to Non-secure State\nWrite 1 to set BPWM1 to non-secure state. Write 0 has no effect.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

BPWM1 is a secure module (default)

#1 : 1

BPWM1 is a non-secure module

End of enumeration elements list.


SCU_PDMA1VA (PDMA1VA)

PDMA1 Violation Address
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_PDMA1VA SCU_PDMA1VA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_SRAM0VSRC (SRAM0VSRC)

SRAM0 Security Policy Violation Source
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SRAM0VSRC SCU_SRAM0VSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_SRAM0VA (SRAM0VA)

SRAM0 Violation Address
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SRAM0VA SCU_SRAM0VA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_SRAM1VSRC (SRAM1VSRC)

SRAM1 Security Policy Violation Source
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SRAM1VSRC SCU_SRAM1VSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_SRAM1VA (SRAM1VA)

SRAM1 Violation Address
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SRAM1VA SCU_SRAM1VA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_FMCVSRC (FMCVSRC)

FMC Security Policy Violation Source
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_FMCVSRC SCU_FMCVSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_FMCVA (FMCVA)

FMC Violation Address
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_FMCVA SCU_FMCVA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_FLASHVSRC (FLASHVSRC)

Flash Security Policy Violation Source
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_FLASHVSRC SCU_FLASHVSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_FLASHVA (FLASHVA)

Flash Violation Address
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_FLASHVA SCU_FLASHVA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_SCUVSRC (SCUVSRC)

SCU Security Policy Violation Source
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SCUVSRC SCU_SCUVSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_SCUVA (SCUVA)

SCU Violation Address
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SCUVA SCU_SCUVA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_SYSVSRC (SYSVSRC)

System Security Policy Violation Source
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SYSVSRC SCU_SYSVSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_SYSVA (SYSVA)

System Violation Address
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_SYSVA SCU_SYSVA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_CRPTVSRC (CRPTVSRC)

Crypto Security Policy Violation Source
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_CRPTVSRC SCU_CRPTVSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_CRPTVA (CRPTVA)

Crypto Violation Address
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_CRPTVA SCU_CRPTVA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SCU_PNSSET3 (PNSSET3)

Peripheral Non-secure Attribution Set Register3 (0x4006_0000~0x4007_FFFF)
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCU_PNSSET3 SCU_PNSSET3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QSPI0 SPI0 SPI1 SPI2 SPI3 UART0 UART1 UART2 UART3 UART4 UART5

QSPI0 : Set QSPI0 to Non-secure State\nWrite 1 to set QSPI0 to non-secure state. Write 0 has no effect.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

QSPI0 is a secure module (default)

#1 : 1

QSPI0 is a non-secure module

End of enumeration elements list.

SPI0 : Set SPI0 to Non-secure State\nWrite 1 to set SPI0 to non-secure state. Write 0 has no effect.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI0 is a secure module (default)

#1 : 1

SPI0 is a non-secure module

End of enumeration elements list.

SPI1 : Set SPI1 to Non-secure State\nWrite 1 to set SPI1 to non-secure state. Write 0 has no effect.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI1 is a secure module (default)

#1 : 1

SPI1 is a non-secure module

End of enumeration elements list.

SPI2 : Set SPI2 to Non-secure State\nWrite 1 to set SPI2 to non-secure state. Write 0 has no effect.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI2 is a secure module (default)

#1 : 1

SPI2 is a non-secure module

End of enumeration elements list.

SPI3 : Set SPI3 to Non-secure State\nWrite 1 to set SPI3 to non-secure state. Write 0 has no effect.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI3 is a secure module (default)

#1 : 1

SPI3 is a non-secure module

End of enumeration elements list.

UART0 : Set UART0 to Non-secure State\nWrite 1 to set UART0 to non-secure state. Write 0 has no effect.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART0 is a secure module (default)

#1 : 1

UART0 is a non-secure module

End of enumeration elements list.

UART1 : Set UART1 to Non-secure State\nWrite 1 to set UART1 to non-secure state. Write 0 has no effect.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART1 is a secure module (default)

#1 : 1

UART1 is a non-secure module

End of enumeration elements list.

UART2 : Set UART2 to Non-secure State\nWrite 1 to set UART2 to non-secure state. Write 0 has no effect.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART2 is a secure module (default)

#1 : 1

UART2 is a non-secure module

End of enumeration elements list.

UART3 : Set UART3 to Non-secure State\nWrite 1 to set UART3 to non-secure state. Write 0 has no effect.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART3 is a secure module (default)

#1 : 1

UART3 is a non-secure module

End of enumeration elements list.

UART4 : Set UART4 to Non-secure State\nWrite 1 to set UART4 to non-secure state. Write 0 has no effect.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART4 is a secure module (default)

#1 : 1

UART4 is a non-secure module

End of enumeration elements list.

UART5 : Set UART5 to Non-secure State\nWrite 1 to set UART5 to non-secure state. Write 0 has no effect.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART5 is a secure module (default)

#1 : 1

UART5 is a non-secure module

End of enumeration elements list.



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