Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
TRNG Control Register and Status
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNGEN : Random Number Generator Enable Bit\nThis bit can be set to 1 only after ACT (TRNG_ACT[7]) bit was set to 1 and READY (TRNG_CTL[7]) bit became 1.\nNote: TRNGEN is an enable bit of digital part. When TRNG is not required to generate random number, TRNGEN bit and ACT (TRNG_ACT[7]) bit should be set to 0 to reduce power consumption.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
TRNG Disabled
#1 : 1
TRNG Enabled
End of enumeration elements list.
DVIF : Data Valid (Read Only)\nThis bit is cleared to '0' by read TRNG_DATA.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data is not valid. Reading from RNGD returns 0x00000000
#1 : 1
Data is valid. A valid random number can be read form RNGD
End of enumeration elements list.
CLKPSC : Clock Prescaler\nThe CLKPSC is the peripheral clock frequency range for the selected value , the CLKPSC setting must be higher than or equal to the actual peripheral clock frequency (for correct random bit generation). To change the CLKPSC setting, set TRNGEN bit to 0, change CLKPSC, and set TRNGEN bit to 1 to re-enable the TRNG.
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
#0000 : 0
80 ~ 100 MHz
#0001 : 1
60 ~ 80 MHz
#0010 : 2
50 ~60 MHz
#0011 : 3
40 ~50 MHz
#0100 : 4
30 ~40 MHz
#0101 : 5
25 ~30 MHz
#0110 : 6
20 ~25 MHz
#0111 : 7
15 ~20 MHz
#1000 : 8
12 ~15 MHz
#1001 : 9
9 ~12 MHz
#1010 : 10
7 ~9 MHz
#1011 : 11
6 ~7 MHz
#1100 : 12
5 ~6 MHz
#1101 : 13
4 ~5 MHz
#1111 : 15
Reserved.
End of enumeration elements list.
DVIEN : Data Valid Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled
#1 : 1
Interrupt Enabled
End of enumeration elements list.
READY : Random Number Generator Ready (Read Only)\nAfter ACT (TRNG_ACT[7]) bit is set, the READY bit become to 1 after a delay of 90us~120us.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
RNG is not ready or was not activated
#1 : 1
RNG is ready to be enabled
End of enumeration elements list.
Reversed : Reversed
bits : 8 - 31 (24 bit)
access : read-write
TRNG Data Register
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Random Number Generator Data (Read Only)\nThe DATA store the random number generated by TRNG and can be read only once.
bits : 0 - 7 (8 bit)
access : read-only
TRNG Activation Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACT : Random Number Generator Activation\nAfter enable the ACT bit, it will active the TRNG module and wait the READY (TRNG_CTL[7]) bit to become 1.\nNote: ACT is an enable bit of analog part. When TRNG is not required to generate random number, TRNGEN (TRNG_CTL[0]) bit and ACT bit should be set to 0 to reduce power consumption.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
TRNG inactive
#1 : 1
TRNG active
End of enumeration elements list.
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