CRYPTO_SHA_CTL

CRYPTO_SHA_DGST2

CRYPTO_SHA_DGST3

CRYPTO_SHA_DGST4

CRYPTO_SHA_DGST5

CRYPTO_SHA_DGST6

CRYPTO_SHA_DGST7

CRYPTO_SHA_DGST8

CRYPTO_SHA_DGST9

CRYPTO_SHA_DGST10

CRYPTO_SHA_DGST11

CRYPTO_SHA_STS

CRYPTO_SHA_KEYCNT

CRYPTO_SHA_SADDR

CRYPTO_SHA_DMACNT

CRYPTO_SHA_DATIN

CRYPTO_SHA_DGST0

CRYPTO_SHA_DGST1

START : SHA Engine Start\nNote: This bit is always 0 when it's read back.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOP : SHA Engine Stop\nNote: This bit is always 0 when it's read back.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMALAST : SHA Last Block\nThis bit must be set as feeding in last byte of data.
bits : 5 - 5 (1 bit)
access : read-write

DMAEN : SHA Engine DMA Enable Bit\nSHA engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE : SHA Engine Operation Modes\n0x0xx: SHA160\n0x100: SHA256\n0x101: SHA224\n0x110: reserved\n0x111: SHA384
bits : 8 - 10 (3 bit)
access : read-write

OUTSWAP : SHA Engine Output Data Swap
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INSWAP : SHA Engine Input Data Swap
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSY : SHA Engine Busy
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DMABUSY : SHA Engine DMA Busy Flag
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DMAERR : SHA Engine DMA Error Flag
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DATINREQ : SHA Non-dMA Mode Data Input Request
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

KEYCNT : SHA Key Byte Count\nThe CRYPTO_SHA_KEYCNT keeps the byte count of key that SHA/SHA engine operates. The register is 32-bit and the maximum byte count is 4G bytes. It can be read and written. \nWriting to the register CRYPTO_SHA_KEYCNT as the SHA/SHA accelerator operating doesn't affect the current SHA/SHA operation. But the value of CRYPTO_SHA _KEYCNT will be updated later on. Consequently, software can prepare the key count for the next SHA/SHA operation.
bits : 0 - 31 (32 bit)
access : read-write

SADDR : SHA DMA Source Address\nThe SHA accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO. The CRYPTO_SHA_SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the SHA accelerator can read the plain text from SRAM memory space and do SHA operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of CRYPTO_SHA_SADDR are ignored.\nCRYPTO_SHA_SADDR can be read and written. Writing to CRYPTO_SHA_SADDR while the SHA accelerator is operating doesn't affect the current SHA operation. But the value of CRYPTO_SHA_SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next SHA operation.\nIn DMA mode, software can update the next CRYPTO_SHA_SADDR before triggering START.\nCRYPTO_SHA_SADDR and CRYPTO_SHA_DADDR can be the same in the value.
bits : 0 - 31 (32 bit)
access : read-write

DMACNT : SHA Operation Byte Count\nThe CRYPTO_SHA_DMACNT keeps the byte count of source text that is for the SHA engine operating in DMA mode. The CRYPTO_SHA_DMACNT is 32-bit and the maximum of byte count is 4G bytes.\nCRYPTO_SHA_DMACNT can be read and written. Writing to CRYPTO_SHA_DMACNT while the SHA accelerator is operating doesn't affect the current SHA operation. But the value of CRYPTO_SHA_DMACNT will be updated later on. Consequently, software can prepare the byte count of data for the next SHA operation.\nIn Non-DMA mode, CRYPTO_SHA_DMACNT must be set as the byte count of the last block before feeding in the last block of data.
bits : 0 - 31 (32 bit)
access : read-write

DATIN : SHA Engine Input Port\nCPU feeds data to SHA engine through this port by checking CRYPTO_SHA_STS. Feed data as DATINREQ is 1.
bits : 0 - 31 (32 bit)
access : read-write

DGST : SHA Digest Message Output Register\nFor SHA-160, the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST4.\nFor SHA-224, the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST6.\nFor SHA-256, the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST7.\nFor SHA-384, the digest is stored in CRYPTO_SHA_DGST0 ~ CRYPTO_SHA_DGST11.
bits : 0 - 31 (32 bit)
access : read-only