Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x48 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x88 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC8 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
TDES/DES Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : TDES/DES Engine Start\nNote: The bit is always 0 when it's read back.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Start TDES/DES engine. The flag BUSY would be set
End of enumeration elements list.
STOP : TDES/DES Engine Stop\nNote: The bit is always 0 when it's read back.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Stop TDES/DES engine
End of enumeration elements list.
TMODE : TDES/DES Engine Operating Mode
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set DES mode for TDES/DES engine
#1 : 1
Set Triple DES mode for TDES/DES engine
End of enumeration elements list.
_3KEYS : TDES/DES Key Number
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Select KEY1 and KEY2 in TDES/DES engine
#1 : 1
Triple keys in TDES/DES engine Enabled
End of enumeration elements list.
DMALAST : TDES/DES Engine Start for the Last Block \nIn DMA mode, this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode, this bit must be set as feeding in last block of data.
bits : 5 - 5 (1 bit)
access : read-write
DMACSCAD : TDES/DES Engine DMA with Cascade Mode
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA cascade function Disabled
#1 : 1
In DMA Cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation
End of enumeration elements list.
DMAEN : TDES/DES Engine DMA Enable Bit\nTDES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
TDES_DMA engine Disabled
#1 : 1
TDES_DMA engine Enabled
End of enumeration elements list.
OPMODE : TDES/DES Engine Operation Mode
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x00 : 0
ECB (Electronic Codebook Mode)
0x01 : 1
CBC (Cipher Block Chaining Mode)
0x02 : 2
CFB (Cipher Feedback Mode)
0x03 : 3
OFB (Output Feedback Mode)
0x04 : 4
CTR (Counter Mode)
End of enumeration elements list.
ENCRYPTO : TDES/DES Encryption/Decryption
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
TDES engine executes decryption operation
#1 : 1
TDES engine executes encryption operation
End of enumeration elements list.
BLKSWAP : TDES/DES Engine Block Double Word Endian Swap
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Keep the original order, e.g. {WORD_H, WORD_L}
#1 : 1
When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H}
End of enumeration elements list.
OUTSWAP : TDES/DES Engine Output Data Swap
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Keep the original order
#1 : 1
The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
End of enumeration elements list.
INSWAP : TDES/DES Engine Input Data Swap
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Keep the original order
#1 : 1
The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
End of enumeration elements list.
CHANNEL : TDES/DES Engine Working Channel
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Current control register setting is for channel 0
#01 : 1
Current control register setting is for channel 1
#10 : 2
Current control register setting is for channel 2
#11 : 3
Current control register setting is for channel 3
End of enumeration elements list.
KEYUNPRT : Unprotect Key\nWriting 0 to CRYPTO_TDES_CTL [31] and '10110' to CRYPTO_TDES_CTL [30:26] is to unprotect TDES key.\nThe KEYUNPRT can be read and written. When it is written as the TDES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
bits : 26 - 30 (5 bit)
access : read-write
KEYPRT : Protect Key\nRead as a flag to reflect KEYPRT.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
This bit is to protect the content of TDES key from reading. The return value for reading CRYPTO_ TDESn_KEYxH/L is not the content in the registers CRYPTO_ TDESn_KEYxH/L. Once it is set, it can be cleared by asserting KEYUNPRT. The key content would be cleared as well
End of enumeration elements list.
TDES Key 2 High Word Register for Channel 0
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 Low Word Register for Channel 0
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 High Word Register for Channel 0
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 Low Word Register for Channel 0
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Initial Vector High Word Register for Channel 0
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IV : TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode. IV is Nonce counter for TDES/DES engine in CTR mode.
bits : 0 - 31 (32 bit)
access : read-write
TDES/DES Initial Vector Low Word Register for Channel 0
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES DMA Source Address Register for Channel 0
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : TDES/DES DMA Source Address\nThe TDES/DES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO. The CRYPTO_TDESn_SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the TDES/DES accelerator can read the plain text (encryption) / cipher text (decryption) from SRAM memory space and do TDES/DES operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of CRYPTO_TDESn_SADDR are ignored.\nCRYPTO_TDESn_SADDR can be read and written. Writing to CRYPTO_TDESn_SADDR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. But the value of CRYPTO_TDESn_SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next TDES/DES operation.\nIn DMA mode, software can update the next CRYPTO_TDESn_SADDR before triggering START.\nCRYPTO_TDESn_SADDR and CRYPTO_TDESn_DADDR can be the same in the value.
bits : 0 - 31 (32 bit)
access : read-write
TDES/DES DMA Destination Address Register for Channel 0
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : TDES/DES DMA Destination Address\nThe TDES/DES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO. The CRYPTO_TDESn_DADDR keeps the destination address of the data buffer where the engine output's text will be stored. Based on the destination address, the TDES/DES accelerator can write the cipher text (encryption) / plain text (decryption) back to SRAM memory space after the TDES/DES operation is finished. The start of destination address should be located at word boundary. In other words, bit 1 and 0 of CRYPTO_TDESn_DADDR are ignored.\nCRYPTO_TDESn_DADDR can be read and written. Writing to CRYPTO_TDESn_DADDR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. But the value of CRYPTO_TDESn_DADDR will be updated later on. Consequently, software can prepare the destination address for the next TDES/DES operation.\nIn DMA mode, software can update the next CRYPTO_TDESn_DADDR before triggering START. \nCRYPTO_TDESn_SADDR and CRYPTO_TDESn_DADDR can be the same in the value.
bits : 0 - 31 (32 bit)
access : read-write
TDES/DES Byte Count Register for Channel 0
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : TDES/DES Byte Count \nThe CRYPTO_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode. The CRYPTO_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.\nCRYPTO_TDESn_CNT can be read and written. Writing to CRYPTO_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. But the value of CRYPTO_TDESn_CNT will be updated later on. Consequently, software can prepare the byte count of data for the next TDES /DES operation.\nIn Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRYPTO_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
bits : 0 - 31 (32 bit)
access : read-write
TDES/DES Engine Input Data Word Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATIN : TDES/DES Engine Input Port\nCPU feeds data to TDES/DES engine through this port by checking CRYPTO_TDES_STS. Feed data as INBUFFULL is 0.
bits : 0 - 31 (32 bit)
access : read-write
TDES/DES Engine Output Data Word Register
address_offset : 0x38 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATOUT : TDES/DES Engine Output Port\nCPU gets result from the TDES/DES engine through this port by checking CRYPTO_TDES_STS. Get data as OUTBUFEMPTY is 0.
bits : 0 - 31 (32 bit)
access : read-only
TDES/DES Engine Flag
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : TDES/DES Engine Busy
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
TDES/DES engine is idle or finished
#1 : 1
TDES/DES engine is under processing
End of enumeration elements list.
INBUFEMPTY : TDES/DES in Buffer Empty
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
There are some data in input buffer waiting for the TDES/DES engine to process
#1 : 1
TDES/DES input buffer is empty. Software needs to feed data to the TDES/DES engine. Otherwise, the TDES/DES engine will be pending to wait for input data
End of enumeration elements list.
INBUFFULL : TDES/DES in Buffer Full Flag
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
TDES/DES input buffer is not full. Software can feed the data into the TDES/DES engine
#1 : 1
TDES input buffer is full. Software cannot feed data to the TDES/DES engine. Otherwise, the flag INBUFERR will be set to 1
End of enumeration elements list.
INBUFERR : TDES/DES in Buffer Error Flag
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Error happens during feeding data to the TDES/DES engine
End of enumeration elements list.
OUTBUFEMPTY : TDES/DES Output Buffer Empty Flag
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
TDES/DES output buffer is not empty. There are some valid data kept in output buffer
#1 : 1
TDES/DES output buffer is empty, Software cannot get data from TDES_DATA_OUT. Otherwise the flag OUTBUFERR will be set to 1, since output buffer is empty
End of enumeration elements list.
OUTBUFFULL : TDES/DES Output Buffer Full Flag
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
TDES/DES output buffer is not full
#1 : 1
TDES/DES output buffer is full, and software needs to get data from TDES_DATA_OUT. Otherwise, the TDES/DES engine will be pending since output buffer is full
End of enumeration elements list.
OUTBUFERR : TDES/DES Out Buffer Error Flag
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Error happens during getting test result from TDES/DES engine
End of enumeration elements list.
BUSERR : TDES/DES DMA Access Bus Error Flag
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Bus error will stop DMA operation and TDES/DES engine
End of enumeration elements list.
TDES/DES Key 1 High Word Register for Channel 1
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Key 1 Low Word Register for Channel 1
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 High Word Register for Channel 1
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 Low Word Register for Channel 1
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 High Word Register for Channel 1
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 Low Word Register for Channel 1
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Initial Vector High Word Register for Channel 1
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Initial Vector Low Word Register for Channel 1
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES DMA Source Address Register for Channel 1
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES DMA Destination Address Register for Channel 1
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Byte Count Register for Channel 1
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Key 1 High Word Register for Channel 0
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits. Thus, it needs two 32-bit registers to store a security key. The register CRYPTO_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRYPTO_TDESn_KEYxL is used to keep the bit [31:0].
bits : 0 - 31 (32 bit)
access : read-write
TDES/DES Key 1 High Word Register for Channel 2
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Key 1 Low Word Register for Channel 2
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 High Word Register for Channel 2
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 Low Word Register for Channel 2
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 High Word Register for Channel 2
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 Low Word Register for Channel 2
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Initial Vector High Word Register for Channel 2
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Initial Vector Low Word Register for Channel 2
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES DMA Source Address Register for Channel 2
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES DMA Destination Address Register for Channel 2
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Byte Count Register for Channel 2
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Key 1 Low Word Register for Channel 0
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Key 1 High Word Register for Channel 3
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Key 1 Low Word Register for Channel 3
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 High Word Register for Channel 3
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 Low Word Register for Channel 3
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 High Word Register for Channel 3
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 Low Word Register for Channel 3
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Initial Vector High Word Register for Channel 3
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Initial Vector Low Word Register for Channel 3
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES DMA Source Address Register for Channel 3
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES DMA Destination Address Register for Channel 3
address_offset : 0xEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Byte Count Register for Channel 3
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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