\n
address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
LCD Configuration Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BIAS : Bias Voltage Level Selection\nThis field is used to select the bias voltage level of LCD controller.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : 0
Reserved.
1 : 1
1/2 bias
2 : 2
1/3 bias
3 : 3
1/4 Bias
End of enumeration elements list.
TYPE : LCD Waveform Type Selection\nThis field is used to select the driving waveform type of LCD controller.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Type A
#1 : 1
Type B
End of enumeration elements list.
DUTY : COM Duty Ratio Selection\nThis field is used to select the LCD operating duty ratio.\nNote: When 1/3 duty is selected, only COM0 to COM2 are for LCD driving; if 1/8 duty is selected, COM0 to COM7 are for LCD driving.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : 0
1/1 duty
1 : 1
1/2 duty
2 : 2
1/3 duty
3 : 3
1/4 duty
4 : 4
1/5 duty
5 : 5
1/6 duty
6 : 6
1/7 duty
7 : 7
1/8 duty
End of enumeration elements list.
FREQDIV : LCD Operating Frequency Divider\nThe FREQDIV of LCD controller is used to divide the LCD_CLK to generate LCD operating frequency.
bits : 8 - 17 (10 bit)
access : read-write
LCD Segment Display Control Register 2
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCD Segment Display Control Register 3
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCD Segment Display Control Register 4
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCD Segment Display Control Register 5
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCD Segment Display Control Register 6
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCD Segment Display Control Register 7
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCD Segment Display Control Register 8
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCD Segment Display Control Register 9
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCD Segment Display Control Register 10
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCD Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : LCD Display Enable Bit\nNote: User should read SYNC (LCD_CTL[31]) bit to check if to enable/disable LCD display is completed or not.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
LCD display function Disabled
#1 : 1
LCD display function Enabled
End of enumeration elements list.
BLINK : LCD Blinking Enable Bit\nNote 1: Blinking frequency is determined by the frame counting event.\nNote 2: LCD blinking function can work normal even if MCU is in Power-down mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
LCD blinking function Disabled
#1 : 1
LCD blinking function Enabled
End of enumeration elements list.
WVREV : Waveform Reverse
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
COM/SEG waveform is normal
#1 : 1
COM/SEG waveform is reversed
End of enumeration elements list.
FCV : Frame Counting Value\nThis field indicates the frame counting value to genetate the frame counting event.\nThe target frame counting event period is (FCV + 1) frames.\nNote: The FCV is rom 0, 1, 2... to 1023, thus the frame counting event period can be selected from 1, 2, 3... to 1024 frames.
bits : 8 - 17 (10 bit)
access : read-write
SYNC : LCD Enable Control SYNC Flag Indicator (Read Only)\nIf user executes enable/disable EN (LCD_CTL[0]), this flag can be indicated enable/disable EN function is completed or not. \nNote: Set LCD EN bit 1 to trun on the LCD display needs 2 * LCD_CLK period to become active. Set LCD EN bit 0 to turn off the LCD display, the LCD display cannot be turned off immediately until the end of frame is reached. Therefore, user should read SYNC bit to check if setting LCD EN bit is completed or not.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
Set EN bit 0 or 1 is completed
#1 : 1
Set EN bit is synchronizing and not become active yet
End of enumeration elements list.
LCD Interrupt Enable Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCIEN : Frame Counting Interrupt Enable Bit\nThis bit is used to enable frame counting interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame Counting Interrupt Disabled
#1 : 1
Frame Counting Interrupt Enabled
End of enumeration elements list.
FEIEN : Frame End Interrupt Enable Bit\nThis bit is used to enable frame end interrupt.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame End Interrupt Disabled
#1 : 1
Frame End Interrupt Enabled
End of enumeration elements list.
LCD Interrupt Status Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCIF : Frame Counting Interrupt Flag\nThis flag indicates that current frame counter value has reached to FCV (LCD_CTL[17:8] Frame Counting Value).\nNote: This bit can be cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame counting event did not occur
#1 : 1
Frame counting event occurred
End of enumeration elements list.
FEIF : Frame End Interrupt Flag\nThis flag indicates that current frame display has completed.\nNote: This bit can be cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame end event did not occur
#1 : 1
Frame end event occurred
End of enumeration elements list.
LCD Segment Display Control Register 0
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0 : Segment Display on Data Region 0\nThis field is used to set specify segment display 'Selected' or 'Deselected' on COM0 to COM7.
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : 0
Correspond segment display is Deselected
1 : 1
Correspond segment display is Selected
End of enumeration elements list.
DATA1 : Segment Display on Data Region 1\nThis field is used to set specify segment display 'Selected' or 'Deselected' on COM0 to COM7.
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
0 : 0
Correspond segment display is Deselected
1 : 1
Correspond segment display is Selected
End of enumeration elements list.
DATA2 : Segment Display on Data Region 2\nThis field is used to set specify segment display 'Selected' or 'Deselected' on COM0 to COM7.
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0 : 0
Correspond segment display is Deselected
1 : 1
Correspond segment display is Selected
End of enumeration elements list.
DATA3 : Segment Display on Data Region 3\nThis field is used to set specify segment display 'Selected' or 'Deselected' on COM0 to COM7.
bits : 24 - 31 (8 bit)
access : read-write
Enumeration:
0 : 0
Correspond segment display is Deselected
1 : 1
Correspond segment display is Selected
End of enumeration elements list.
LCD Segment Display Control Register 1
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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