Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xF0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1EC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x24 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1F8 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x144 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x188 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
Part Device Identification Number Register
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDID : Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only
Peripheral Reset Control Register 2
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SC0RST : SC0 Controller Reset
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SC0 controller normal operation
#1 : 1
SC0 controller reset
End of enumeration elements list.
USCI0RST : USCI0 Controller Reset
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
USCI0 controller normal operation
#1 : 1
USCI0 controller reset
End of enumeration elements list.
USCI1RST : USCI1 Controller Reset
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
USCI1 controller normal operation
#1 : 1
USCI1 controller reset
End of enumeration elements list.
USCI2RST : USCI2 Controller Reset
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
USCI2 controller normal operation
#1 : 1
USCI2 controller reset
End of enumeration elements list.
DACRST : DAC Controller Reset
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC controller normal operation
#1 : 1
DAC controller reset
End of enumeration elements list.
SLCDRST : SLCD Controller Reset
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Segment LCD controller normal operation
#1 : 1
Segment LCD controller reset
End of enumeration elements list.
TKRST : Touch Key Controller Reset
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Touch Key controller normal operation
#1 : 1
Touch Key controller reset
End of enumeration elements list.
PWM0RST : PWM0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0 controller normal operation
#1 : 1
PWM0 controller reset
End of enumeration elements list.
PWM1RST : PWM1 Controller Reset
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1 controller normal operation
#1 : 1
PWM1 controller reset
End of enumeration elements list.
BPWM0RST : BPWM0 Controller Reset
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM0 controller normal operation
#1 : 1
BPWM0 controller reset
End of enumeration elements list.
BPWM1RST : BPWM1 Controller Reset
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM1 controller normal operation
#1 : 1
BPWM1 controller reset
End of enumeration elements list.
OPARST : OP Amplifier (OPA) Controller Reset
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OPA controller normal operation
#1 : 1
OPA controller reset
End of enumeration elements list.
PSIORST : PSIORST
bits : 31 - 31 (1 bit)
access : read-write
Register Lock Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGLCTL : Register Lock Control Code
Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h', '16h', '88h' to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
Register Lock Control Disable Index
The Protected registers are:
NMIEN address 0x4000_0300
FMC_ISPCTL address 0x4000_C000 (Flash ISP Control register)
FMC_ISPTRG address 0x4000_C010 (ISP Trigger Control register)
FMC_ISPSTS address 0x4000_C040
WDT_CTL address 0x4004_0000
FMC_FTCTL address 0x4000_5018
FMC_ICPCMD address 0x4000_501C
EADC_TEST address 0x4004_3200
AHBMCTL address 0x4000_0400
SYS_IPRST0 address 0x4000_0008
SYS_BODCTL address 0x4000_0018
SYS_PORCTL0 address 0x4000_0024
SYS_SRAM_BISTCTL address 0x4000_00D0
SYS_PORCTL1 address 0x4000_1EC
CLK_PWRCTL address 0x4000_0200
CLK_APBCLK0[0] address 0x4000_0208
CLK_CLKSEL0 address 0x4000_0110
CLK_CLKSEL1[3:0] address 0x4000_0214
CLK_PLLCTL address 0x4000_0240
CLK_PMUCTL address 0x4000_0290
CLK_HXTFSEL address 0x4000_02B4
PWM_CTL0 address 0x4005_8000
PWM_CTL0 address 0x4005_9000
PWM_DTCTL0_1 address 0x4005_8070
PWM_DTCTL0_1 address 0x4005_9070
PWM_DTCTL2_3 address 0x4005_8074
PWM_DTCTL2_3 address 0x4005_9074
PWM_DTCTL4_5 address 0x4005_8078
PWM_DTCTL4_5 address 0x4005_9078
PWM_BRKCTL0_1 address 0x4005_80C8
PWM_BRKCTL0_1 address 0x4005_90C8
PWM_BRKCTL2_3 address0x4005_80CC
PWM_BRKCTL2_3 address0x4005_90CC
PWM_BRKCTL4_5 address0x4005_80D0
PWM_BRKCTL4_5 address0x4005_90D0
PWM_INTEN1 address0x4005_80E4
PWM_INTEN1 address0x4005_90E4
PWM_INTSTS1 address0x4005_80EC
PWM_INTSTS1 address0x4005_90EC
PWM_SELFTEST address0x4005_8300
PWM_SELFTEST address0x4005_930
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : 0
Write-protection Enabled for writing protected registers. Any write to the protected register is ignored
1 : 1
Write-protection Disabled for writing protected registers
End of enumeration elements list.
MIRC Trim Control Register
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQSEL : Trim Frequency Selection\nThis field indicates the target frequency of medium speed RC oscillator (MIRC) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Disable HIRC auto trim function
#01 : 1
Reserved.
#10 : 2
Enable HIRC auto trim function and trim MIRC to 4.032 MHz
End of enumeration elements list.
LOOPSEL : Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved.
#01 : 1
Trim value calculation is based on average difference in 8 clocks of reference clock
#10 : 2
Trim value calculation is based on average difference in 16 clocks of reference clock
#11 : 3
Trim value calculation is based on average difference in 32 clocks of reference clock
End of enumeration elements list.
RETRYCNT : Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the MIRC trim value before the frequency of MIRC locked.\nOnce the MIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of MIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim retry count limitation is 64 loops
#01 : 1
Trim retry count limitation is 128 loops
#10 : 2
Trim retry count limitation is 256 loops
#11 : 3
Trim retry count limitation is 512 loops
End of enumeration elements list.
CESTOPEN : Clock Error Stop Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The trim operation keeps going if clock is inaccurate
#1 : 1
The trim operation stops if clock is inaccurate
End of enumeration elements list.
BOUNDEN : Boundary Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Boundary function Disabled
#1 : 1
Boundary function Enabled
End of enumeration elements list.
REFCKSEL : Reference Clock Selection
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
MIRC trim reference clock is from LXT (32.768 kHz)
#1 : 1
MIRC trim reference clock is from internal USB synchronous mode
End of enumeration elements list.
BOUNDARY : Boundary Selection\nFill the boundary range from 0x1 to 0x1F, 0x0 is reserved.\nNote: This field is effective only when the BOUNDEN(SYS_MIRCTRIMCTL[9]) is enabled
bits : 16 - 20 (5 bit)
access : read-write
MIRC Trim Interrupt Enable Register
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFALIEN : Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while MIRC trim value update limitation count reached and MIRC frequency still not locked on target frequency set by FREQSEL(SYS_ MIRTRIMCTL[1:0]).\nIf this bit is high and TFAILIF(SYS_ MIRCTRIMSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that MIRC trim value update limitation count was reached.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable TFAILIF(SYS_MIRCTRIMSTS[1]) status to trigger an interrupt to CPU
#1 : 1
Enable TFAILIF(SYS_MIRCTRIMSTS[1]) status to trigger an interrupt to CPU
End of enumeration elements list.
CLKEIEN : Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_MIRCTRIMSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable CLKERRIF(SYS_MIRCTRIMSTS[2]) status to trigger an interrupt to CPU
#1 : 1
Enable CLKERRIF(SYS_MIRCTRIMSTS[2]) status to trigger an interrupt to CPU
End of enumeration elements list.
MIRC Trim Interrupt Status Register
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQLOCK : MIRC Frequency Lock Status\nThis bit indicates the MIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt\nWrite 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled. \nNote: Reset by power on reset.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The internal medium-speed oscillator frequency isn't locked
#1 : 1
The internal medium-speed oscillator frequency locked
End of enumeration elements list.
TFAILIF : Trim Failure Interrupt Status\nThis bit indicates that MIRC trim value update limitation count reached and the MIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_MIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_MIRCTRIMIEN[1]) is high, an interrupt will be triggered to notify that MIRC trim value update limitation count was reached. Write 1 to clear this to 0.\nNote: Reset by power on reset.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trim value update limitation count does not reach
#1 : 1
Trim value update limitation count reached and MIRC frequency still not locked
End of enumeration elements list.
CLKERIF : Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or internal medium speed RC oscillator (MIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_MIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_MIRCTRIMCTL[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_MIRCTRIMIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.\nNote: Reset by power on reset.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock frequency is accuracy
#1 : 1
Clock frequency is inaccuracy
End of enumeration elements list.
OVBDIF : Over Boundary Status\nWhen the over boundary function is set, if there occurs the over boundary condition, this flag will be set.\nNote: Write 1 to clear this flag.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Over boundary coundition did not occur
#1 : 1
Over boundary coundition occurred
End of enumeration elements list.
RTC LVR Interrupt Control Register
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IE : RTC LVR Interrupt Enable Bit (Write Protect)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC LVR Interrupt Disabled (default)
#1 : 1
RTC LVR Interrupt Enabled
End of enumeration elements list.
RTC LVR Interrupt Status Register
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IF : RTC LVR Interrupt Flag\nWhen a positive edge of RTCLVR is detected, this bit will be set to 1 and will be cleared when a 1 is set to this bit\nThis bit is write protected
bits : 0 - 0 (1 bit)
access : read-write
RTCLVR : RTCLVR value (read only)
bits : 8 - 8 (1 bit)
access : read-only
Brown-out Detector Control Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BODEN : Brown-out Detector Enable Bit (Write Protect)
The default value is set by Flash controller user configuration register CBODEN (CONFIG0 [19]).
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: Reset by power on reset.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector function Disabled
#1 : 1
Brown-out Detector function Enabled
End of enumeration elements list.
BODRSTEN : Brown-out Reset Enable Bit (Write Protect)
The default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit.
Note 1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will keep till to the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
Note 2: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 3: Reset by power on reset.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out 'INTERRUPT' function Enabled
#1 : 1
Brown-out 'RESET' function Enabled
End of enumeration elements list.
BODIF : Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting
#1 : 1
When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled
End of enumeration elements list.
BODLPM : Brown-out Detector Low Power Mode (Write Protect)
Note 1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
Note 2: For BOD low power mode to be active, LVREN must be set to 1
Note 3: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
BOD operate in normal mode (default)
#1 : 1
BOD Low Power mode Enabled
End of enumeration elements list.
BODOUT : Brown-out Detector Output Status\nIt means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled, this bit always responds 0000.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector output status is 0
#1 : 1
Brown-out Detector output status is 1
End of enumeration elements list.
LVREN : Low Voltage Reset Enable Bit (Write Protect)
The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.
Note 1: After enabling the bit, the LVR function will be active with 3ms delay for LVR output stable (default).
Note 2: For BOD low power mode to be active, this bit must be set to 1.
Note 3: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low Voltage Reset function Disabled
#1 : 1
Low Voltage Reset function Enabled
End of enumeration elements list.
BODDGSEL : Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
BOD output is sampled by LIRC
#001 : 1
4 system clock (HCLK)
#010 : 2
8 system clock (HCLK)
#011 : 3
16 system clock (HCLK)
#100 : 4
32 system clock (HCLK)
#101 : 5
64 system clock (HCLK)
#110 : 6
128 system clock (HCLK)
#111 : 7
256 system clock (HCLK)
End of enumeration elements list.
LVRDGSEL : LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.\nNote: The MIRC enabled automatically when LVRDGSEL is not 000 and LVREN is 1.
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Without de-glitch function
#001 : 1
4 MIRC clock (4 MHz), 1 us
#010 : 2
8 MIRC clock (4 MHz), 2 us
#011 : 3
16 MIRC clock (4 MHz), 4 us
#100 : 4
32 MIRC clock (4 MHz), 8 us
#101 : 5
64 MIRC clock (4 MHz), 16 us
#110 : 6
128 MIRC clock (4 MHz), 32 us
#111 : 7
256 MIRC clock (4 MHz), 64 us
End of enumeration elements list.
BODVL : Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by Flash controller user configuration register CBOV (CONFIG0 [23:21]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote: Reset by power on reset.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
Reserved.
#001 : 1
Brown-Out Detector threshold voltage is 1.8V
#010 : 2
Brown-Out Detector threshold voltage is 2.0V
#011 : 3
Brown-Out Detector threshold voltage is 2.4V
#100 : 4
Brown-Out Detector threshold voltage is 2.7V
#101 : 5
Brown-Out Detector threshold voltage is 3.0V
#110 : 6
Brown-Out Detector threshold voltage is 3.7V
#111 : 7
Brown-Out Detector threshold voltage is 4.4V
End of enumeration elements list.
HIRC Test Mode Control Register
address_offset : 0x188 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Internal Voltage Source Control Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTEMPEN : Temperature Sensor Enable Bit
This bit is used to enable/disable temperature sensor function.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Temperature sensor function Disabled (default)
#1 : 1
Temperature sensor function Enabled
End of enumeration elements list.
VBATUGEN : VBAT Unity Gain Buffer Enable Bit\nThis bit is used to enable/disable VBAT unity gain buffer function.\nNote: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
VBAT unity gain buffer function Disabled (default)
#1 : 1
VBAT unity gain buffer function Enabled
End of enumeration elements list.
Power-On-reset Controller Register 1
address_offset : 0x1EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POROFF : Power-on Reset Enable Bit (Write Protect)\nAfter powered on, User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field.\nThe analog POR circuit will be active again when this field is set to another value or chip is reset by other reset source, including:\nnRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 15 (16 bit)
access : read-write
Power Level Control Register
address_offset : 0x1F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSEL : Power Level Select(Write Protect)\nNote : When at PL2, HCLK has to be lower than 4Mhz
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Set to power level 0 (PL0)
#01 : 1
Reserved.
#10 : 2
Set to power level 2 (PL2) [Internal note: this mode is MLDO low power mode]
#11 : 3
Reserved.
End of enumeration elements list.
Power Level Status Register
address_offset : 0x1FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLCBUSY : Power Level Change Busy Bit (Read Only)\nThis bit is set by hardware when power level is changing. After power level change is completed, this bit will be cleared automatically by hardware.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Power level change is completed
#1 : 1
Power level change is ongoing
End of enumeration elements list.
CURPL : Current Power Level (Read Only)\nThis bit field reflect the current power level.
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
#00 : 0
Current power level is PL0
#01 : 1
Reserved.
#10 : 2
Current power level is PL2. [Internal note: this mode is MLDO low power mode]
End of enumeration elements list.
Power-On-reset Controller Register 0
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORMASK : Power-on Reset Mask Enable Bit (Write Protect)\nWhen powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can mask internal POR signal to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.\nThe POR function will be active again when this field is set to another value or chip is reset by other reset source, including:\nnRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 15 (16 bit)
access : read-write
VREF Control Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVRS : Internal Voltage Reference Scale (Write Protect)
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0 : 0
Internal voltage reference(INT_VREF) set to 1.536V
1 : 1
Internal voltage reference(INT_VREF) set to 2.048V
2 : 2
Internal voltage reference(INT_VREF) set to 2.56V
3 : 3
Internal voltage reference(INT_VREF) set to 3.072V
4 : 4
Internal voltage reference(INT_VREF) set to 4.096V
End of enumeration elements list.
IVREN : Internal Voltage Reference Module Enable Bit (Write Protect)
Note: INT_VREF is only supported while package includes VREF pin with external capacitor.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal voltage reference module Disabled
#1 : 1
Internal voltage reference module Enabled
End of enumeration elements list.
PRELOAD : Preload Enable Bit\nNote: This bit is used to speed up charging external capacitor of VREF.If INT_VREF voltage is stable, this bit has to be disabled.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Preload Disabled (default)
#1 : 1
Preload Enabled
End of enumeration elements list.
GPIOA Low Byte Multiple Function Control Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA0MFP : PA.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PA1MFP : PA.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PA2MFP : PA.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PA3MFP : PA.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PA4MFP : PA.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PA5MFP : PA.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PA6MFP : PA.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PA7MFP : PA.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOA High Byte Multiple Function Control Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA8MFP : PA.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PA9MFP : PA.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PA10MFP : PA.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PA11MFP : PA.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PA12MFP : PA.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PA13MFP : PA.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PA14MFP : PA.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PA15MFP : PA.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOB Low Byte Multiple Function Control Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB0MFP : PB.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PB1MFP : PB.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PB2MFP : PB.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PB3MFP : PB.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PB4MFP : PB.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PB5MFP : PB.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PB6MFP : PB.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PB7MFP : PB.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOB High Byte Multiple Function Control Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB8MFP : PB.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PB9MFP : PB.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PB10MFP : PB.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PB11MFP : PB.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PB12MFP : PB.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PB13MFP : PB.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PB14MFP : PB.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PB15MFP : PB.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
System Reset Status Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORF : POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from POR or CHIPRST
#1 : 1
Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system
End of enumeration elements list.
PINRF : NRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from nRESET pin
#1 : 1
Pin nRESET had issued the reset signal to reset the system
End of enumeration elements list.
WDTRF : WDT Reset Flag
The WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
Note 1: Write 1 to clear this bit to 0.
Note 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from watchdog timer or window watchdog timer
#1 : 1
The watchdog timer or window watchdog timer had issued the reset signal to reset the system
End of enumeration elements list.
LVRF : LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from LVR
#1 : 1
LVR controller had issued the reset signal to reset the system
End of enumeration elements list.
BODRF : BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from BOD
#1 : 1
The BOD had issued the reset signal to reset the system
End of enumeration elements list.
SYSRF : System Reset Flag\nThe system reset flag is set by the 'Reset Signal' from the CortexM23Core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from Cortex-M23
#1 : 1
The Cortex- M23 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M23core
End of enumeration elements list.
PMURF : PMU Reset Flag, \nThe PMU reset flag is set by any reset signal when MCU is in power down state.\nNote: Write 1 to clear this bit to 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset in power down state
#1 : 1
Any reset signal happens in power down state
End of enumeration elements list.
CPURF : CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex- M23Core and Flash Memory Controller (FMC).\nNote: Write 1 to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from CPU
#1 : 1
The Cortex-M23 Core and FMC are reset by software setting CPURST to 1
End of enumeration elements list.
CPULKRF : CPU Lockup Reset Flag
Note: Write 1 to clear this bit to 0.
Note 2: When CPU lockup happened under ICE is connected, This flag will set to 1 but chip will not reset.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from CPU lockup happened
#1 : 1
The Cortex-M23lockup happened and chip is reset
End of enumeration elements list.
VBATLVRF : VBAT LVR Reset Flag\nThe VBAT LVR reset flag is set by the 'Reset Signal' from the VBAT Low Voltage Reset Controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from VBAT LVR
#1 : 1
VBAT LVR controller had issued the reset signal to reset the system
End of enumeration elements list.
GPIOC Low Byte Multiple Function Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC0MFP : PC.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PC1MFP : PC.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PC2MFP : PC.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PC3MFP : PC.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PC4MFP : PC.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PC5MFP : PC.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PC6MFP : PC.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PC7MFP : PC.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOC High Byte Multiple Function Control Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC8MFP : PC.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PC9MFP : PC.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PC10MFP : PC.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PC11MFP : PC.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PC12MFP : PC.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PC13MFP : PC.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PC14MFP : PC.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PC15MFP : PC.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOD Low Byte Multiple Function Control Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD0MFP : PD.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PD1MFP : PD.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PD2MFP : PD.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PD3MFP : PD.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PD4MFP : PD.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PD5MFP : PD.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PD6MFP : PD.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PD7MFP : PD.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOD High Byte Multiple Function Control Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD8MFP : PD.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PD9MFP : PD.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PD10MFP : PD.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PD11MFP : PD.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PD12MFP : PD.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PD13MFP : PD.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PD14MFP : PD.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PD15MFP : PD.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOE Low Byte Multiple Function Control Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE0MFP : PE.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PE1MFP : PE.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PE2MFP : PE.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PE3MFP : PE.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PE4MFP : PE.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PE5MFP : PE.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PE6MFP : PE.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PE7MFP : PE.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOE High Byte Multiple Function Control Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE8MFP : PE.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PE9MFP : PE.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PE10MFP : PE.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PE11MFP : PE.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PE12MFP : PE.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PE13MFP : PE.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PE14_MFP : PE.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PE15_MFP : PE.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOF Low Byte Multiple Function Control Register
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF0MFP : PF.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PF1MFP : PF.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PF2MFP : PF.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PF3MFP : PF.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PF4MFP : PF.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PF5MFP : PF.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PF6MFP : PF.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PF7MFP : PF.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOF High Byte Multiple Function Control Register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF8MFP : PF.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PF9MFP : PF.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PF10MFP : PF.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PF11MFP : PF.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PF12MFP : PF.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PF13MFP : PF.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PF14MFP : PF.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PF15MFP : PF.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Peripheral Reset Control Register 0
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIPRST : Chip One-shot Reset (Write Protect)
Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from Flash are also reload.
For the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2
Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note 2: Reset by power on reset
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip normal operation
#1 : 1
Chip one-shot reset
End of enumeration elements list.
CPURST : Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Processor core normal operation
#1 : 1
Processor core one-shot reset
End of enumeration elements list.
PDMARST : PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA controller normal operation
#1 : 1
PDMA controller reset
End of enumeration elements list.
EBIRST : EBI Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the EBI. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI controller normal operation
#1 : 1
EBI controller reset
End of enumeration elements list.
CRCRST : CRC Calculation Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
CRC calculation controller normal operation
#1 : 1
CRC calculation controller reset
End of enumeration elements list.
CRYPTRST : CRYPTO Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the CRYPTO controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
CRYPTO controller normal operation
#1 : 1
CRYPTO controller reset
End of enumeration elements list.
GPIOA Multiple Function Output Select Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MFOS0 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS1 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS2 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS3 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS4 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS5 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS6 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS7 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS8 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS9 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS10 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS11 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS12 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS13 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS14 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS15 : GPIOA-f Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple funtion pin output mode type is Push-pull mode
#1 : 1
Multiple funtion pin output mode type is Open-drain mode
End of enumeration elements list.
GPIOB Multiple Function Output Select Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOC Multiple Function Output Select Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOD Multiple Function Output Select Register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOE Multiple Function Output Select Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOF Multiple Function Output Select Register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Peripheral Reset Control Register 1
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIORST : GPIO Controller Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO controller normal operation
#1 : 1
GPIO controller reset
End of enumeration elements list.
TMR0RST : Timer0 Controller Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 controller normal operation
#1 : 1
Timer0 controller reset
End of enumeration elements list.
TMR1RST : Timer1 Controller Reset
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 controller normal operation
#1 : 1
Timer1 controller reset
End of enumeration elements list.
TMR2RST : Timer2 Controller Reset
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 controller normal operation
#1 : 1
Timer2 controller reset
End of enumeration elements list.
TMR3RST : Timer3 Controller Reset
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer3 controller normal operation
#1 : 1
Timer3 controller reset
End of enumeration elements list.
ACMP01RST : Analog Comparator 0/1 Controller Reset
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog Comparator 0/1 controller normal operation
#1 : 1
Analog Comparator 0/1 controller reset
End of enumeration elements list.
I2C0RST : I2C0 Controller Reset
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C0 controller normal operation
#1 : 1
I2C0 controller reset
End of enumeration elements list.
I2C1RST : I2C1 Controller Reset
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C1 controller normal operation
#1 : 1
I2C1 controller reset
End of enumeration elements list.
QSPI0RST : QSPI0 Controller Reset
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
QSPI0 controller normal operation
#1 : 1
QSPI0 controller reset
End of enumeration elements list.
SPI0RST : SPI0 Controller Reset
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI0 controller normal operation
#1 : 1
SPI0 controller reset
End of enumeration elements list.
UART0RST : UART0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 controller normal operation
#1 : 1
UART0 controller reset
End of enumeration elements list.
UART1RST : UART1 Controller Reset
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 controller normal operation
#1 : 1
UART1 controller reset
End of enumeration elements list.
UART2RST : UART2 Controller Reset
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART2 controller normal operation
#1 : 1
UART2 controller reset
End of enumeration elements list.
USBDRST : USBD Controller Reset
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
USBD controller normal operation
#1 : 1
USBD controller reset
End of enumeration elements list.
EADCRST : EADC Controller Reset
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
EADC controller normal operation
#1 : 1
EADC controller reset
End of enumeration elements list.
Modulation Control Register
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODEN : Modulation Function Enable Bit\nThis bit enables modulation funcion by modulating with PWM0 channel output and USCI0(USCI0_DAT1) or UART0(UART0_TXD) output.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Modulation Function Disabled
#1 : 1
Modulation Function Enabled
End of enumeration elements list.
MODH : Modulation at Data High\nSelect modulation pulse(PWM0) at high or low of UART0_TXD or USCI0_DAT1
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Modulation pulse at UART0_TXD low or USCI0_DAT1 low
#1 : 1
Modulation pulse at UART0_TXD high or USCI0_DAT1 high
End of enumeration elements list.
MODPWMSEL : PWM0 Channel Select for Modulation\nSelect the PWM0 channel to modulate with the UART0_TXD or USCI0_DAT1.\n0000: PWM0 Channel 0 modulate with UART0_TXD.\n0001: PWM0 Channel 1 modulate with UART0_TXD.\n0010: PWM0 Channel 2 modulate with UART0_TXD.\n0011: PWM0 Channel 3 modulete with UART0_TXD.\n0100: PWM0 Channel 4 modulete with UART0_TXD.\n0101: PWM0 Channel 5 modulete with UART0_TXD.\n0110: Reserved.\n0111: Reserved.\n1000: PWM0 Channel 0 modulate with USCI0_DAT1.\n1001: PWM0 Channel 1 modulate with USCI0_DAT1.\n1010: PWM0 Channel 2 modulate with USCI0_DAT1.\n1011: PWM0 Channel 3 modulete with USCI0_DAT1.\n1100: PWM0 Channel 4 modulete with USCI0_DAT1.\n1101: PWM0 Channel 5 modulete with USCI0_DAT1.\n1110: Reserved.\n1111: Reserved.\nNote: This bis is valid while MODEN (SYS_MODCTL[0]) is set to 1.
bits : 4 - 7 (4 bit)
access : read-write
System SRAM BIST Test Control Register
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRBIST : SRAM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for SRAM.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
System SRAM BIST Disabled
#1 : 1
System SRAM BIST Enabled
End of enumeration elements list.
FMCBIST : FMC CACHE BIST Enable Bit (Write Protect)\nThis bit enables BIST test for CACHE RAM\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
System CACHE BIST Disabled
#1 : 1
System CACHE BIST Enabled
End of enumeration elements list.
USBBIST : USB BIST Enable Bit (Write Protect) \nThis bit enables BIST test for USB RAM\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
System USB BIST Disabled
#1 : 1
System USB BIST Enabled
End of enumeration elements list.
PDMABIST : PDMA BIST Enable Bit (Write Protect)\nThis bit enables BIST test for PDMA RAM\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
System PDMA BIST Disabled
#1 : 1
Sstem PDMA BIST Enabled
End of enumeration elements list.
System SRAM BIST Test Status Register
address_offset : 0xD4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SRBISTEF : System SRAM BIST Fail Flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
System SRAM BIST test pass
#1 : 1
System SRAM BIST test failed
End of enumeration elements list.
CR0BISTEF : CACHE0 SRAM BIST Fail Flag
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
System CACHE RAM BIST test pass
#1 : 1
System CACHE RAM BIST test failed
End of enumeration elements list.
CR1BISTEF : CACHE1 SRAM BIST Fail Flag
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
System CACHE RAM BIST test pass
#1 : 1
System CACHE RAM BIST test failed
End of enumeration elements list.
USBBEF : USB SRAM BIST Fail Flag
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
USB SRAM BIST test pass
#1 : 1
USB SRAM BIST test failed
End of enumeration elements list.
PDMABISTF : PDMA SRAM BIST Failed Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA SRAM BIST pass
#1 : 1
PDMA SRAM BIST failed
End of enumeration elements list.
SRBEND : SRAM BIST Test Finish
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
System SRAM BIST active
#1 : 1
system SRAM BIST finished
End of enumeration elements list.
CR0BEND : CACHE 0 SRAM BIST Test Finish
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
System CACHE RAM BIST is active
#1 : 1
System CACHE RAM BIST test finished
End of enumeration elements list.
CR1BEND : CACHE 1 SRAM BIST Test Finish
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
System CACHE RAM BIST is active
#1 : 1
System CACHE RAM BIST test finished
End of enumeration elements list.
USBBEND : USB SRAM BIST Test Finish
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
#0 : 0
USB SRAM BIST is active
#1 : 1
USB SRAM BIST test finished
End of enumeration elements list.
PDMAEND : PDMA SRAM BIST Test Finish
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA SRAM BIST is active
#1 : 1
PDMA SRAM BIST test finished
End of enumeration elements list.
HIRC Trim Control Register
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQSEL : Trim Frequency Selection\nThis field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Disable HIRC auto trim function
#01 : 1
Enable HIRC auto trim function and trim HIRC to 48 MHz
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
LOOPSEL : Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim value calculation is based on average difference in 4 clocks of reference clock
#01 : 1
Trim value calculation is based on average difference in 8 clocks of reference clock
#10 : 2
Trim value calculation is based on average difference in 16 clocks of reference clock
#11 : 3
Trim value calculation is based on average difference in 32 clocks of reference clock
End of enumeration elements list.
RETRYCNT : Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim retry count limitation is 64 loops
#01 : 1
Trim retry count limitation is 128 loops
#10 : 2
Trim retry count limitation is 256 loops
#11 : 3
Trim retry count limitation is 512 loops
End of enumeration elements list.
CESTOPEN : Clock Error Stop Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The trim operation keeps going if clock is inaccurate
#1 : 1
The trim operation stops if clock is inaccurate
End of enumeration elements list.
BOUNDEN : Boundary Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Boundary function Disabled
#1 : 1
Boundary function Enabled
End of enumeration elements list.
REFCKSEL : Reference Clock Selection
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
HIRC trim reference clock is from LXT (32.768 kHz)
#1 : 1
HIRC trim reference clock is from internal USB synchronous mode
End of enumeration elements list.
BOUNDARY : Boundary Selection\nFill the boundary range from 0x1 to 0x1F, 0x0 is reserved.\nNote: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enable.
bits : 16 - 20 (5 bit)
access : read-write
HIRC Trim Interrupt Enable Register
address_offset : 0xF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFALIEN : Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_HIRCTRIMCTL[1:0]).\nIf this bit is high and TFAILIF(SYS_HIRCTRIMSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable TFAILIF(SYS_HIRCTRIMSTS[1]) status to trigger an interrupt to CPU
#1 : 1
Enable TFAILIF(SYS_HIRCTRIMSTS[1]) status to trigger an interrupt to CPU
End of enumeration elements list.
CLKEIEN : Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_HIRCTRIMSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable CLKERRIF(SYS_HIRCTRIMSTS[2]) status to trigger an interrupt to CPU
#1 : 1
Enable CLKERRIF(SYS_HIRCTRIMSTS[2]) status to trigger an interrupt to CPU
End of enumeration elements list.
HIRC Trim Interrupt Status Register
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQLOCK : HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt\nWrite 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled. \nNote: Reset by power on reset.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The internal high-speed oscillator frequency doesn't lock at 48 MHz
#1 : 1
The internal high-speed oscillator frequency locked at 48 MHz
End of enumeration elements list.
TFAILIF : Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_HIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_HIRCTRIMIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.\nNote: Reset by power on reset.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trim value update limitation count does not reach
#1 : 1
Trim value update limitation count reached and HIRC frequency still not locked
End of enumeration elements list.
CLKERIF : Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_HIRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_HIRCTRIMCTL[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_HIRCTRIMIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.\nNote: Reset by power on reset.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock frequency is accuracy
#1 : 1
Clock frequency is inaccuracy
End of enumeration elements list.
OVBDIF : Over Boundary Status\nWhen the over boundary function is set, if there occurs the over boundary condition, this flag will be set.\nNote: Write 1 to clear this flag.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Over boundary coundition did not occur
#1 : 1
Over boundary coundition occurred
End of enumeration elements list.
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