\n
address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xE0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
ISP Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPEN : ISP Enable Bit (Write Protect)\nISP function enable bit. Set this bit to enable ISP function.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP function Disabled
#1 : 1
ISP function Enabled
End of enumeration elements list.
BS : Boot Select (Write Protect)\n/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset or system reset is happened\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Booting from APROM
#1 : 1
Booting from LDROM
End of enumeration elements list.
APUEN : APROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
APROM cannot be updated when the chip runs in APROM
#1 : 1
APROM can be updated when the chip runs in APROM
End of enumeration elements list.
CFGUEN : CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
CONFIG cannot be updated
#1 : 1
CONFIG can be updated
End of enumeration elements list.
LDUEN : LDROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
LDROM cannot be updated
#1 : 1
LDROM can be updated
End of enumeration elements list.
ISPFF : ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands\n(8) ISP CMD in XOM region, except mass erase, page erase and chksum command\n(9) The wrong setting of page erase ISP CMD in XOM\n(10) Violate XOM setting one time protection \nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write
ISP Trigger Control Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPGO : ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP operation is finished
#1 : 1
ISP is progressed
End of enumeration elements list.
Flash Access Time Control Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CACHEINV : Flash Cache Invalidation (Write Protect)\nNote1: Write 1 to start cache invalidation. The value will be changed to 0 once the process finishes.\nNote2: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash Cache Invalidation finished (default)
#1 : 1
Flash Cache Invalidation
End of enumeration elements list.
ISP Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPADDR : ISP Address\nThe NuMicro M23 series is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.\nFor Checksum Calculation command, this field is the Flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation.
bits : 0 - 31 (32 bit)
access : read-write
ISP Status Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPBUSY : ISP Busy Flag (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0]).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
ISP operation is finished
#1 : 1
ISP is progressed
End of enumeration elements list.
CBS : Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset or system reset is happened.
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
#00 : 0
LDROM with IAP mode
#01 : 1
LDROM without IAP mode
#10 : 2
APROM with IAP mode
#11 : 3
APROM without IAP mode
End of enumeration elements list.
PGFF : Flash Program with Fast Verification Flag (Read Only)\nThis bit is set if data is mismatched at ISP programming verification. This bit is clear by performing ISP Flash erase or ISP read CID operation
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Flash Program is success
#1 : 1
Flash Program is fail. Program data is different with data in the Flash memory
End of enumeration elements list.
ISPFF : ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands\n(8) ISP CMD in XOM region, except mass erase, page erase and chksum command\n(9) The wrong setting of page erase ISP CMD in XOM\n(10) Violate XOM setting one time protection \nNote: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write
ALLONE : Flash All-one Verification Flag \nThis bit is set by hardware if all of Flash bits are 1, and clear if Flash bits are not all 1 after 'Run Flash All-One Verification' complete; this bit also can be clear by writing 1
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash bits are not all 1 after 'Run Flash All-One Verification' complete
#1 : 1
All of Flash bits are 1 after 'Run Flash All-One Verification' complete
End of enumeration elements list.
VECMAP : Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF}.\nVECMAP [18:12] should be 0.
bits : 9 - 29 (21 bit)
access : read-only
Flash Access Cycle Control Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CYCLE : Flash Access Cycle Control (Write Protect) \n The optimized HCLK working frequency range is 33~50 MHz\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0001 : 1
CPU access with zero wait cycle if cache hit or cache is disabled; Flash access cycle is 1;
#0010 : 2
CPU access with one wait cycles if cache miss; Flash access cycle is 2;
#0011 : 3
CPU access with two wait cycles if cahce miss; Flash access cycle is 3;
End of enumeration elements list.
ISP Data Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPDAT : ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.
bits : 0 - 31 (32 bit)
access : read-write
ISP Data0 Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPDAT0 : ISP Data 0\nThis register is the first 32-bit data for 32-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data.
bits : 0 - 31 (32 bit)
access : read-write
ISP Data1 Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPDAT1 : ISP Data 1\nThis register is the second 32-bit data for multi-word programming.
bits : 0 - 31 (32 bit)
access : read-write
ISP Data2 Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPDAT2 : ISP Data 2\nThis register is the third 32-bit data for multi-word programming.
bits : 0 - 31 (32 bit)
access : read-write
ISP Data3 Register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPDAT3 : ISP Data 3\nThis register is the fourth 32-bit data for multi-word programming.
bits : 0 - 31 (32 bit)
access : read-write
ISP Command Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : ISP Command\nISP command table is shown below:\nThe other commands are invalid.
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x00 : 0
FLASH Read
0x04 : 4
Read Unique ID
0x08 : 8
Read Flash All-One Result
0x0b : 11
Read Company ID
0x0c : 12
Read Device ID
0x0d : 13
Read Checksum
0x21 : 33
FLASH 32-bit Program
0x22 : 34
FLASH Page Erase
0x26 : 38
FLASH Mass Erase
0x27 : 39
FLASH Multi-Word Program
0x28 : 40
Run Flash All-One Verification
0x2d : 45
Run Checksum Calculation
0x2e : 46
Vector Remap
End of enumeration elements list.
ISP Multi-program Status Register
address_offset : 0xC0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MPBUSY : ISP Multi-word Program Busy Flag (Read Only)\nWrite 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0]).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
ISP Multi-Word program operation is finished
#1 : 1
ISP Multi-Word program operation is progressed
End of enumeration elements list.
PPGO : ISP Multi-program Status (Read Only)
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
ISP multi-word program operation is not active
#1 : 1
ISP multi-word program operation is in progress
End of enumeration elements list.
ISPFF : ISP Fail Flag (Read Only)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands.
bits : 2 - 2 (1 bit)
access : read-only
D0 : ISP DATA 0 Flag (Read Only)\nThis bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to Flash complete.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
FMC_MPDAT0 register is empty, or program to Flash complete
#1 : 1
FMC_MPDAT0 register has been written, and not program to Flash complete
End of enumeration elements list.
D1 : ISP DATA 1 Flag (Read Only)\nThis bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to Flash complete.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
FMC_MPDAT1 register is empty, or program to Flash complete
#1 : 1
FMC_MPDAT1 register has been written, and not program to Flash complete
End of enumeration elements list.
D2 : ISP DATA 2 Flag (Read Only)\nThis bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to Flash complete.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
FMC_MPDAT2 register is empty, or program to Flash complete
#1 : 1
FMC_MPDAT2 register has been written, and not program to Flash complete
End of enumeration elements list.
D3 : ISP DATA 3 Flag (Read Only)\nThis bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to Flash complete.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
FMC_MPDAT3 register is empty, or program to Flash complete
#1 : 1
FMC_MPDAT3 register has been written, and not program to Flash complete
End of enumeration elements list.
ISP Multi-program Address Register
address_offset : 0xC4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MPADDR : ISP Multi-word Program Address\nMPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.\nMPADDR will keep the final ISP address when ISP multi-word program is complete.
bits : 0 - 31 (32 bit)
access : read-only
XOM Region 0 Status Register 0
address_offset : 0xD0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BASE : XOM Region 0 Base Address (Page-aligned)\nBASE is the base address of XOM Region 0.
bits : 0 - 23 (24 bit)
access : read-only
XOM Region 0 Status Register 1
address_offset : 0xD4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SIZE : XOM Region 0 Size (Page-aligned)\nSIZE is the page number of XOM Region 0.
bits : 0 - 8 (9 bit)
access : read-only
XOM Status Register
address_offset : 0xE0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
XOMR0ON : XOM Region 0 On\nXOM Region 0 active status.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No active
#1 : 1
XOM region 0 is active
End of enumeration elements list.
XOMPEF : XOM Page Erase Function Fail\nXOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Success
#1 : 1
Fail
End of enumeration elements list.
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