GPIO

MODE0 : Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

MODE1 : Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

MODE2 : Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

MODE3 : Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

MODE4 : Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

MODE5 : Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

MODE6 : Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

MODE7 : Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

MODE8 : Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

MODE9 : Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

MODE10 : Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

MODE11 : Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

MODE12 : Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

MODE13 : Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

MODE14 : Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

MODE15 : Port A-F I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\nNote1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

PA_PIN

PA Pin Value
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PIN0 : Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

The corresponding pin status is low

#1 : 1

The corresponding pin status is high

End of enumeration elements list.

PIN1 : Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

The corresponding pin status is low

#1 : 1

The corresponding pin status is high

End of enumeration elements list.

PIN2 : Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

The corresponding pin status is low

#1 : 1

The corresponding pin status is high

End of enumeration elements list.

PIN3 : Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

The corresponding pin status is low

#1 : 1

The corresponding pin status is high

End of enumeration elements list.

PIN4 : Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

The corresponding pin status is low

#1 : 1

The corresponding pin status is high

End of enumeration elements list.

PIN5 : Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

The corresponding pin status is low

#1 : 1

The corresponding pin status is high

End of enumeration elements list.

PIN6 : Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

The corresponding pin status is low

#1 : 1

The corresponding pin status is high

End of enumeration elements list.

PIN7 : Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

The corresponding pin status is low

#1 : 1

The corresponding pin status is high

End of enumeration elements list.

PIN8 : Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

#0 : 0

The corresponding pin status is low

#1 : 1

The corresponding pin status is high

End of enumeration elements list.

PIN9 : Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

#0 : 0

The corresponding pin status is low

#1 : 1

The corresponding pin status is high

End of enumeration elements list.

PIN10 : Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

#0 : 0

The corresponding pin status is low

#1 : 1

The corresponding pin status is high

End of enumeration elements list.

PIN11 : Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

#0 : 0

The corresponding pin status is low

#1 : 1

The corresponding pin status is high

End of enumeration elements list.

PIN12 : Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

#0 : 0

The corresponding pin status is low

#1 : 1

The corresponding pin status is high

End of enumeration elements list.

PIN13 : Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

#0 : 0

The corresponding pin status is low

#1 : 1

The corresponding pin status is high

End of enumeration elements list.

PIN14 : Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

#0 : 0

The corresponding pin status is low

#1 : 1

The corresponding pin status is high

End of enumeration elements list.

PIN15 : Port A-F Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

#0 : 0

The corresponding pin status is low

#1 : 1

The corresponding pin status is high

End of enumeration elements list.

PE_MODE

PE I/O Mode Control
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE_DINOFF

PE Digital Input Path Disable Control
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE_DOUT

PE Data Output Value
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE_DATMSK

PE Data Output Write Mask
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE_PIN

PE Pin Value
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE_DBEN

PE De-bounce Enable Control Register
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE_INTTYPE

PE Interrupt Trigger Type Control
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE_INTEN

PE Interrupt Enable Control Register
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE_INTSRC

PE Interrupt Source Flag
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE_SMTEN

PE Input Schmitt Trigger Enable Register
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE_SLEWCTL

PE High Slew Rate Control Register
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE_PUSEL

PE Pull-up and Pull-down Selection Register
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA_DBEN

PA De-bounce Enable Control Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBEN0 : Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n de-bounce function Disabled

#1 : 1

Px.n de-bounce function Enabled

End of enumeration elements list.

DBEN1 : Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n de-bounce function Disabled

#1 : 1

Px.n de-bounce function Enabled

End of enumeration elements list.

DBEN2 : Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n de-bounce function Disabled

#1 : 1

Px.n de-bounce function Enabled

End of enumeration elements list.

DBEN3 : Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n de-bounce function Disabled

#1 : 1

Px.n de-bounce function Enabled

End of enumeration elements list.

DBEN4 : Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n de-bounce function Disabled

#1 : 1

Px.n de-bounce function Enabled

End of enumeration elements list.

DBEN5 : Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n de-bounce function Disabled

#1 : 1

Px.n de-bounce function Enabled

End of enumeration elements list.

DBEN6 : Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n de-bounce function Disabled

#1 : 1

Px.n de-bounce function Enabled

End of enumeration elements list.

DBEN7 : Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n de-bounce function Disabled

#1 : 1

Px.n de-bounce function Enabled

End of enumeration elements list.

DBEN8 : Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n de-bounce function Disabled

#1 : 1

Px.n de-bounce function Enabled

End of enumeration elements list.

DBEN9 : Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n de-bounce function Disabled

#1 : 1

Px.n de-bounce function Enabled

End of enumeration elements list.

DBEN10 : Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n de-bounce function Disabled

#1 : 1

Px.n de-bounce function Enabled

End of enumeration elements list.

DBEN11 : Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n de-bounce function Disabled

#1 : 1

Px.n de-bounce function Enabled

End of enumeration elements list.

DBEN12 : Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n de-bounce function Disabled

#1 : 1

Px.n de-bounce function Enabled

End of enumeration elements list.

DBEN13 : Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n de-bounce function Disabled

#1 : 1

Px.n de-bounce function Enabled

End of enumeration elements list.

DBEN14 : Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n de-bounce function Disabled

#1 : 1

Px.n de-bounce function Enabled

End of enumeration elements list.

DBEN15 : Port A-F Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n de-bounce function Disabled

#1 : 1

Px.n de-bounce function Enabled

End of enumeration elements list.

PF_MODE

PF I/O Mode Control
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF_DINOFF

PF Digital Input Path Disable Control
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF_DOUT

PF Data Output Value
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF_DATMSK

PF Data Output Write Mask
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF_PIN

PF Pin Value
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF_DBEN

PF De-bounce Enable Control Register
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF_INTTYPE

PF Interrupt Trigger Type Control
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF_INTEN

PF Interrupt Enable Control Register
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF_INTSRC

PF Interrupt Source Flag
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF_SMTEN

PF Input Schmitt Trigger Enable Register
address_offset : 0x164 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF_SLEWCTL

PF High Slew Rate Control Register
address_offset : 0x168 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF_PUSEL

PF Pull-up and Pull-down Selection Register
address_offset : 0x170 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA_INTTYPE

PA Interrupt Trigger Type Control
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TYPE0 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

TYPE1 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

TYPE2 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

TYPE3 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

TYPE4 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

TYPE5 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

TYPE6 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

TYPE7 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

TYPE8 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

TYPE9 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

TYPE10 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

TYPE11 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

TYPE12 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

TYPE13 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

TYPE14 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

TYPE15 : Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). If both levels to trigger interrupt are set, the setting has no effect and no interrupt will occur.\nThe de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ineffective.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

PA_INTEN

PA Interrupt Enable Control Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLIEN0 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level low or high to low interrupt Disabled

#1 : 1

Px.n level low or high to low interrupt Enabled

End of enumeration elements list.

FLIEN1 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level low or high to low interrupt Disabled

#1 : 1

Px.n level low or high to low interrupt Enabled

End of enumeration elements list.

FLIEN2 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level low or high to low interrupt Disabled

#1 : 1

Px.n level low or high to low interrupt Enabled

End of enumeration elements list.

FLIEN3 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level low or high to low interrupt Disabled

#1 : 1

Px.n level low or high to low interrupt Enabled

End of enumeration elements list.

FLIEN4 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level low or high to low interrupt Disabled

#1 : 1

Px.n level low or high to low interrupt Enabled

End of enumeration elements list.

FLIEN5 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level low or high to low interrupt Disabled

#1 : 1

Px.n level low or high to low interrupt Enabled

End of enumeration elements list.

FLIEN6 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level low or high to low interrupt Disabled

#1 : 1

Px.n level low or high to low interrupt Enabled

End of enumeration elements list.

FLIEN7 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level low or high to low interrupt Disabled

#1 : 1

Px.n level low or high to low interrupt Enabled

End of enumeration elements list.

FLIEN8 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level low or high to low interrupt Disabled

#1 : 1

Px.n level low or high to low interrupt Enabled

End of enumeration elements list.

FLIEN9 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level low or high to low interrupt Disabled

#1 : 1

Px.n level low or high to low interrupt Enabled

End of enumeration elements list.

FLIEN10 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level low or high to low interrupt Disabled

#1 : 1

Px.n level low or high to low interrupt Enabled

End of enumeration elements list.

FLIEN11 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level low or high to low interrupt Disabled

#1 : 1

Px.n level low or high to low interrupt Enabled

End of enumeration elements list.

FLIEN12 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level low or high to low interrupt Disabled

#1 : 1

Px.n level low or high to low interrupt Enabled

End of enumeration elements list.

FLIEN13 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level low or high to low interrupt Disabled

#1 : 1

Px.n level low or high to low interrupt Enabled

End of enumeration elements list.

FLIEN14 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level low or high to low interrupt Disabled

#1 : 1

Px.n level low or high to low interrupt Enabled

End of enumeration elements list.

FLIEN15 : Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the FLIEN (Px_INTEN[n]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level low or high to low interrupt Disabled

#1 : 1

Px.n level low or high to low interrupt Enabled

End of enumeration elements list.

RHIEN0 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level high or low to high interrupt Disabled

#1 : 1

Px.n level high or low to high interrupt Enabled

End of enumeration elements list.

RHIEN1 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level high or low to high interrupt Disabled

#1 : 1

Px.n level high or low to high interrupt Enabled

End of enumeration elements list.

RHIEN2 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level high or low to high interrupt Disabled

#1 : 1

Px.n level high or low to high interrupt Enabled

End of enumeration elements list.

RHIEN3 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level high or low to high interrupt Disabled

#1 : 1

Px.n level high or low to high interrupt Enabled

End of enumeration elements list.

RHIEN4 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level high or low to high interrupt Disabled

#1 : 1

Px.n level high or low to high interrupt Enabled

End of enumeration elements list.

RHIEN5 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level high or low to high interrupt Disabled

#1 : 1

Px.n level high or low to high interrupt Enabled

End of enumeration elements list.

RHIEN6 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level high or low to high interrupt Disabled

#1 : 1

Px.n level high or low to high interrupt Enabled

End of enumeration elements list.

RHIEN7 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level high or low to high interrupt Disabled

#1 : 1

Px.n level high or low to high interrupt Enabled

End of enumeration elements list.

RHIEN8 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level high or low to high interrupt Disabled

#1 : 1

Px.n level high or low to high interrupt Enabled

End of enumeration elements list.

RHIEN9 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level high or low to high interrupt Disabled

#1 : 1

Px.n level high or low to high interrupt Enabled

End of enumeration elements list.

RHIEN10 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level high or low to high interrupt Disabled

#1 : 1

Px.n level high or low to high interrupt Enabled

End of enumeration elements list.

RHIEN11 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level high or low to high interrupt Disabled

#1 : 1

Px.n level high or low to high interrupt Enabled

End of enumeration elements list.

RHIEN12 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level high or low to high interrupt Disabled

#1 : 1

Px.n level high or low to high interrupt Enabled

End of enumeration elements list.

RHIEN13 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level high or low to high interrupt Disabled

#1 : 1

Px.n level high or low to high interrupt Enabled

End of enumeration elements list.

RHIEN14 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level high or low to high interrupt Disabled

#1 : 1

Px.n level high or low to high interrupt Enabled

End of enumeration elements list.

RHIEN15 : Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. \nWhen setting the RHIEN (Px_INTEN[n+16]) bit to 1 :\nIf the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n level high or low to high interrupt Disabled

#1 : 1

Px.n level high or low to high interrupt Enabled

End of enumeration elements list.

PA_INTSRC

PA Interrupt Source Flag
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSRC0 : Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No action.\nNo interrupt at Px.n

#1 : 1

Clear the corresponding pending interrupt.\nPx.n generates an interrupt

End of enumeration elements list.

INTSRC1 : Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No action.\nNo interrupt at Px.n

#1 : 1

Clear the corresponding pending interrupt.\nPx.n generates an interrupt

End of enumeration elements list.

INTSRC2 : Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No action.\nNo interrupt at Px.n

#1 : 1

Clear the corresponding pending interrupt.\nPx.n generates an interrupt

End of enumeration elements list.

INTSRC3 : Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No action.\nNo interrupt at Px.n

#1 : 1

Clear the corresponding pending interrupt.\nPx.n generates an interrupt

End of enumeration elements list.

INTSRC4 : Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No action.\nNo interrupt at Px.n

#1 : 1

Clear the corresponding pending interrupt.\nPx.n generates an interrupt

End of enumeration elements list.

INTSRC5 : Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No action.\nNo interrupt at Px.n

#1 : 1

Clear the corresponding pending interrupt.\nPx.n generates an interrupt

End of enumeration elements list.

INTSRC6 : Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

No action.\nNo interrupt at Px.n

#1 : 1

Clear the corresponding pending interrupt.\nPx.n generates an interrupt

End of enumeration elements list.

INTSRC7 : Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

No action.\nNo interrupt at Px.n

#1 : 1

Clear the corresponding pending interrupt.\nPx.n generates an interrupt

End of enumeration elements list.

INTSRC8 : Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

No action.\nNo interrupt at Px.n

#1 : 1

Clear the corresponding pending interrupt.\nPx.n generates an interrupt

End of enumeration elements list.

INTSRC9 : Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

No action.\nNo interrupt at Px.n

#1 : 1

Clear the corresponding pending interrupt.\nPx.n generates an interrupt

End of enumeration elements list.

INTSRC10 : Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

No action.\nNo interrupt at Px.n

#1 : 1

Clear the corresponding pending interrupt.\nPx.n generates an interrupt

End of enumeration elements list.

INTSRC11 : Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

No action.\nNo interrupt at Px.n

#1 : 1

Clear the corresponding pending interrupt.\nPx.n generates an interrupt

End of enumeration elements list.

INTSRC12 : Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

No action.\nNo interrupt at Px.n

#1 : 1

Clear the corresponding pending interrupt.\nPx.n generates an interrupt

End of enumeration elements list.

INTSRC13 : Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

No action.\nNo interrupt at Px.n

#1 : 1

Clear the corresponding pending interrupt.\nPx.n generates an interrupt

End of enumeration elements list.

INTSRC14 : Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

No action.\nNo interrupt at Px.n

#1 : 1

Clear the corresponding pending interrupt.\nPx.n generates an interrupt

End of enumeration elements list.

INTSRC15 : Port A-F Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

No action.\nNo interrupt at Px.n

#1 : 1

Clear the corresponding pending interrupt.\nPx.n generates an interrupt

End of enumeration elements list.

PA_SMTEN

PA Input Schmitt Trigger Enable Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMTEN0 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n input schmitt trigger function Disabled

#1 : 1

Px.n input schmitt trigger function Enabled

End of enumeration elements list.

SMTEN1 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n input schmitt trigger function Disabled

#1 : 1

Px.n input schmitt trigger function Enabled

End of enumeration elements list.

SMTEN2 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n input schmitt trigger function Disabled

#1 : 1

Px.n input schmitt trigger function Enabled

End of enumeration elements list.

SMTEN3 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n input schmitt trigger function Disabled

#1 : 1

Px.n input schmitt trigger function Enabled

End of enumeration elements list.

SMTEN4 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n input schmitt trigger function Disabled

#1 : 1

Px.n input schmitt trigger function Enabled

End of enumeration elements list.

SMTEN5 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n input schmitt trigger function Disabled

#1 : 1

Px.n input schmitt trigger function Enabled

End of enumeration elements list.

SMTEN6 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n input schmitt trigger function Disabled

#1 : 1

Px.n input schmitt trigger function Enabled

End of enumeration elements list.

SMTEN7 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n input schmitt trigger function Disabled

#1 : 1

Px.n input schmitt trigger function Enabled

End of enumeration elements list.

SMTEN8 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n input schmitt trigger function Disabled

#1 : 1

Px.n input schmitt trigger function Enabled

End of enumeration elements list.

SMTEN9 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n input schmitt trigger function Disabled

#1 : 1

Px.n input schmitt trigger function Enabled

End of enumeration elements list.

SMTEN10 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n input schmitt trigger function Disabled

#1 : 1

Px.n input schmitt trigger function Enabled

End of enumeration elements list.

SMTEN11 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n input schmitt trigger function Disabled

#1 : 1

Px.n input schmitt trigger function Enabled

End of enumeration elements list.

SMTEN12 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n input schmitt trigger function Disabled

#1 : 1

Px.n input schmitt trigger function Enabled

End of enumeration elements list.

SMTEN13 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n input schmitt trigger function Disabled

#1 : 1

Px.n input schmitt trigger function Enabled

End of enumeration elements list.

SMTEN14 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n input schmitt trigger function Disabled

#1 : 1

Px.n input schmitt trigger function Enabled

End of enumeration elements list.

SMTEN15 : Port A-F Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n input schmitt trigger function Disabled

#1 : 1

Px.n input schmitt trigger function Enabled

End of enumeration elements list.

PA_SLEWCTL

PA High Slew Rate Control Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSREN0 : Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n output with normal slew rate mode

#01 : 1

Px.n output with high slew rate mode

#10 : 2

Reserved.

#11 : 3

Reserved.

End of enumeration elements list.

HSREN1 : Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n output with normal slew rate mode

#01 : 1

Px.n output with high slew rate mode

#10 : 2

Reserved.

#11 : 3

Reserved.

End of enumeration elements list.

HSREN2 : Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n output with normal slew rate mode

#01 : 1

Px.n output with high slew rate mode

#10 : 2

Reserved.

#11 : 3

Reserved.

End of enumeration elements list.

HSREN3 : Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n output with normal slew rate mode

#01 : 1

Px.n output with high slew rate mode

#10 : 2

Reserved.

#11 : 3

Reserved.

End of enumeration elements list.

HSREN4 : Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n output with normal slew rate mode

#01 : 1

Px.n output with high slew rate mode

#10 : 2

Reserved.

#11 : 3

Reserved.

End of enumeration elements list.

HSREN5 : Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n output with normal slew rate mode

#01 : 1

Px.n output with high slew rate mode

#10 : 2

Reserved.

#11 : 3

Reserved.

End of enumeration elements list.

HSREN6 : Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n output with normal slew rate mode

#01 : 1

Px.n output with high slew rate mode

#10 : 2

Reserved.

#11 : 3

Reserved.

End of enumeration elements list.

HSREN7 : Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n output with normal slew rate mode

#01 : 1

Px.n output with high slew rate mode

#10 : 2

Reserved.

#11 : 3

Reserved.

End of enumeration elements list.

HSREN8 : Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n output with normal slew rate mode

#01 : 1

Px.n output with high slew rate mode

#10 : 2

Reserved.

#11 : 3

Reserved.

End of enumeration elements list.

HSREN9 : Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n output with normal slew rate mode

#01 : 1

Px.n output with high slew rate mode

#10 : 2

Reserved.

#11 : 3

Reserved.

End of enumeration elements list.

HSREN10 : Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n output with normal slew rate mode

#01 : 1

Px.n output with high slew rate mode

#10 : 2

Reserved.

#11 : 3

Reserved.

End of enumeration elements list.

HSREN11 : Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n output with normal slew rate mode

#01 : 1

Px.n output with high slew rate mode

#10 : 2

Reserved.

#11 : 3

Reserved.

End of enumeration elements list.

HSREN12 : Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n output with normal slew rate mode

#01 : 1

Px.n output with high slew rate mode

#10 : 2

Reserved.

#11 : 3

Reserved.

End of enumeration elements list.

HSREN13 : Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n output with normal slew rate mode

#01 : 1

Px.n output with high slew rate mode

#10 : 2

Reserved.

#11 : 3

Reserved.

End of enumeration elements list.

HSREN14 : Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n output with normal slew rate mode

#01 : 1

Px.n output with high slew rate mode

#10 : 2

Reserved.

#11 : 3

Reserved.

End of enumeration elements list.

HSREN15 : Port A-F Pin[n] High Slew Rate Control\n\nNote1: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.\nNote2: Please refer to the M251 Datasheet for detailed pin operation voltage information about VDD, VDDIO and VBAT electrical characteristics.
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n output with normal slew rate mode

#01 : 1

Px.n output with high slew rate mode

#10 : 2

Reserved.

#11 : 3

Reserved.

End of enumeration elements list.

PA_PUSEL

PA Pull-up and Pull-down Selection Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PUSEL0 : Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n pull-up and pull-down disable

#01 : 1

Px.n pull-up enable

#10 : 2

Px.n pull-down enable

#11 : 3

Px.n pull-up and pull- down disable

End of enumeration elements list.

PUSEL1 : Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n pull-up and pull-down disable

#01 : 1

Px.n pull-up enable

#10 : 2

Px.n pull-down enable

#11 : 3

Px.n pull-up and pull- down disable

End of enumeration elements list.

PUSEL2 : Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n pull-up and pull-down disable

#01 : 1

Px.n pull-up enable

#10 : 2

Px.n pull-down enable

#11 : 3

Px.n pull-up and pull- down disable

End of enumeration elements list.

PUSEL3 : Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n pull-up and pull-down disable

#01 : 1

Px.n pull-up enable

#10 : 2

Px.n pull-down enable

#11 : 3

Px.n pull-up and pull- down disable

End of enumeration elements list.

PUSEL4 : Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n pull-up and pull-down disable

#01 : 1

Px.n pull-up enable

#10 : 2

Px.n pull-down enable

#11 : 3

Px.n pull-up and pull- down disable

End of enumeration elements list.

PUSEL5 : Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n pull-up and pull-down disable

#01 : 1

Px.n pull-up enable

#10 : 2

Px.n pull-down enable

#11 : 3

Px.n pull-up and pull- down disable

End of enumeration elements list.

PUSEL6 : Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n pull-up and pull-down disable

#01 : 1

Px.n pull-up enable

#10 : 2

Px.n pull-down enable

#11 : 3

Px.n pull-up and pull- down disable

End of enumeration elements list.

PUSEL7 : Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n pull-up and pull-down disable

#01 : 1

Px.n pull-up enable

#10 : 2

Px.n pull-down enable

#11 : 3

Px.n pull-up and pull- down disable

End of enumeration elements list.

PUSEL8 : Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n pull-up and pull-down disable

#01 : 1

Px.n pull-up enable

#10 : 2

Px.n pull-down enable

#11 : 3

Px.n pull-up and pull- down disable

End of enumeration elements list.

PUSEL9 : Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n pull-up and pull-down disable

#01 : 1

Px.n pull-up enable

#10 : 2

Px.n pull-down enable

#11 : 3

Px.n pull-up and pull- down disable

End of enumeration elements list.

PUSEL10 : Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n pull-up and pull-down disable

#01 : 1

Px.n pull-up enable

#10 : 2

Px.n pull-down enable

#11 : 3

Px.n pull-up and pull- down disable

End of enumeration elements list.

PUSEL11 : Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n pull-up and pull-down disable

#01 : 1

Px.n pull-up enable

#10 : 2

Px.n pull-down enable

#11 : 3

Px.n pull-up and pull- down disable

End of enumeration elements list.

PUSEL12 : Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n pull-up and pull-down disable

#01 : 1

Px.n pull-up enable

#10 : 2

Px.n pull-down enable

#11 : 3

Px.n pull-up and pull- down disable

End of enumeration elements list.

PUSEL13 : Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n pull-up and pull-down disable

#01 : 1

Px.n pull-up enable

#10 : 2

Px.n pull-down enable

#11 : 3

Px.n pull-up and pull- down disable

End of enumeration elements list.

PUSEL14 : Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n pull-up and pull-down disable

#01 : 1

Px.n pull-up enable

#10 : 2

Px.n pull-down enable

#11 : 3

Px.n pull-up and pull- down disable

End of enumeration elements list.

PUSEL15 : Port A-F Pin[n] Pull-up and Pull-down Enable Register\nDetermine each I/O Pull-up/pull-down of Px.n pins.\nNote1: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up control register only valid when MODEn set as tri-state and open-drain mode.\nThe independent pull-down control register only valid when MODEn set as tri-state mode.\nWhen both pull-up pull-down is set as 1 at 'tri-state' mode, keep I/O in tri-state mode.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n pull-up and pull-down disable

#01 : 1

Px.n pull-up enable

#10 : 2

Px.n pull-down enable

#11 : 3

Px.n pull-up and pull- down disable

End of enumeration elements list.

PA_DINOFF

PA Digital Input Path Disable Control
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DINOFF0 : Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n digital input path Enabled

#1 : 1

Px.n digital input path Disabled (digital input tied to low)

End of enumeration elements list.

DINOFF1 : Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n digital input path Enabled

#1 : 1

Px.n digital input path Disabled (digital input tied to low)

End of enumeration elements list.

DINOFF2 : Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n digital input path Enabled

#1 : 1

Px.n digital input path Disabled (digital input tied to low)

End of enumeration elements list.

DINOFF3 : Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n digital input path Enabled

#1 : 1

Px.n digital input path Disabled (digital input tied to low)

End of enumeration elements list.

DINOFF4 : Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n digital input path Enabled

#1 : 1

Px.n digital input path Disabled (digital input tied to low)

End of enumeration elements list.

DINOFF5 : Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n digital input path Enabled

#1 : 1

Px.n digital input path Disabled (digital input tied to low)

End of enumeration elements list.

DINOFF6 : Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n digital input path Enabled

#1 : 1

Px.n digital input path Disabled (digital input tied to low)

End of enumeration elements list.

DINOFF7 : Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n digital input path Enabled

#1 : 1

Px.n digital input path Disabled (digital input tied to low)

End of enumeration elements list.

DINOFF8 : Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n digital input path Enabled

#1 : 1

Px.n digital input path Disabled (digital input tied to low)

End of enumeration elements list.

DINOFF9 : Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n digital input path Enabled

#1 : 1

Px.n digital input path Disabled (digital input tied to low)

End of enumeration elements list.

DINOFF10 : Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n digital input path Enabled

#1 : 1

Px.n digital input path Disabled (digital input tied to low)

End of enumeration elements list.

DINOFF11 : Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n digital input path Enabled

#1 : 1

Px.n digital input path Disabled (digital input tied to low)

End of enumeration elements list.

DINOFF12 : Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n digital input path Enabled

#1 : 1

Px.n digital input path Disabled (digital input tied to low)

End of enumeration elements list.

DINOFF13 : Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n digital input path Enabled

#1 : 1

Px.n digital input path Disabled (digital input tied to low)

End of enumeration elements list.

DINOFF14 : Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n digital input path Enabled

#1 : 1

Px.n digital input path Disabled (digital input tied to low)

End of enumeration elements list.

DINOFF15 : Port A-F Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n digital input path Enabled

#1 : 1

Px.n digital input path Disabled (digital input tied to low)

End of enumeration elements list.

PB_MODE

PB I/O Mode Control
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_DINOFF

PB Digital Input Path Disable Control
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_DBCTL (DBCTL)

Interrupt De-bounce Control Register
address_offset : 0x440 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBCLKSEL : De-bounce Sampling Cycle Selection
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0

Sample interrupt input once per 1 clocks

#0001 : 1

Sample interrupt input once per 2 clocks

#0010 : 2

Sample interrupt input once per 4 clocks

#0011 : 3

Sample interrupt input once per 8 clocks

#0100 : 4

Sample interrupt input once per 16 clocks

#0101 : 5

Sample interrupt input once per 32 clocks

#0110 : 6

Sample interrupt input once per 64 clocks

#0111 : 7

Sample interrupt input once per 128 clocks

#1000 : 8

Sample interrupt input once per 256 clocks

#1001 : 9

Sample interrupt input once per 2*256 clocks

#1010 : 10

Sample interrupt input once per 4*256 clocks

#1011 : 11

Sample interrupt input once per 8*256 clocks

#1100 : 12

Sample interrupt input once per 16*256 clocks

#1101 : 13

Sample interrupt input once per 32*256 clocks

#1110 : 14

Sample interrupt input once per 64*256 clocks

#1111 : 15

Sample interrupt input once per 128*256 clocks

End of enumeration elements list.

DBCLKSRC : De-bounce Counter Clock Source Selection
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

De-bounce counter clock source is the HCLK

#1 : 1

De-bounce counter clock source is the 38.4 kHz internal low speed RC oscillator (LIRC)

End of enumeration elements list.

ICLKONx : Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern. Each bit control each GPIO group.
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0 : 0

Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1

1 : 1

All I/O pins edge detection circuit is always active after reset

End of enumeration elements list.

PB_DOUT

PB Data Output Value
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_DATMSK

PB Data Output Write Mask
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_PIN

PB Pin Value
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_DBEN

PB De-bounce Enable Control Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_INTTYPE

PB Interrupt Trigger Type Control
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_INTEN

PB Interrupt Enable Control Register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_INTSRC

PB Interrupt Source Flag
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_SMTEN

PB Input Schmitt Trigger Enable Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_SLEWCTL

PB High Slew Rate Control Register
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_PUSEL

PB Pull-up and Pull-down Selection Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA_DOUT

PA Data Output Value
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOUT0 : Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT1 : Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT2 : Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT3 : Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT4 : Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT5 : Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT6 : Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT7 : Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT8 : Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT9 : Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT10 : Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT11 : Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT12 : Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT13 : Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT14 : Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

DOUT15 : Port A-F Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\nNote: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

#1 : 1

Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.

PC_MODE

PC I/O Mode Control
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA0_PDIO

GPIO PA.n Pin Data Input/Output Register
address_offset : 0x800 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDIO : GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example, writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]), reading PA0_PDIO will return the value of PIN (PA_PIN[0]).\nNote1: The writing operation will not be affected by register DATMSK (Px_DATMSK[n]).\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding GPIO pin set to low

#1 : 1

Corresponding GPIO pin set to high

End of enumeration elements list.

PA1_PDIO

GPIO PA.n Pin Data Input/Output Register
address_offset : 0x804 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA2_PDIO

GPIO PA.n Pin Data Input/Output Register
address_offset : 0x808 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA3_PDIO

GPIO PA.n Pin Data Input/Output Register
address_offset : 0x80C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA4_PDIO

GPIO PA.n Pin Data Input/Output Register
address_offset : 0x810 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA5_PDIO

GPIO PA.n Pin Data Input/Output Register
address_offset : 0x814 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA6_PDIO

GPIO PA.n Pin Data Input/Output Register
address_offset : 0x818 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA7_PDIO

GPIO PA.n Pin Data Input/Output Register
address_offset : 0x81C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA8_PDIO

GPIO PA.n Pin Data Input/Output Register
address_offset : 0x820 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA9_PDIO

GPIO PA.n Pin Data Input/Output Register
address_offset : 0x824 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA10_PDIO

GPIO PA.n Pin Data Input/Output Register
address_offset : 0x828 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA11_PDIO

GPIO PA.n Pin Data Input/Output Register
address_offset : 0x82C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA12_PDIO

GPIO PA.n Pin Data Input/Output Register
address_offset : 0x830 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA13_PDIO

GPIO PA.n Pin Data Input/Output Register
address_offset : 0x834 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA14_PDIO

GPIO PA.n Pin Data Input/Output Register
address_offset : 0x838 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA15_PDIO

GPIO PA.n Pin Data Input/Output Register
address_offset : 0x83C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC_DINOFF

PC Digital Input Path Disable Control
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB0_PDIO

GPIO PB.n Pin Data Input/Output Register
address_offset : 0x840 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB1_PDIO

GPIO PB.n Pin Data Input/Output Register
address_offset : 0x844 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB2_PDIO

GPIO PB.n Pin Data Input/Output Register
address_offset : 0x848 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB3_PDIO

GPIO PB.n Pin Data Input/Output Register
address_offset : 0x84C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB4_PDIO

GPIO PB.n Pin Data Input/Output Register
address_offset : 0x850 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB5_PDIO

GPIO PB.n Pin Data Input/Output Register
address_offset : 0x854 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB6_PDIO

GPIO PB.n Pin Data Input/Output Register
address_offset : 0x858 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB7_PDIO

GPIO PB.n Pin Data Input/Output Register
address_offset : 0x85C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB8_PDIO

GPIO PB.n Pin Data Input/Output Register
address_offset : 0x860 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB9_PDIO

GPIO PB.n Pin Data Input/Output Register
address_offset : 0x864 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB10_PDIO

GPIO PB.n Pin Data Input/Output Register
address_offset : 0x868 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB11_PDIO

GPIO PB.n Pin Data Input/Output Register
address_offset : 0x86C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB12_PDIO

GPIO PB.n Pin Data Input/Output Register
address_offset : 0x870 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB13_PDIO

GPIO PB.n Pin Data Input/Output Register
address_offset : 0x874 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB14_PDIO

GPIO PB.n Pin Data Input/Output Register
address_offset : 0x878 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB15_PDIO

GPIO PB.n Pin Data Input/Output Register
address_offset : 0x87C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC_DOUT

PC Data Output Value
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC0_PDIO

GPIO PC.n Pin Data Input/Output Register
address_offset : 0x880 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC1_PDIO

GPIO PC.n Pin Data Input/Output Register
address_offset : 0x884 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC2_PDIO

GPIO PC.n Pin Data Input/Output Register
address_offset : 0x888 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC3_PDIO

GPIO PC.n Pin Data Input/Output Register
address_offset : 0x88C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC4_PDIO

GPIO PC.n Pin Data Input/Output Register
address_offset : 0x890 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC5_PDIO

GPIO PC.n Pin Data Input/Output Register
address_offset : 0x894 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC6_PDIO

GPIO PC.n Pin Data Input/Output Register
address_offset : 0x898 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC7_PDIO

GPIO PC.n Pin Data Input/Output Register
address_offset : 0x89C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC8_PDIO

GPIO PC.n Pin Data Input/Output Register
address_offset : 0x8A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC9_PDIO

GPIO PC.n Pin Data Input/Output Register
address_offset : 0x8A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC10_PDIO

GPIO PC.n Pin Data Input/Output Register
address_offset : 0x8A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC11_PDIO

GPIO PC.n Pin Data Input/Output Register
address_offset : 0x8AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC12_PDIO

GPIO PC.n Pin Data Input/Output Register
address_offset : 0x8B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC14_PDIO

GPIO PC.n Pin Data Input/Output Register
address_offset : 0x8B8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC15_PDIO

GPIO PC.n Pin Data Input/Output Register
address_offset : 0x8BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC_DATMSK

PC Data Output Write Mask
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD0_PDIO

GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD1_PDIO

GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD2_PDIO

GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD3_PDIO

GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD4_PDIO

GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD5_PDIO

GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD6_PDIO

GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD7_PDIO

GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD8_PDIO

GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD9_PDIO

GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD10_PDIO

GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD11_PDIO

GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD12_PDIO

GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD13_PDIO

GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD15_PDIO

GPIO PD.n Pin Data Input/Output Register
address_offset : 0x8FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC_PIN

PC Pin Value
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE0_PDIO

GPIO PE.n Pin Data Input/Output Register
address_offset : 0x900 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE1_PDIO

GPIO PE.n Pin Data Input/Output Register
address_offset : 0x904 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE2_PDIO

GPIO PE.n Pin Data Input/Output Register
address_offset : 0x908 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE3_PDIO

GPIO PE.n Pin Data Input/Output Register
address_offset : 0x90C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE4_PDIO

GPIO PE.n Pin Data Input/Output Register
address_offset : 0x910 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE5_PDIO

GPIO PE.n Pin Data Input/Output Register
address_offset : 0x914 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE6_PDIO

GPIO PE.n Pin Data Input/Output Register
address_offset : 0x918 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE7_PDIO

GPIO PE.n Pin Data Input/Output Register
address_offset : 0x91C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE8_PDIO

GPIO PE.n Pin Data Input/Output Register
address_offset : 0x920 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE9_PDIO

GPIO PE.n Pin Data Input/Output Register
address_offset : 0x924 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE10_PDIO

GPIO PE.n Pin Data Input/Output Register
address_offset : 0x928 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE11_PDIO

GPIO PE.n Pin Data Input/Output Register
address_offset : 0x92C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE12_PDIO

GPIO PE.n Pin Data Input/Output Register
address_offset : 0x930 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE13_PDIO

GPIO PE.n Pin Data Input/Output Register
address_offset : 0x934 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE14_PDIO

GPIO PE.n Pin Data Input/Output Register
address_offset : 0x938 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE15_PDIO

GPIO PE.n Pin Data Input/Output Register
address_offset : 0x93C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC_DBEN

PC De-bounce Enable Control Register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF0_PDIO

GPIO PF.n Pin Data Input/Output Register
address_offset : 0x940 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF1_PDIO

GPIO PF.n Pin Data Input/Output Register
address_offset : 0x944 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF2_PDIO

GPIO PF.n Pin Data Input/Output Register
address_offset : 0x948 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF3_PDIO

GPIO PF.n Pin Data Input/Output Register
address_offset : 0x94C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF4_PDIO

GPIO PF.n Pin Data Input/Output Register
address_offset : 0x950 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF5_PDIO

GPIO PF.n Pin Data Input/Output Register
address_offset : 0x954 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF6_PDIO

GPIO PF.n Pin Data Input/Output Register
address_offset : 0x958 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF7_PDIO

GPIO PF.n Pin Data Input/Output Register
address_offset : 0x95C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC_INTTYPE

PC Interrupt Trigger Type Control
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC_INTEN

PC Interrupt Enable Control Register
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC_INTSRC

PC Interrupt Source Flag
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC_SMTEN

PC Input Schmitt Trigger Enable Register
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC_SLEWCTL

PC High Slew Rate Control Register
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC_PUSEL

PC Pull-up and Pull-down Selection Register
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA_DATMSK

PA Data Output Write Mask
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATMSK0 : Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding DOUT (Px_DOUT[n]) bit can be updated

#1 : 1

Corresponding DOUT (Px_DOUT[n]) bit protected

End of enumeration elements list.

DATMSK1 : Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding DOUT (Px_DOUT[n]) bit can be updated

#1 : 1

Corresponding DOUT (Px_DOUT[n]) bit protected

End of enumeration elements list.

DATMSK2 : Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding DOUT (Px_DOUT[n]) bit can be updated

#1 : 1

Corresponding DOUT (Px_DOUT[n]) bit protected

End of enumeration elements list.

DATMSK3 : Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding DOUT (Px_DOUT[n]) bit can be updated

#1 : 1

Corresponding DOUT (Px_DOUT[n]) bit protected

End of enumeration elements list.

DATMSK4 : Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding DOUT (Px_DOUT[n]) bit can be updated

#1 : 1

Corresponding DOUT (Px_DOUT[n]) bit protected

End of enumeration elements list.

DATMSK5 : Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding DOUT (Px_DOUT[n]) bit can be updated

#1 : 1

Corresponding DOUT (Px_DOUT[n]) bit protected

End of enumeration elements list.

DATMSK6 : Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding DOUT (Px_DOUT[n]) bit can be updated

#1 : 1

Corresponding DOUT (Px_DOUT[n]) bit protected

End of enumeration elements list.

DATMSK7 : Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding DOUT (Px_DOUT[n]) bit can be updated

#1 : 1

Corresponding DOUT (Px_DOUT[n]) bit protected

End of enumeration elements list.

DATMSK8 : Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding DOUT (Px_DOUT[n]) bit can be updated

#1 : 1

Corresponding DOUT (Px_DOUT[n]) bit protected

End of enumeration elements list.

DATMSK9 : Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding DOUT (Px_DOUT[n]) bit can be updated

#1 : 1

Corresponding DOUT (Px_DOUT[n]) bit protected

End of enumeration elements list.

DATMSK10 : Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding DOUT (Px_DOUT[n]) bit can be updated

#1 : 1

Corresponding DOUT (Px_DOUT[n]) bit protected

End of enumeration elements list.

DATMSK11 : Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding DOUT (Px_DOUT[n]) bit can be updated

#1 : 1

Corresponding DOUT (Px_DOUT[n]) bit protected

End of enumeration elements list.

DATMSK12 : Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding DOUT (Px_DOUT[n]) bit can be updated

#1 : 1

Corresponding DOUT (Px_DOUT[n]) bit protected

End of enumeration elements list.

DATMSK13 : Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding DOUT (Px_DOUT[n]) bit can be updated

#1 : 1

Corresponding DOUT (Px_DOUT[n]) bit protected

End of enumeration elements list.

DATMSK14 : Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding DOUT (Px_DOUT[n]) bit can be updated

#1 : 1

Corresponding DOUT (Px_DOUT[n]) bit protected

End of enumeration elements list.

DATMSK15 : Port A-F Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked, writing data to the protect bit is ineffective.\nNote1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.\nNote2: The PC.13/PC.15/PD.14/PF.8~15 pin is ineffective.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding DOUT (Px_DOUT[n]) bit can be updated

#1 : 1

Corresponding DOUT (Px_DOUT[n]) bit protected

End of enumeration elements list.

PD_MODE

PD I/O Mode Control
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_DINOFF

PD Digital Input Path Disable Control
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_DOUT

PD Data Output Value
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_DATMSK

PD Data Output Write Mask
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_PIN

PD Pin Value
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_DBEN

PD De-bounce Enable Control Register
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_INTTYPE

PD Interrupt Trigger Type Control
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_INTEN

PD Interrupt Enable Control Register
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_INTSRC

PD Interrupt Source Flag
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_SMTEN

PD Input Schmitt Trigger Enable Register
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_SLEWCTL

PD High Slew Rate Control Register
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_PUSEL

PD Pull-up and Pull-down Selection Register
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

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ChipSelect

GPIO

Peripheral Memory Blocks

Registers

PA_MODE

PA_PIN

PE_MODE

PE_DINOFF

PE_DOUT

PE_DATMSK

PE_PIN

PE_DBEN

PE_INTTYPE

PE_INTEN

PE_INTSRC

PE_SMTEN

PE_SLEWCTL

PE_PUSEL

PA_DBEN

PF_MODE

PF_DINOFF

PF_DOUT

PF_DATMSK

PF_PIN

PF_DBEN

PF_INTTYPE

PF_INTEN

PF_INTSRC

PF_SMTEN

PF_SLEWCTL

PF_PUSEL

PA_INTTYPE

PA_INTEN

PA_INTSRC

PA_SMTEN

PA_SLEWCTL

PA_PUSEL

PA_DINOFF

PB_MODE

PB_DINOFF

GPIO_DBCTL (DBCTL)

PB_DOUT

PB_DATMSK

PB_PIN

PB_DBEN

PB_INTTYPE

PB_INTEN

PB_INTSRC

PB_SMTEN

PB_SLEWCTL

PB_PUSEL

PA_DOUT

PC_MODE

PA0_PDIO

PA1_PDIO

PA2_PDIO

PA3_PDIO

PA4_PDIO

PA5_PDIO

PA6_PDIO

PA7_PDIO

PA8_PDIO

PA9_PDIO

PA10_PDIO

PA11_PDIO

PA12_PDIO

PA13_PDIO

PA14_PDIO

PA15_PDIO

PC_DINOFF

PB0_PDIO

PB1_PDIO

PB2_PDIO

PB3_PDIO

PB4_PDIO

PB5_PDIO

PB6_PDIO

PB7_PDIO

PB8_PDIO

PB9_PDIO