Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x400 Bytes (0x0)
size : 0x44 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x480 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x500 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x460 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
Descriptor Table Control Register of PDMA Channel n
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPMODE : PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table, user must check the PDMA_INTSTS[1] to make sure the curren task is complete.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically
#01 : 1
Basic mode: The descriptor table only has one task. When this task is finished, the PDMA_INTSTS[1] will be asserted
#10 : 2
Scatter-gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute
#11 : 3
Reserved.
End of enumeration elements list.
TXTYPE : Transfer Type
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Burst transfer type
#1 : 1
Single transfer type
End of enumeration elements list.
BURSIZE : Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size.\nNote: This field is only useful in burst transfer type.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 0
128 Transfers
#001 : 1
64 Transfers
#010 : 2
32 Transfers
#011 : 3
16 Transfers
#100 : 4
8 Transfers
#101 : 5
4 Transfers
#110 : 6
2 Transfers
#111 : 7
1 Transfers
End of enumeration elements list.
TBINTDIS : Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[7:0]) when PDMA controller finishes transfer task.\nNote: This function only for Scatter-gather mode.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Table interrupt Enabled
#1 : 1
Table interrupt Disabled
End of enumeration elements list.
SAINC : Source Address Increment\nThis field is used to set the source address increment size.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#11 : 3
No increment (fixed address)
End of enumeration elements list.
DAINC : Destination Address Increment\nThis field is used to set the destination address increment size.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#11 : 3
No increment (fixed address)
End of enumeration elements list.
TXWIDTH : Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
One byte (8 bit) is transferred for every operation
#01 : 1
One half-word (16 bit) is transferred for every operation
#10 : 2
One word (32-bit) is transferred for every operation
#11 : 3
Reserved.
End of enumeration elements list.
STRIDEEN : Stride Mode Enable Bit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stride transfer mode Disabled
#1 : 1
Stride transfer mode Enabled
End of enumeration elements list.
TXCNT : Transfer Count\nThe TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384, every transfer may be byte, half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA finish each transfer data, this field will be decreased immediately.
bits : 16 - 31 (16 bit)
access : read-write
Descriptor Table Control Register of PDMA Channel n
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel n
address_offset : 0x100 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CURADDR : PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-gather mode only to indicate the current external description address.
bits : 0 - 31 (32 bit)
access : read-only
Current Scatter-gather Descriptor Table Address of PDMA Channel n
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel n
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel n
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel n
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel n
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel n
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Scatter-gather Descriptor Table Address of PDMA Channel n
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel n
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel n
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel n
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel n
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel n
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel n
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel n
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel n
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel n
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller.
bits : 0 - 31 (32 bit)
access : read-write
Descriptor Table Control Register of PDMA Channel n
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA Channel Control Register
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN0 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
CHEN1 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
CHEN2 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
CHEN3 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
CHEN4 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
CHEN5 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
CHEN6 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
CHEN7 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel [n] Disabled
#1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
PDMA Transfer Pause Control Register
address_offset : 0x404 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PAUSE0 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer
End of enumeration elements list.
PAUSE1 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer
End of enumeration elements list.
PAUSE2 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer
End of enumeration elements list.
PAUSE3 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 3 - 3 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer
End of enumeration elements list.
PAUSE4 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 4 - 4 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer
End of enumeration elements list.
PAUSE5 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 5 - 5 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer
End of enumeration elements list.
PAUSE6 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer
End of enumeration elements list.
PAUSE7 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Pause PDMA channel n transfer
End of enumeration elements list.
PDMA Software Request Register
address_offset : 0x408 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWREQ0 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
SWREQ1 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
SWREQ2 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
SWREQ3 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 3 - 3 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
SWREQ4 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 4 - 4 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
SWREQ5 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 5 - 5 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
SWREQ6 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
SWREQ7 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Generate a software request
End of enumeration elements list.
PDMA Channel Request Status Register
address_offset : 0x40C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REQSTS0 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
REQSTS1 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
REQSTS2 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
REQSTS3 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
REQSTS4 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
REQSTS5 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
REQSTS6 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
REQSTS7 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA Channel n has no request
#1 : 1
PDMA Channel n has a request
End of enumeration elements list.
PDMA Fixed Priority Setting Register
address_offset : 0x410 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPRISET0 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nCorresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
End of enumeration elements list.
FPRISET1 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nCorresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
End of enumeration elements list.
FPRISET2 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nCorresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
End of enumeration elements list.
FPRISET3 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nCorresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
End of enumeration elements list.
FPRISET4 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nCorresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
End of enumeration elements list.
FPRISET5 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nCorresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
End of enumeration elements list.
FPRISET6 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nCorresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
End of enumeration elements list.
FPRISET7 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nCorresponding PDMA channel is round-robin priority
#1 : 1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
End of enumeration elements list.
PDMA Fixed Priority Clear Register
address_offset : 0x414 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FPRICLR0 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
FPRICLR1 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 1 - 1 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
FPRICLR2 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
FPRICLR3 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 3 - 3 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
FPRICLR4 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 4 - 4 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
FPRICLR5 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 5 - 5 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
FPRICLR6 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 6 - 6 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
FPRICLR7 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 7 - 7 (1 bit)
access : write-only
Enumeration:
#0 : 0
No effect
#1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
PDMA Interrupt Enable Register
address_offset : 0x418 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTEN0 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
INTEN1 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
INTEN2 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
INTEN3 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
INTEN4 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
INTEN5 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
INTEN6 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
INTEN7 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out, abort, transfer done and align.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel n interrupt Disabled
#1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
PDMA Interrupt Status Register
address_offset : 0x41C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ABTIF : PDMA Read/Write Target Abort Interrupt Flag (Read Only)\nThis bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No AHB bus ERROR response received
#1 : 1
AHB bus ERROR response received
End of enumeration elements list.
TDIF : Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Not finished yet
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
ALIGNF : Transfer Alignment Interrupt Flag (Read Only)
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel source address and destination address both follow transfer width setting
#1 : 1
PDMA channel source address or destination address is not follow transfer width setting
End of enumeration elements list.
REQTOF0 : Request Time-out Flag for Channel 0\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear this bit.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No request time-out
#1 : 1
Peripheral request time-out
End of enumeration elements list.
REQTOF1 : Request Time-out Flag for Channel 1\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear this bit.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No request time-out
#1 : 1
Peripheral request time-out
End of enumeration elements list.
PDMA Channel Read/Write Target Abort Flag Register
address_offset : 0x420 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ABTIF0 : PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
ABTIF1 : PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
ABTIF2 : PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
ABTIF3 : PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
ABTIF4 : PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
ABTIF5 : PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
ABTIF6 : PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
ABTIF7 : PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received when channel n transfer
#1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
PDMA Channel Transfer Done Flag Register
address_offset : 0x424 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDIF0 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TDIF1 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TDIF2 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TDIF3 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TDIF4 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TDIF5 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TDIF6 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TDIF7 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel transfer has not finished
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
PDMA Transfer Alignment Status Register
address_offset : 0x428 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALIGN0 : Transfer Alignment Flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel source address and destination address both follow transfer width setting
#1 : 1
PDMA channel source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN1 : Transfer Alignment Flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel source address and destination address both follow transfer width setting
#1 : 1
PDMA channel source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN2 : Transfer Alignment Flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel source address and destination address both follow transfer width setting
#1 : 1
PDMA channel source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN3 : Transfer Alignment Flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel source address and destination address both follow transfer width setting
#1 : 1
PDMA channel source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN4 : Transfer Alignment Flag
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel source address and destination address both follow transfer width setting
#1 : 1
PDMA channel source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN5 : Transfer Alignment Flag
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel source address and destination address both follow transfer width setting
#1 : 1
PDMA channel source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN6 : Transfer Alignment Flag
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel source address and destination address both follow transfer width setting
#1 : 1
PDMA channel source address or destination address is not follow transfer width setting
End of enumeration elements list.
ALIGN7 : Transfer Alignment Flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA channel source address and destination address both follow transfer width setting
#1 : 1
PDMA channel source address or destination address is not follow transfer width setting
End of enumeration elements list.
PDMA Transfer Active Flag Register
address_offset : 0x42C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXACTF0 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
TXACTF1 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
TXACTF2 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
TXACTF3 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
TXACTF4 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
TXACTF5 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
TXACTF6 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
TXACTF7 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel is not finished
#1 : 1
PDMA channel is active
End of enumeration elements list.
PDMA Time-out Prescaler Register
address_offset : 0x430 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUTPSC0 : PDMA Channel 0 Time-out Clock Source Prescaler Bits
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
PDMA channel 0 time-out clock source is HCLK/28
#001 : 1
PDMA channel 0 time-out clock source is HCLK/29
#010 : 2
PDMA channel 0 time-out clock source is HCLK/210
#011 : 3
PDMA channel 0 time-out clock source is HCLK/211
#100 : 4
PDMA channel 0 time-out clock source is HCLK/212
#101 : 5
PDMA channel 0 time-out clock source is HCLK/213
#110 : 6
PDMA channel 0 time-out clock source is HCLK/214
#111 : 7
PDMA channel 0 time-out clock source is HCLK/215
End of enumeration elements list.
TOUTPSC1 : PDMA Channel 1 Time-out Clock Source Prescaler Bits
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 0
PDMA channel 1 time-out clock source is HCLK/28
#001 : 1
PDMA channel 1 time-out clock source is HCLK/29
#010 : 2
PDMA channel 1 time-out clock source is HCLK/210
#011 : 3
PDMA channel 1 time-out clock source is HCLK/211
#100 : 4
PDMA channel 1 time-out clock source is HCLK/212
#101 : 5
PDMA channel 1 time-out clock source is HCLK/213
#110 : 6
PDMA channel 1 time-out clock source is HCLK/214
#111 : 7
PDMA channel 1 time-out clock source is HCLK/215
End of enumeration elements list.
PDMA Time-out Enable Register
address_offset : 0x434 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUTEN0 : PDMA Time-out Enable Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel n time-out function Disabled
#1 : 1
PDMA Channel n time-out function Enabled
End of enumeration elements list.
TOUTEN1 : PDMA Time-out Enable Bits
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel n time-out function Disabled
#1 : 1
PDMA Channel n time-out function Enabled
End of enumeration elements list.
PDMA Time-out Interrupt Enable Register
address_offset : 0x438 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUTIEN0 : PDMA Time-out Interrupt Enable Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel n time-out interrupt Disabled
#1 : 1
PDMA Channel n time-out interrupt Enabled
End of enumeration elements list.
TOUTIEN1 : PDMA Time-out Interrupt Enable Bits
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA Channel n time-out interrupt Disabled
#1 : 1
PDMA Channel n time-out interrupt Enabled
End of enumeration elements list.
PDMA Scatter-gather Descriptor Table Base Address Register
address_offset : 0x43C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCATBA : PDMA Scatter-gather Descriptor Table Address\nIn Scatter-gather mode, this is the base address for calculating the next link - list address. The next link address equation is \nNote: Only useful in Scatter-gather mode.
bits : 16 - 31 (16 bit)
access : read-write
Source Address Register of PDMA Channel n
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA Time-out Counter Ch1 and Ch0 Register
address_offset : 0x440 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOC0 : Time-out Counter for Channel 0\nThis controls the period of time-out function for channel 0. The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC0[2:0]) clock.
bits : 0 - 15 (16 bit)
access : read-write
TOC1 : Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1. The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC0[6:4]) clock. The example of time-out period can refer TOC0 bit description.
bits : 16 - 31 (16 bit)
access : read-write
PDMA Channel Reset Register
address_offset : 0x460 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHnRST : Channel n Reset
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0 : 0
corresponding channel n is not reset
1 : 1
corresponding channel n is reset
End of enumeration elements list.
PDMA with SPI Performance Improvement Register
address_offset : 0x464 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel n
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA Request Source Select Register 0
address_offset : 0x480 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REQSRC0 : Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.\nNote 1: A peripheral cannot be assigned to two channels at the same time.\nNote 2: This field is useless when transfer between memory and memory.
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0 : 0
Disable PDMA peripheral request
1 : 1
Reserved.
2 : 2
Reserved.
3 : 3
Reserved.
4 : 4
Channel connects to UART0_TX
5 : 5
Channel connects to UART0_RX
6 : 6
Channel connects to UART1_TX
7 : 7
Channel connects to UART1_RX
8 : 8
Channel connects to UART2_TX
9 : 9
Channel connects to UART2_RX
10 : 10
Reserved.
11 : 11
Reserved.
12 : 12
Reserved.
13 : 13
Reserved.
14 : 14
Reserved.
15 : 15
Reserved.
16 : 16
Channel connects to USCI0_TX
17 : 17
Channel connects to USCI0_RX
18 : 18
Channel connects to USCI1_TX
19 : 19
Channel connects to USCI1_RX
20 : 20
Channel connects to SPI0_TX
21 : 21
Channel connects to SPI0_RX
22 : 22
Channel connects to SPI1_TX
23 : 23
Channel connects to SPI1_RX
24 : 24
Reserved.
25 : 25
Reserved.
26 : 26
Reserved.
27 : 27
Reserved.
28 : 28
Reserved.
29 : 29
Reserved.
30 : 30
Reserved.
31 : 31
Reserved.
32 : 32
Channel connects to PWM0_P1_RX
33 : 33
Channel connects to PWM0_P2_RX
34 : 34
Channel connects to PWM0_P3_RX
35 : 35
Channel connects to PWM1_P1_RX
36 : 36
Channel connects to PWM1_P2_RX
37 : 37
Channel connects to PWM1_P3_RX
38 : 38
Channel connects to I2C0_TX
39 : 39
Channel connects to I2C0_RX
40 : 40
Channel connects to I2C1_TX
41 : 41
Channel connects to I2C1_RX
42 : 42
Reserved.
43 : 43
Reserved.
44 : 44
Reserved.
45 : 45
Reserved.
46 : 46
Channel connects to TMR0
47 : 47
Channel connects to TMR1
48 : 48
Channel connects to TMR2
49 : 49
Channel connects to TMR3
50 : 50
Channel connects to ADC_RX
52 : 52
Reserved.
53 : 53
Reserved.
54 : 54
Reserved.
55 : 55
Reserved.
56 : 56
Reserved.
57 : 57
Reserved.
58 : 58
Reserved.
59 : 59
Reserved.
60 : 60
Reserved.
61 : 61
Reserved.
62 : 62
Reserved.
63 : 63
Reserved.
64 : 64
Reserved.
65 : 65
Reserved.
End of enumeration elements list.
REQSRC1 : Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 14 (7 bit)
access : read-write
REQSRC2 : Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 22 (7 bit)
access : read-write
REQSRC3 : Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 30 (7 bit)
access : read-write
PDMA Request Source Select Register 1
address_offset : 0x484 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REQSRC4 : Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 0 - 6 (7 bit)
access : read-write
REQSRC5 : Channel 5 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 5. User can configure the peripheral setting by REQSRC5. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 14 (7 bit)
access : read-write
REQSRC6 : Channel 6 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 6. User can configure the peripheral setting by REQSRC6. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 22 (7 bit)
access : read-write
REQSRC7 : Channel 7 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 7. User can configure the peripheral setting by REQSRC7. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 30 (7 bit)
access : read-write
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel n
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Stride Transfer Count Register of PDMA Channel 0
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STC : PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row.
bits : 0 - 15 (16 bit)
access : read-write
Address Stride Offset Register of PDMA Channel 0
address_offset : 0x504 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SASOL : VDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row.
bits : 0 - 15 (16 bit)
access : read-write
DASOL : VDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row.
bits : 16 - 31 (16 bit)
access : read-write
Stride Transfer Count Register of PDMA Channel 1
address_offset : 0x508 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Address Stride Offset Register of PDMA Channel 1
address_offset : 0x50C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Stride Transfer Count Register of PDMA Channel 2
address_offset : 0x510 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Address Stride Offset Register of PDMA Channel 2
address_offset : 0x514 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Stride Transfer Count Register of PDMA Channel 3
address_offset : 0x518 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Address Stride Offset Register of PDMA Channel 3
address_offset : 0x51C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Stride Transfer Count Register of PDMA Channel 4
address_offset : 0x520 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Address Stride Offset Register of PDMA Channel 4
address_offset : 0x524 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Stride Transfer Count Register of PDMA Channel 5
address_offset : 0x528 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Address Stride Offset Register of PDMA Channel 5
address_offset : 0x52C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel n
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel n
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel n
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel n
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel n
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Descriptor Table Control Register of PDMA Channel n
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Source Address Register of PDMA Channel n
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel n
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Destination Address Register of PDMA Channel n
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DA : PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller.
bits : 0 - 31 (32 bit)
access : read-write
Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NEXT : PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory. \nWrite Operation:\nIf the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the next descriptor table is start from 0x2000_0100, then this field must fill in 0x0100.\nRead Operation:\nWhen operating in Scatter-gather mode, the last two bits NEXT[1:0] will become reserved, and indicate the first next address of system memory.\nNote1: The descriptor table address must be word boundary.\nNote2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
bits : 0 - 15 (16 bit)
access : read-write
EXENEXT : PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory. \nNote: Write operation is useless in this field.
bits : 16 - 31 (16 bit)
access : read-write
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