TIMER

PSC : Prescale Counter\nNote: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value.
bits : 0 - 7 (8 bit)
access : read-write

FUNCSEL : Function Selection\nNote: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer controller is used as timer function

#1 : 1

Timer controller is used as PWM function

End of enumeration elements list.

INTRGEN : Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function.\nNote: For Timer1/3, this bit is ineffective and the read back value is always 0.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Inter-Timer Trigger Capture mode Disabled

#1 : 1

Inter-Timer Trigger Capture mode Enabled

End of enumeration elements list.

PERIOSEL : Periodic Mode Behavior Selection Enable Bit\nIf updated CMPDAT value CNT, CNT will be reset to default value.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

The behavior selection in periodic mode is Disabled

#1 : 1

The behavior selection in periodic mode is Enabled

End of enumeration elements list.

TGLPINSEL : Toggle-output Pin Select
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Toggle mode output to TMx (Timer Event Counter Pin)

#1 : 1

Toggle mode output to TMx_EXT (Timer External Capture Pin)

End of enumeration elements list.

CAPSRC : Capture Pin Source Selection
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

Capture Function source is from TMx_EXT (x= 0~3) pin

#1 : 1

Capture Function source is from internal ACMP output signal , internal clock (MIRC, LIRC, HIRC), or external clock (HXT, LXT)

End of enumeration elements list.

WKEN : Wake-up Function Enable Bit\nIf this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Wake-up function Disabled if timer interrupt signal generated

#1 : 1

Wake-up function Enabled if timer interrupt signal generated

End of enumeration elements list.

EXTCNTEN : Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Event counter mode Disabled

#1 : 1

Event counter mode Enabled

End of enumeration elements list.

ACTSTS : Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may active when CNT 0 transition to CNT 1.
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

#0 : 0

24-bit up counter is not active

#1 : 1

24-bit up counter is active

End of enumeration elements list.

OPMODE : Timer Counting Mode Select
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

#00 : 0

The timer controller is operated in One-shot mode

#01 : 1

The timer controller is operated in Periodic mode

#10 : 2

The timer controller is operated in Toggle-output mode

#11 : 3

The timer controller is operated in Continuous Counting mode

End of enumeration elements list.

INTEN : Timer Interrupt Enable Bit\nNote: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer time-out interrupt Disabled

#1 : 1

Timer time-out interrupt Enabled

End of enumeration elements list.

CNTEN : Timer Counting Enable Bit\nNote3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Stops/Suspends counting

#1 : 1

Starts counting

End of enumeration elements list.

ICEDEBUG : ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

ICE debug mode acknowledgement effects TIMER counting

#1 : 1

ICE debug mode acknowledgement Disabled

End of enumeration elements list.

TIMER2_CAP

Timer2 Capture Data Register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAPDAT : Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
bits : 0 - 23 (24 bit)
access : read-only

TIMER3_CTL

Timer3 Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER3_CMP

Timer3 Comparator Register
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER3_INTSTS

Timer3 Interrupt Status Register
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER3_CNT

Timer3 Data Register
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER3_CAP

Timer3 Capture Data Register
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER3_EXTCTL

Timer3 External Control Register
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER3_EINTSTS

Timer3 External Interrupt Status Register
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER3_TRGCTL

Timer3 Trigger Control Register
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER2_EXTCTL

Timer2 External Control Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTPHASE : Timer External Count Phase
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

A falling edge of external counting pin will be counted

#1 : 1

A rising edge of external counting pin will be counted

End of enumeration elements list.

CAPEN : Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: When CAPEN is 1, user can set INTERCAPSEL (TIMERx_EXTCTL [10:8]) to select capture source.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Capture source Disabled

#1 : 1

Capture source Enabled

End of enumeration elements list.

CAPFUNCS : Capture Function Selection
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

External Capture Mode Enabled

#1 : 1

External Reset Mode Enabled

End of enumeration elements list.

CAPIEN : Timer External Capture Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock detection Interrupt Disabled

#1 : 1

TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock detection Interrupt Enabled

End of enumeration elements list.

CAPDBEN : Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Disabled

#1 : 1

TMx_EXT (x= 0~3) pin de-bounce or ACMP output de-bounce Enabled

End of enumeration elements list.

CNTDBEN : Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

TMx (x= 0~3) pin de-bounce Disabled

#1 : 1

TMx (x= 0~3) pin de-bounce Enabled

End of enumeration elements list.

INTERCAPSEL : Internal Capture Source Select\nNote: these bits only available when CAPSRC (TIMERx_CTL[22]) is 1.
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 0

Capture Function source is from internal ACMP0 output signal

#001 : 1

Capture Function source is from internal ACMP1 output signal

#010 : 2

Capture Function source is from HXT

#011 : 3

Capture Function source is from LXT

#100 : 4

Capture Function source is from HIRC

#101 : 5

Capture Function source is from LIRC

#110 : 6

Capture Function source is from MIRC

#111 : 7

Reserved.

End of enumeration elements list.

CAPEDGE : Timer External Capture Pin Edge Detect\nWhen first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0.\nNote: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL (TIMERx_EXTCTL[10:8]) to select capture source.
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 0

Capture event occurred when detect falling edge transfer on TMx_EXT (x= 0~3) pin

#001 : 1

Capture event occurred when detect rising edge transfer on TMx_EXT (x= 0~3) pin

#010 : 2

Capture event occurred when detect both falling and rising edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at falling edge transfer

#011 : 3

Capture event occurred when detect both rising and falling edge transfer on TMx_EXT (x= 0~3) pin, and first capture event occurred at rising edge transfer

#110 : 6

First capture event occurred at falling edge, follows capture events are at rising edge transfer on TMx_EXT (x= 0~3) pin

#111 : 7

First capture event occurred at rising edge, follows capture events are at falling edge transfer on TMx_EXT (x= 0~3) pin

End of enumeration elements list.

ECNTSSEL : Event Counter Source Selection to Trigger Event Counter Function
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Event Counter input source is from TMx (x= 0~3) pin

#1 : 1

Event Counter input source is from USB internal SOF output signal

End of enumeration elements list.

CAPDIVSCL : Timer Capture Source Divider Scale\nThis bits indicate the divide scale for capture source divider \nNote: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source.
bits : 28 - 31 (4 bit)
access : read-write

Enumeration:

#0000 : 0

Capture source/1

#0001 : 1

Capture source/2

#0010 : 2

Capture source/4

#0011 : 3

Capture source/8

#0100 : 4

Capture source/16

#0101 : 5

Capture source/32

#0110 : 6

Capture source/64

#0111 : 7

Capture source/128

#1000 : 8

Capture source/256

End of enumeration elements list.

TIMER3_PWMCTL

Timer3 PWM Control Register
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER3_PWMCLKPSC

Timer3 PWM Counter Clock Pre-scale Register
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER3_PWMCNTCLR

Timer3 PWM Clear Counter Register
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER3_PWMPERIOD

Timer3 PWM Period Register
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER3_PWMCMPDAT

Timer3 PWM Comparator Register
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER3_PWMCNT

Timer3 PWM Counter Register
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER3_PWMPOLCTL

Timer3 PWM Pin Output Polar Control Register
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER3_PWMPOCTL

Timer3 PWM Pin Output Control Register
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER3_PWMINTEN0

Timer3 PWM Interrupt Enable Register 0
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER3_PWMINTSTS0

Timer3 PWM Interrupt Status Register 0
address_offset : 0x164 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER3_PWMTRGCTL

Timer3 PWM Trigger Control Register
address_offset : 0x168 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER3_PWMSTATUS

Timer3 PWM Status Register
address_offset : 0x16C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER3_PWMPBUF

Timer3 PWM Period Buffer Register
address_offset : 0x170 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER3_PWMCMPBUF

Timer3 PWM Comparator Buffer Register
address_offset : 0x174 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER2_EINTSTS

Timer2 External Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPIF : Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock interrupt did not occur

#1 : 1

TMx_EXT (x= 0~3) pin, ACMP, internal clock, or external clock interrupt occurred

End of enumeration elements list.

TIMER2_TRGCTL

Timer2 Trigger Control Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGSSEL : Trigger Source Select Bit\nThis bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Time-out interrupt signal is used to internal trigger PWM, PDMA, DAC, and EADC

#1 : 1

Capture interrupt signal is used to internal trigger PWM, PDMA, DAC, and EADC

End of enumeration elements list.

TRGPWM : Trigger PWM/BPWM Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be as PWM/BPWM counter clock source.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer interrupt trigger PWM/BPWM Disabled

#1 : 1

Timer interrupt trigger PWM/BPWM Enabled

End of enumeration elements list.

TRGEADC : Trigger EADC Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer interrupt trigger EADC Disabled

#1 : 1

Timer interrupt trigger EADC Enabled

End of enumeration elements list.

TRGDAC : Trigger DAC Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered DAC.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer interrupt trigger DAC Disabled

#1 : 1

Timer interrupt trigger DAC Enabled

End of enumeration elements list.

TRGPDMA : Trigger PDMA Enable Bit\nIf this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer interrupt trigger PDMA Disabled

#1 : 1

Timer interrupt trigger PDMA Enabled

End of enumeration elements list.

TIMER2_CMP

Timer2 Comparator Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPDAT : Timer Comparator Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
bits : 0 - 23 (24 bit)
access : read-write

TIMER2_PWMCTL

Timer2 PWM Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTEN : PWM Counter Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM counter and clock prescale Stop Running

#1 : 1

PWM counter and clock prescale Start Running

End of enumeration elements list.

CNTMODE : PWM Counter Mode
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Auto-reload mode

#1 : 1

One-shot mode

End of enumeration elements list.

PWMINTWKEN : PWM Interrupt Wake-up Enable Bit\nIf PWM interrupt occurs when chip is in Power-down mode, PWMINTWKEN can determine whether chip wake-up occurs or not.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM interrupt wake-up Disabled

#1 : 1

PWM interrupt wake-up Enabled

End of enumeration elements list.

DBGHALT : ICE Debug Mode Counter Halt (Write Protect)\nIf debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL control register.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

ICE debug mode counter halt Disabled

#1 : 1

ICE debug mode counter halt Enabled

End of enumeration elements list.

DBGTRIOFF : ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM output pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL control register.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

ICE debug mode acknowledgement effects PWM output

#1 : 1

ICE debug mode acknowledgement disabled

End of enumeration elements list.

TIMER2_PWMCLKPSC

Timer2 PWM Counter Clock Pre-scale Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKPSC : PWM Counter Clock Pre-scale \nThe active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). If CLKPSC is 0, then there is no scaling in PWM counter clock source.
bits : 0 - 7 (8 bit)
access : read-write

TIMER2_PWMCNTCLR

Timer2 PWM Clear Counter Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTCLR : Clear PWM Counter Control Bit\nIt is automatically cleared by hardware.\nNote: Timer peripheral clock source should be set as PCLK to ensure that this bit can be automatically cleared by hardware.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Clear 16-bit PWM counter to 0x0000 in up count type

End of enumeration elements list.

TIMER2_PWMPERIOD

Timer2 PWM Period Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERIOD : PWM Period Register\nIn up count type: PWM counter counts from 0 to PERIOD, and restarts from 0.\nIn up count type:
bits : 0 - 15 (16 bit)
access : read-write

TIMER2_PWMCMPDAT

Timer2 PWM Comparator Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMP : PWM Comparator Register\nPWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger EADC, PDMA, and DAC start convert.
bits : 0 - 15 (16 bit)
access : read-write

TIMER2_PWMCNT

Timer2 PWM Counter Register
address_offset : 0x54 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CNT : PWM Counter Value Register (Read Only)\nUser can monitor CNT to know the current counter value in 16-bit period counter.
bits : 0 - 15 (16 bit)
access : read-only

TIMER2_PWMPOLCTL

Timer2 PWM Pin Output Polar Control Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINV : PWMx Output Pin Polar Control Bit\nThe bit is used to control polarity state of PWMx_OUT pin.\nNote: Sets POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWMx_OUT pin polar inverse Disabled

#1 : 1

PWMx_OUT polar inverse Enabled

End of enumeration elements list.

TIMER2_PWMPOCTL

Timer2 PWM Pin Output Control Register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POEN : PWMx Output Pin Enable Bit\nNote: Set POSEL (TIMERx_PWMPOCTL[8]) to select TMx or TMx_EXT as PWMx output pin.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWMx_OUT pin at tri-state mode

#1 : 1

PWMx_OUT pin in output mode

End of enumeration elements list.

POSEL : PWM Output Pin Select
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWMx_OUT pin is TMx

#1 : 1

PWMx_OUT pin is TMx_EXT

End of enumeration elements list.

TIMER2_PWMINTEN0

Timer2 PWM Interrupt Enable Register 0
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIEN : PWM Period Point Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Period point interrupt Disabled

#1 : 1

Period point interrupt Enabled

End of enumeration elements list.

CMPUIEN : PWM Compare Up Count Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Compare up count interrupt Disabled

#1 : 1

Compare up count interrupt Enabled

End of enumeration elements list.

TIMER2_PWMINTSTS0

Timer2 PWM Interrupt Status Register 0
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIF : PWM Period Point Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter reaches PERIOD.\nNote: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write

CMPUIF : PWM Compare Up Count Interrupt Flag\nThis bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP.\nNote1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type. Note2: This bit is cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write

TIMER2_PWMTRGCTL

Timer2 PWM Trigger Control Register
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGSEL : PWM Counter Event Source Select to Trigger Conversion
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Trigger conversion at period point (PIF)

#01 : 1

Trigger conversion at compare up count point (CMPUIF)

#10 : 2

Trigger conversion at period or compare up count point (PIF or CMPUIF)

#11 : 3

Reserved.

End of enumeration elements list.

PWMTRGEADC : PWM Counter Event Trigger EADC Conversion Enable Bit\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM counter event trigger EADC conversion Disabled

#1 : 1

PWM counter event trigger EADC conversion Enabled

End of enumeration elements list.

PWMTRGDAC : PWM Counter Event Trigger DAC Conversion Enable Bit\nIf this bit is set to 1, PWM can trigger DAC conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM trigger DAC Disabled

#1 : 1

PWM trigger DAC Enabled

End of enumeration elements list.

PWMTRGPDMA : PWM Counter Event Trigger PDMA Conversion Enable Bit\nIf this bit is set to 1, PWM can trigger PDMA conversion.\nNote: Set TRGSEL (TIMERx_PWMTRGCTL[1:0]) to select PWM trigger conversion source.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM trigger PDMA Disabled

#1 : 1

PWM trigger PDMA Enabled

End of enumeration elements list.

TIMER2_PWMSTATUS

Timer2 PWM Status Register
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTMAXF : PWM Counter Equal to 0xFFFF Flag\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The PWM counter value never reached its maximum value 0xFFFF

#1 : 1

The PWM counter value has reached its maximum value

End of enumeration elements list.

PWMINTWKF : PWM Interrupt Wake-up Flag\nNote: This bit is cleared by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM interrupt wake-up has not occurred

#1 : 1

PWM interrupt wake-up has occurred

End of enumeration elements list.

EADCTRGF : Trigger EADC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM counter event trigger EADC start conversion is not occurred

#1 : 1

PWM counter event trigger EADC start conversion has occurred

End of enumeration elements list.

DACTRGF : Trigger DAC Start Conversion Flag\nNote: This bit is cleared by writing 1 to it.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM counter event trigger DAC start conversion has not occurred

#1 : 1

PWM counter event trigger DAC start conversion has occurred

End of enumeration elements list.

PDMATRGF : Trigger PDMA Start Conversion Flag\nNote: This bit is cleared by writing 1 to it.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM counter event trigger PDMA start conversion has not occurred

#1 : 1

PWM counter event trigger PDMA start conversion has occurred

End of enumeration elements list.

TIMER2_PWMPBUF

Timer2 PWM Period Buffer Register
address_offset : 0x70 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PBUF : PWM Period Buffer Register (Read Only)\nUsed as PERIOD active register.
bits : 0 - 15 (16 bit)
access : read-only

TIMER2_PWMCMPBUF

Timer2 PWM Comparator Buffer Register
address_offset : 0x74 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CMPBUF : PWM Comparator Buffer Register (Read Only)\nUsed as CMP active register.
bits : 0 - 15 (16 bit)
access : read-only

TIMER2_INTSTS

Timer2 Interrupt Status Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIF : Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

CNT value matches the CMPDAT value

End of enumeration elements list.

TWKF : Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer does not cause CPU wake-up

#1 : 1

CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated

End of enumeration elements list.

TIMER2_CNT

Timer2 Data Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNT : Timer Data Register\nRead operation.\nRead this register to get CNT value. For example:\nIf EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value.\nIf EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value.\nWrite operation.\nWriting any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter.
bits : 0 - 23 (24 bit)
access : read-write

RSTACT : Timer Data Register Reset Active (Read Only)\nThis bit indicates if the counter reset operation active.\nWhen user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress. Once the counter reset operation done, timer clear this bit to 0 automatically.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

#0 : 0

Reset operation is done

#1 : 1

Reset operation triggered by writing TIMERx_CNT is in progress

End of enumeration elements list.

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TIMER

Peripheral Memory Blocks

Registers

TIMER2_CTL

TIMER2_CAP

TIMER3_CTL

TIMER3_CMP

TIMER3_INTSTS

TIMER3_CNT

TIMER3_CAP

TIMER3_EXTCTL

TIMER3_EINTSTS

TIMER3_TRGCTL

TIMER2_EXTCTL

TIMER3_PWMCTL

TIMER3_PWMCLKPSC

TIMER3_PWMCNTCLR

TIMER3_PWMPERIOD

TIMER3_PWMCMPDAT

TIMER3_PWMCNT

TIMER3_PWMPOLCTL

TIMER3_PWMPOCTL

TIMER3_PWMINTEN0

TIMER3_PWMINTSTS0

TIMER3_PWMTRGCTL

TIMER3_PWMSTATUS

TIMER3_PWMPBUF

TIMER3_PWMCMPBUF

TIMER2_EINTSTS

TIMER2_TRGCTL

TIMER2_CMP

TIMER2_PWMCTL

TIMER2_PWMCLKPSC

TIMER2_PWMCNTCLR

TIMER2_PWMPERIOD

TIMER2_PWMCMPDAT

TIMER2_PWMCNT

TIMER2_PWMPOLCTL

TIMER2_PWMPOCTL

TIMER2_PWMINTEN0

TIMER2_PWMINTSTS0

TIMER2_PWMTRGCTL

TIMER2_PWMSTATUS

TIMER2_PWMPBUF

TIMER2_PWMCMPBUF

TIMER2_INTSTS

TIMER2_CNT