\n

RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x120 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x130 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x110 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x8 Bytes (0x0)
size : 0x4C byte (0x0)
mem_usage : registers
protection : not protected

Registers

RTC_INIT (INIT)

RTC_CAL (CAL)

RTC_LXTCTL (LXTCTL)

RTC_GPIOCTL0 (GPIOCTL0)

RTC_DSTCTL (DSTCTL)

RTC_TAMPCTL (TAMPCTL)

RTC_TAMPTIME (TAMPTIME)

RTC_TAMPCAL (TAMPCAL)

RTC_CLKFMT (CLKFMT)

RTC_WEEKDAY (WEEKDAY)

RTC_TALM (TALM)

RTC_CALM (CALM)

RTC_LEAPYEAR (LEAPYEAR)

RTC_INTEN (INTEN)

RTC_INTSTS (INTSTS)

RTC_TICK (TICK)

RTC_TAMSK (TAMSK)

RTC_CAMSK (CAMSK)

RTC_SPRCTL (SPRCTL)

RTC_SPR0 (SPR0)

RTC_SPR1 (SPR1)

RTC_SPR2 (SPR2)

RTC_SPR3 (SPR3)

RTC_SPR4 (SPR4)

RTC_FREQADJ (FREQADJ)

RTC_TIME (TIME)


RTC_INIT (INIT)

RTC Initiation Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_INIT RTC_INIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT_ACTIVE INIT

INIT_ACTIVE : RTC Active Status (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

RTC is at reset state

#1 : 1

RTC is at normal active state

End of enumeration elements list.

INIT : RTC Initiation (Write Only)\nWhen RTC block is powered on, RTC is at reset state. User has to write a number (0x a5eb1357) to INIT to make RTC leave reset state. Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.\nThe INIT is a write-only field and read value will be always 0.
bits : 1 - 31 (31 bit)
access : write-only


RTC_CAL (CAL)

RTC Calendar Loading Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_CAL RTC_CAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAY TENDAY MON TENMON YEAR TENYEAR

DAY : 1-Day Calendar Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write

TENDAY : 10-Day Calendar Digit (0~3)
bits : 4 - 5 (2 bit)
access : read-write

MON : 1-Month Calendar Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write

TENMON : 10-Month Calendar Digit (0~1)
bits : 12 - 12 (1 bit)
access : read-write

YEAR : 1-Year Calendar Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write

TENYEAR : 10-Year Calendar Digit (0~9)
bits : 20 - 23 (4 bit)
access : read-write


RTC_LXTCTL (LXTCTL)

RTC 32.768 KHz Oscillator Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_LXTCTL RTC_LXTCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GAIN C32KS RTCLVDPD RTCPORPD

GAIN : Oscillator Gain Option\nUser can select oscillator gain according to crystal external loading and operating temperature range. The larger gain value corresponding to stronger driving capability and higher power consumption.\nNote: Please refer to the M251 Datasheet for detailed information about LXT electrical characteristics.
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

#000 : 0

L0 mode

#001 : 1

L1 mode

#010 : 2

L2 mode

#011 : 3

L3 mode

#100 : 4

L4 mode. (Only for VBAT domain)

#101 : 5

L5 mode. (Only for VBAT domain)

#110 : 6

L6 mode. (Only for VBAT domain)

#111 : 7

L7 mode. (Only for VBAT domain)

End of enumeration elements list.

C32KS : Clock 32K Source Selection:
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal 32K clock is from 32K crystal

#1 : 1

Internal 32K clock is from LIRC32K

End of enumeration elements list.

RTCLVDPD : RTC Low Voltage Detector Power Down (Only for VBAT Domain)
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC Low Voltage Detector active.

#1 : 1

RTC Low Voltage Detector enter power down

End of enumeration elements list.

RTCPORPD : RTC Power on Reset Power Down (Only for VBAT Domain)\nNote: This bit only can be set to 1.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC POR active 1sec after first power up

#1 : 1

RTC POR enter power down

End of enumeration elements list.


RTC_GPIOCTL0 (GPIOCTL0)

RTC GPIO Control 0 Register
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_GPIOCTL0 RTC_GPIOCTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPMODE0 DOUT0 CTLSEL0 PUSEL0 SMTEN0 OPMODE1 DOUT1 CTLSEL1 PUSEL1 SMTEN1 OPMODE2 DOUT2 CTLSEL2 PUSEL2 SMTEN2

OPMODE0 : IO Operation Mode (Only for VBAT Domain)
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

PF.4 is input only mode

#01 : 1

PF.4 is output push pull mode

#10 : 2

PF.4 is open drain mode

#11 : 3

PF.4 is quasi-bidirectional mode

End of enumeration elements list.

DOUT0 : IO Output Data (Only for VBAT Domain)
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

PF.4 output low

#1 : 1

PF.4 output high

End of enumeration elements list.

CTLSEL0 : IO Pin State Backup Selection (Only for VBAT Domain)\nWhen low speed 32 kHz oscillator is disabled, PF.4 pin (X32KO pin) can be used as GPIO function. User can program CTLSEL0 to decide PF.4 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.\nPF.4 pin function and I/O status are controlled by OPMODE0[1:0] and DOUT0 after CTLSEL0 is set to 1.\nNote1: CTLSEL0 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0])] (RTC Active Status) is 1.\nNote2: The GPIO control feature is not supported when there is not any VBAT power domain.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

PF.4 pin I/O function is controlled by GPIO module

#1 : 1

PF.4 pin I/O function is controlled by VBAT power domain

End of enumeration elements list.

PUSEL0 : IO Pull-up and Pull-down Enable Bits (Only for VBAT Domain)\nDetermine PF.4 I/O pull-up or pull-down.\nNote: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when OPMODE0 set as input tri-state and open-drain mode.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

PF.4 pull-up and pull-down disabled

#01 : 1

PF.4 pull-up enabled

#10 : 2

PF.4 pull-down enabled

#11 : 3

PF.4 pull-up and pull-down disabled

End of enumeration elements list.

SMTEN0 : Input Schmitt Trigger Enable Bit (Only for VBAT Domain)
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

PF.4 input schmitt trigger function Disabled

#1 : 1

PF.4 input schmitt trigger function Enabled

End of enumeration elements list.

OPMODE1 : IO Operation Mode (Only for VBAT Domain)
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 0

PF.5 is input only mode

#01 : 1

PF.5 is output push pull mode

#10 : 2

PF.5 is open drain mode

#11 : 3

PF.5 is quasi-bidirectional mode

End of enumeration elements list.

DOUT1 : IO Output Data (Only for VBAT Domain)
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

PF.5 output low

#1 : 1

PF.5 output high

End of enumeration elements list.

CTLSEL1 : IO Pin State Backup Selection (Only for VBAT Domain)\nWhen low speed 32 kHz oscillator is disabled, PF.5 pin (X32KI pin) can be used as GPIO function. User can program CTLSEL1 to decide PF.5 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.\nPF.5 pin function and I/O status are controlled by OPMODE1[1:0] and DOUT1 after CTLSEL1 is set to 1.\nNote1: CTLSEL1 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0])] (RTC Active Status) is 1.\nNote2: The GPIO control feature is not supported when there is not any VBAT power domain.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

PF.5 pin I/O function is controlled by GPIO module

#1 : 1

PF.5 pin I/O function is controlled by VBAT power domain

End of enumeration elements list.

PUSEL1 : IO Pull-up and Pull-down Enable Bits (Only for VBAT Domain)\nDetermine PF.5 I/O pull-up or pull-down.\nNote: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when OPMODE1 set as input tri-state and open-drain mode.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 0

PF.5 pull-up and pull-down disabled

#01 : 1

PF.5 pull-up enabled

#10 : 2

PF.5 pull-down enabled

#11 : 3

PF.5 pull-up and pull-down disabled

End of enumeration elements list.

SMTEN1 : Input Schmitt Trigger Enable Bit (Only for VBAT Domain)
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

PF.5 input schmitt trigger function Disabled

#1 : 1

PF.5 input schmitt trigger function Enabled

End of enumeration elements list.

OPMODE2 : IO Operation Mode (Only for VBAT Domain)
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 0

PF.6 is input only mode

#01 : 1

PF.6 is output push pull mode

#10 : 2

PF.6 is open drain mode

#11 : 3

PF.6 is quasi-bidirectional mode

End of enumeration elements list.

DOUT2 : IO Output Data (Only for VBAT Domain)
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

PF.6 output low

#1 : 1

PF.6 output high

End of enumeration elements list.

CTLSEL2 : IO Pin State Backup Selection (Only for VBAT Domain)When TAMP0EN is disabled, PF.6 pin (TAMPER0 pin) can be used as GPIO function. User can program CTLSEL2 to decide PF.6 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.\nPF.6 pin function and I/O status are controlled by OPMODE2[1:0] and DOUT2 after CTLSEL2 is set to 1.\nNote1: CTLSEL2 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0])] (RTC Active Status) is 1.\nNote2: The GPIO control feature is not supported when there is not any VBAT power domain.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

PF.6 pin I/O function is controlled by GPIO module

#1 : 1

PF.6 pin I/O function is controlled by VBAT power domain

End of enumeration elements list.

PUSEL2 : IO Pull-up and Pull-down Enable Bits (Only for VBAT Domain)\nDetermine PF.6 I/O pull-up or pull-down.\nThe independent pull-up / pull-down control register only valid when OPMODE2 set as input tri-state and open-drain mode and PF6 as tamper pin.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 0

PF.6 pull-up and pull-down disabled

#01 : 1

PF.6 pull-up enabled

#10 : 2

PF.6 pull-down enabled

#11 : 3

PF.6 pull-up and pull-down disabled.Note: Basically, the pull-up control and pull-down control has following behavior limitation

End of enumeration elements list.

SMTEN2 : Input Schmitt Trigger Enable Bit (Only for VBAT Domain)
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

PF.6 input schmitt trigger function Disabled

#1 : 1

PF.6 input schmitt trigger function Enabled

End of enumeration elements list.


RTC_DSTCTL (DSTCTL)

RTC Daylight Saving Time Control Register
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_DSTCTL RTC_DSTCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDHR SUBHR DSBAK

ADDHR : Add 1 Hour
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Indicates RTC hour digit has been added one hour for summer time change

End of enumeration elements list.

SUBHR : Subtract 1 Hour
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Indicates RTC hour digit has been subtracted one hour for winter time change

End of enumeration elements list.

DSBAK : Daylight Saving Back
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Daylight Saving Change is not performed

#1 : 1

Daylight Saving Change is performed

End of enumeration elements list.


RTC_TAMPCTL (TAMPCTL)

RTC Tamper Pin Control Register
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_TAMPCTL RTC_TAMPCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAMP0EN TAMP0LV TAMP0DBEN TAMP0TYPE

TAMP0EN : Tamper0 Detect Enable Bit\nNote: The reference is RTC-clock. Tamper detector need sync 2 ~ 3 RTC-clock.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper 0 detect Disabled

#1 : 1

Tamper 0 detect Enabled

End of enumeration elements list.

TAMP0LV : Tamper 0 Level\nThis bit depends on level attribute of tamper pin for static tamper detection.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Detect Rising detection, will trigger tamper status when RTC_TAMPCTL[11] = 1

#1 : 1

Detect Falling detection, will trigger tamper status when RTC_TAMPCTL[11] = 1

End of enumeration elements list.

TAMP0DBEN : Tamper 0 De-bounce Enable Bit\nNote: In normal condition (25 ), it can deglitch 1~2 ns noise.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper 0 de-bounce Disabled

#1 : 1

Tamper 0 de-bounce Enabled., tamper detection pin will sync 1 RTC clock

End of enumeration elements list.

TAMP0TYPE : Tamper 0 DetectType
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper as edge detector

#1 : 1

Tamper as Level detector

End of enumeration elements list.


RTC_TAMPTIME (TAMPTIME)

RTC Tamper Time Register
address_offset : 0x130 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RTC_TAMPTIME RTC_TAMPTIME read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEC TENSEC MIN TENMIN HR TENHR

SEC : 1-Sec Time Digit of TAMPER Time (0~9)
bits : 0 - 3 (4 bit)
access : read-only

TENSEC : 10-Sec Time Digit of TAMPER Time (0~5)
bits : 4 - 6 (3 bit)
access : read-only

MIN : 1-Min Time Digit of TAMPER Time (0~9)
bits : 8 - 11 (4 bit)
access : read-only

TENMIN : 10-Min Time Digit of TAMPER Time (0~5)
bits : 12 - 14 (3 bit)
access : read-only

HR : 1-Hour Time Digit of TAMPER Time (0~9)
bits : 16 - 19 (4 bit)
access : read-only

TENHR : 10-Hour Time Digit of TAMPER Time (0~2) \nNote: 24-hour time scale only.
bits : 20 - 21 (2 bit)
access : read-only


RTC_TAMPCAL (TAMPCAL)

RTC Tamper Calendar Register
address_offset : 0x134 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RTC_TAMPCAL RTC_TAMPCAL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAY TENDAY MON TENMON YEAR TENYEAR

DAY : 1-Day Calendar Digit of TAMPER Calendar (0~9)
bits : 0 - 3 (4 bit)
access : read-only

TENDAY : 10-Day Calendar Digit of TAMPER Calendar (0~3)
bits : 4 - 5 (2 bit)
access : read-only

MON : 1-Month Calendar Digit of TAMPER Calendar (0~9)
bits : 8 - 11 (4 bit)
access : read-only

TENMON : 10-Month Calendar Digit of TAMPER Calendar (0~1)
bits : 12 - 12 (1 bit)
access : read-only

YEAR : 1-Year Calendar Digit of TAMPER Calendar (0~9)
bits : 16 - 19 (4 bit)
access : read-only

TENYEAR : 10-Year Calendar Digit of TAMPER Calendar (0~9)
bits : 20 - 23 (4 bit)
access : read-only


RTC_CLKFMT (CLKFMT)

RTC Time Scale Selection Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_CLKFMT RTC_CLKFMT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _24HEN

_24HEN : 24-hour / 12-hour Time Scale Selection\nIndicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

12-hour time scale with AM and PM indication selected

#1 : 1

24-hour time scale selected

End of enumeration elements list.


RTC_WEEKDAY (WEEKDAY)

RTC Day of the Week Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_WEEKDAY RTC_WEEKDAY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WEEKDAY

WEEKDAY : Day of the Week Register
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

Sunday

#001 : 1

Monday

#010 : 2

Tuesday

#011 : 3

Wednesday

#100 : 4

Thursday

#101 : 5

Friday

#110 : 6

Saturday

#111 : 7

Reserved.

End of enumeration elements list.


RTC_TALM (TALM)

RTC Time Alarm Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_TALM RTC_TALM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEC TENSEC MIN TENMIN HR TENHR

SEC : 1-Sec Time Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write

TENSEC : 10-Sec Time Digit of Alarm Setting (0~5)
bits : 4 - 6 (3 bit)
access : read-write

MIN : 1-Min Time Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write

TENMIN : 10-Min Time Digit of Alarm Setting (0~5)
bits : 12 - 14 (3 bit)
access : read-write

HR : 1-Hour Time Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write

TENHR : 10-Hour Time Digit of Alarm Setting (0~2)When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
bits : 20 - 21 (2 bit)
access : read-write


RTC_CALM (CALM)

RTC Calendar Alarm Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_CALM RTC_CALM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAY TENDAY MON TENMON YEAR TENYEAR

DAY : 1-Day Calendar Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write

TENDAY : 10-Day Calendar Digit of Alarm Setting (0~3)
bits : 4 - 5 (2 bit)
access : read-write

MON : 1-Month Calendar Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write

TENMON : 10-Month Calendar Digit of Alarm Setting (0~1)
bits : 12 - 12 (1 bit)
access : read-write

YEAR : 1-Year Calendar Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write

TENYEAR : 10-Year Calendar Digit of Alarm Setting (0~9)
bits : 20 - 23 (4 bit)
access : read-write


RTC_LEAPYEAR (LEAPYEAR)

RTC Leap Year Indicator Register
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RTC_LEAPYEAR RTC_LEAPYEAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEAPYEAR

LEAPYEAR : Leap Year Indication (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

This year is not a leap year

#1 : 1

This year is leap year

End of enumeration elements list.


RTC_INTEN (INTEN)

RTC Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_INTEN RTC_INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALMIEN TICKIEN TAMP0IEN

ALMIEN : Alarm Interrupt Enable Bit\nSet ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC Alarm interrupt Disabled

#1 : 1

RTC Alarm interrupt Enabled

End of enumeration elements list.

TICKIEN : Time Tick Interrupt Enable Bit\nSet TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC Time Tick interrupt Disabled

#1 : 1

RTC Time Tick interrupt Enabled

End of enumeration elements list.

TAMP0IEN : Tamper 0 Interrupt Enable Bit\nSet TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tamper 0 interrupt Disabled

#1 : 1

Tamper 0 interrupt Enabled

End of enumeration elements list.


RTC_INTSTS (INTSTS)

RTC Interrupt Status Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_INTSTS RTC_INTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALMIF TICKIF TAMP0IF

ALMIF : RTC Alarm Interrupt Flag\nNote: Write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Alarm condition is not matched

#1 : 1

Alarm condition is matched

End of enumeration elements list.

TICKIF : RTC Time Tick Interrupt Flag\nNote: Write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tick condition did not occur

#1 : 1

Tick condition occurred

End of enumeration elements list.

TAMP0IF : Tamper 0 Interrupt Flag\nNote: Write 1 to clear this bit.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

No Tamper 0 interrupt flag is generated

#1 : 1

Tamper 0 interrupt flag is generated

End of enumeration elements list.


RTC_TICK (TICK)

RTC Time Tick Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_TICK RTC_TICK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TICK

TICK : Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

Time tick is 1 second

#001 : 1

Time tick is 1/2 second

#010 : 2

Time tick is 1/4 second

#011 : 3

Time tick is 1/8 second

#100 : 4

Time tick is 1/16 second

#101 : 5

Time tick is 1/32 second

#110 : 6

Time tick is 1/64 second

#111 : 7

Time tick is 1/128 second

End of enumeration elements list.


RTC_TAMSK (TAMSK)

RTC Time Alarm Mask Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_TAMSK RTC_TAMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSEC MTENSEC MMIN MTENMIN MHR MTENHR

MSEC : Mask 1-Sec Time Digit of Alarm Setting (0~9)
bits : 0 - 0 (1 bit)
access : read-write

MTENSEC : Mask 10-Sec Time Digit of Alarm Setting (0~5)
bits : 1 - 1 (1 bit)
access : read-write

MMIN : Mask 1-Min Time Digit of Alarm Setting (0~9)
bits : 2 - 2 (1 bit)
access : read-write

MTENMIN : Mask 10-Min Time Digit of Alarm Setting (0~5)
bits : 3 - 3 (1 bit)
access : read-write

MHR : Mask 1-Hour Time Digit of Alarm Setting (0~9)
bits : 4 - 4 (1 bit)
access : read-write

MTENHR : Mask 10-Hour Time Digit of Alarm Setting (0~2)
bits : 5 - 5 (1 bit)
access : read-write


RTC_CAMSK (CAMSK)

RTC Calendar Alarm Mask Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_CAMSK RTC_CAMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDAY MTENDAY MMON MTENMON MYEAR MTENYEAR

MDAY : Mask 1-Day Calendar Digit of Alarm Setting (0~9)
bits : 0 - 0 (1 bit)
access : read-write

MTENDAY : Mask 10-Day Calendar Digit of Alarm Setting (0~3)
bits : 1 - 1 (1 bit)
access : read-write

MMON : Mask 1-Month Calendar Digit of Alarm Setting (0~9)
bits : 2 - 2 (1 bit)
access : read-write

MTENMON : Mask 10-Month Calendar Digit of Alarm Setting (0~1)
bits : 3 - 3 (1 bit)
access : read-write

MYEAR : Mask 1-Year Calendar Digit of Alarm Setting (0~9)
bits : 4 - 4 (1 bit)
access : read-write

MTENYEAR : Mask 10-Year Calendar Digit of Alarm Setting (0~9)
bits : 5 - 5 (1 bit)
access : read-write


RTC_SPRCTL (SPRCTL)

RTC Spare Functional Control Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPRCTL RTC_SPRCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPRCLRM SPRRWEN SPRCSTS

SPRCLRM : Spare Register Clear Mask Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Spare register will be clear after TAMPER occurs

#1 : 1

Spare register will not be clear after TAMPER occurs

End of enumeration elements list.

SPRRWEN : Spare Register Enable Bit\nNote: When spare register is disabled, RTC_SPR0 ~ RTC_SPR4 cannot be accessed.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Spare register Disabled

#1 : 1

Spare register Enabled

End of enumeration elements list.

SPRCSTS : SPR Clear Flag \nThis bit indicates if the RTC_SPR0 ~RTC_SPR4 content is cleared when specify tamper event is detected.\nNote1: Write 1 to clear this bit.\nNote2: This bit keeps 1 when RTC_INTSTS[8] is not equal to 0.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Spare register content is not cleared

#1 : 1

Spare register content is cleared

End of enumeration elements list.


RTC_SPR0 (SPR0)

RTC Spare Register 0
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR0 RTC_SPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPARE

SPARE : Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.
bits : 0 - 31 (32 bit)
access : read-write


RTC_SPR1 (SPR1)

RTC Spare Register 1
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR1 RTC_SPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR2 (SPR2)

RTC Spare Register 2
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR2 RTC_SPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR3 (SPR3)

RTC Spare Register 3
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR3 RTC_SPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR4 (SPR4)

RTC Spare Register 4
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR4 RTC_SPR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_FREQADJ (FREQADJ)

RTC Frequency Compensation Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_FREQADJ RTC_FREQADJ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRACTION INTEGER

FRACTION : Fraction Part\nNote: Digit in FCR must be expressed as hexadecimal number.
bits : 0 - 5 (6 bit)
access : read-write

INTEGER : Integer Part
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

#00000 : 0

Integer part of detected value is 32752

#00001 : 1

Integer part of detected value is 32753

#00010 : 2

Integer part of detected value is 32754

#00011 : 3

Integer part of detected value is 32755

#00100 : 4

Integer part of detected value is 32756

#00101 : 5

Integer part of detected value is 32757

#00110 : 6

Integer part of detected value is 32758

#00111 : 7

Integer part of detected value is 32759

#01000 : 8

Integer part of detected value is 32760

#01001 : 9

Integer part of detected value is 32761

#01010 : 10

Integer part of detected value is 32762

#01011 : 11

Integer part of detected value is 32763

#01100 : 12

Integer part of detected value is 32764

#01101 : 13

Integer part of detected value is 32765

#01110 : 14

Integer part of detected value is 32766

#01111 : 15

Integer part of detected value is 32767

#10000 : 16

Integer part of detected value is 32768

#10001 : 17

Integer part of detected value is 32769

#10010 : 18

Integer part of detected value is 32770

#10011 : 19

Integer part of detected value is 32771

#10100 : 20

Integer part of detected value is 32772

#10101 : 21

Integer part of detected value is 32773

#10110 : 22

Integer part of detected value is 32774

#10111 : 23

Integer part of detected value is 32775

#11000 : 24

Integer part of detected value is 32776

#11001 : 25

Integer part of detected value is 32777

#11010 : 26

Integer part of detected value is 32778

#11011 : 27

Integer part of detected value is 32779

#11100 : 28

Integer part of detected value is 32780

#11101 : 29

Integer part of detected value is 32781

#11110 : 30

Integer part of detected value is 32782

#11111 : 31

Integer part of detected value is 32783

End of enumeration elements list.


RTC_TIME (TIME)

RTC Time Loading Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_TIME RTC_TIME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEC TENSEC MIN TENMIN HR TENHR

SEC : 1-Sec Time Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write

TENSEC : 10-Sec Time Digit (0~5)
bits : 4 - 6 (3 bit)
access : read-write

MIN : 1-Min Time Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write

TENMIN : 10-Min Time Digit (0~5)
bits : 12 - 14 (3 bit)
access : read-write

HR : 1-Hour Time Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write

TENHR : 10-Hour Time Digit (0~2)When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
bits : 20 - 21 (2 bit)
access : read-write



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