Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x120 Bytes (0x0)
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mem_usage : registers
protection : not protected
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mem_usage : registers
protection : not protected
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mem_usage : registers
protection : not protected
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protection : not protected
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mem_usage : registers
protection : not protected
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mem_usage : registers
protection : not protected
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mem_usage : registers
protection : not protected
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mem_usage : registers
protection : not protected
address_offset : 0xF8 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x110 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
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mem_usage : registers
protection : not protected
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mem_usage : registers
protection : not protected
address_offset : 0x304 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x31C Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
BPWM Control Register 0
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRLD0 : Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
bits : 0 - 0 (1 bit)
access : read-write
CTRLD1 : Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
bits : 1 - 1 (1 bit)
access : read-write
CTRLD2 : Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
bits : 2 - 2 (1 bit)
access : read-write
CTRLD3 : Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
bits : 3 - 3 (1 bit)
access : read-write
CTRLD4 : Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
bits : 4 - 4 (1 bit)
access : read-write
CTRLD5 : Center Re-load\nEach bit n controls the corresponding BPWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
bits : 5 - 5 (1 bit)
access : read-write
IMMLDEN0 : Immediately Load Enable Bit(s)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, CTRLDn will be invalid.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
End of enumeration elements list.
IMMLDEN1 : Immediately Load Enable Bit(s)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, CTRLDn will be invalid.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
End of enumeration elements list.
IMMLDEN2 : Immediately Load Enable Bit(s)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, CTRLDn will be invalid.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
End of enumeration elements list.
IMMLDEN3 : Immediately Load Enable Bit(s)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, CTRLDn will be invalid.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
End of enumeration elements list.
IMMLDEN4 : Immediately Load Enable Bit(s)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, CTRLDn will be invalid.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
End of enumeration elements list.
IMMLDEN5 : Immediately Load Enable Bit(s)\nEach bit n controls the corresponding BPWM channel n.\nNote: If IMMLDENn is enabled, CTRLDn will be invalid.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
End of enumeration elements list.
DBGHALT : ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode counter halt Disabled
#1 : 1
ICE debug mode counter halt Enabled
End of enumeration elements list.
DBGTRIOFF : ICE Debug Mode Acknowledge Disable (Write Protect)\nBPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode acknowledgement effects BPWM output
#1 : 1
ICE debug mode acknowledgement Disabled
End of enumeration elements list.
BPWM Clock Source Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECLKSRC0 : BPWM_CH01 External Clock Source Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
BPWMx_CLK, x denotes 0 or 1
#001 : 1
TIMER0 overflow
#010 : 2
TIMER1 overflow
#011 : 3
TIMER2 overflow
#100 : 4
TIMER3 overflow
End of enumeration elements list.
BPWM Synchronous Start Control Register
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSEN0 : BPWM Synchronous Start Function 0 Enable Bit\nWhen synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM synchronous start function Disabled
#1 : 1
BPWM synchronous start function Enabled
End of enumeration elements list.
SSRC : BPWM Synchronous Start Source Select
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Synchronous start source come from PWM0
#01 : 1
Synchronous start source come from PWM1
#10 : 2
Synchronous start source come from BPWM0
#11 : 3
Synchronous start source come from BPWM1
End of enumeration elements list.
BPWM Synchronous Start Trigger Register
address_offset : 0x114 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CNTSEN : BPWM Counter Synchronous Start Enable Bit (Write Only)\nBPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled.
bits : 0 - 0 (1 bit)
access : write-only
BPWM Status Register
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTMAX0 : Time-base Counter 0 Equal to 0xFFFF Latched Status
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The time-base counter never reached its maximum value 0xFFFF
#1 : 1
The time-base counter reached its maximum value.Note: This bit can be cleared by software write 1
End of enumeration elements list.
EADCTRG0 : EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No EADC start of conversion trigger event has occurred
#1 : 1
An EADC start of conversion trigger event has occurred
End of enumeration elements list.
EADCTRG1 : EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
No EADC start of conversion trigger event has occurred
#1 : 1
An EADC start of conversion trigger event has occurred
End of enumeration elements list.
EADCTRG2 : EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
No EADC start of conversion trigger event has occurred
#1 : 1
An EADC start of conversion trigger event has occurred
End of enumeration elements list.
EADCTRG3 : EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No EADC start of conversion trigger event has occurred
#1 : 1
An EADC start of conversion trigger event has occurred
End of enumeration elements list.
EADCTRG4 : EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
No EADC start of conversion trigger event has occurred
#1 : 1
An EADC start of conversion trigger event has occurred
End of enumeration elements list.
EADCTRG5 : EADC Start of Conversion Status\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit can be cleared by software write 1.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
No EADC start of conversion trigger event has occurred
#1 : 1
An EADC start of conversion trigger event has occurred
End of enumeration elements list.
BPWM Clock Prescale Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKPSC : BPWM Counter Clock Prescale \nThe clock of BPWM counter is decided by clock prescaler. Each BPWM pair share one BPWM counter clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1).
bits : 0 - 11 (12 bit)
access : read-write
BPWM Counter Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTEN0 : BPWM Counter 0 Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM Counter and clock prescaler stop running
#1 : 1
BPWM Counter and clock prescaler start running
End of enumeration elements list.
BPWM Capture Input Enable Register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPINEN0 : Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#1 : 1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN1 : Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#1 : 1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN2 : Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#1 : 1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN3 : Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#1 : 1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN4 : Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#1 : 1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN5 : Capture Input Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM Channel capture input path Disabled. The input of BPWM channel capture function is always regarded as 0
#1 : 1
BPWM Channel capture input path Enabled. The input of BPWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
BPWM Capture Control Register
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPEN0 : Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#1 : 1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPEN1 : Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#1 : 1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPEN2 : Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#1 : 1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPEN3 : Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#1 : 1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPEN4 : Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#1 : 1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPEN5 : Capture Function Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#1 : 1
Capture function Enabled. Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPINV0 : Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV1 : Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV2 : Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV3 : Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV4 : Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV5 : Capture Inverter Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
RCRLDEN0 : Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN1 : Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN2 : Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN3 : Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN4 : Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN5 : Rising Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
FCRLDEN0 : Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN1 : Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN2 : Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN3 : Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN4 : Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN5 : Falling Capture Reload Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
BPWM Capture Status Register
address_offset : 0x208 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRIFOV0 : Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
bits : 0 - 0 (1 bit)
access : read-only
CRIFOV1 : Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
bits : 1 - 1 (1 bit)
access : read-only
CRIFOV2 : Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
bits : 2 - 2 (1 bit)
access : read-only
CRIFOV3 : Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
bits : 3 - 3 (1 bit)
access : read-only
CRIFOV4 : Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
bits : 4 - 4 (1 bit)
access : read-only
CRIFOV5 : Capture Rising Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CAPRIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPRIF is cleared.
bits : 5 - 5 (1 bit)
access : read-only
CFIFOV0 : Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
bits : 8 - 8 (1 bit)
access : read-only
CFIFOV1 : Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
bits : 9 - 9 (1 bit)
access : read-only
CFIFOV2 : Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
bits : 10 - 10 (1 bit)
access : read-only
CFIFOV3 : Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
bits : 11 - 11 (1 bit)
access : read-only
CFIFOV4 : Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
bits : 12 - 12 (1 bit)
access : read-only
CFIFOV5 : Capture Falling Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CAPFIF is 1. Each bit n controls the corresponding BPWM channel n.\nNote: This bit will be cleared automatically when the corresponding CAPFIF is cleared.
bits : 13 - 13 (1 bit)
access : read-only
BPWM Rising Capture Data Register 0
address_offset : 0x20C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RCAPDAT : BPWM Rising Capture Data (Read Only)\nWhen rising capture condition happened, the BPWM counter value will be saved in this register.
bits : 0 - 15 (16 bit)
access : read-only
BPWM Falling Capture Data Register 0
address_offset : 0x210 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FCAPDAT : BPWM Falling Capture Data (Read Only)\nWhen falling capture condition happened, the BPWM counter value will be saved in this register.
bits : 0 - 15 (16 bit)
access : read-only
BPWM Rising Capture Data Register 1
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Falling Capture Data Register 1
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Rising Capture Data Register 2
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Falling Capture Data Register 2
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Rising Capture Data Register 3
address_offset : 0x224 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Falling Capture Data Register 3
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Rising Capture Data Register 4
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Falling Capture Data Register 4
address_offset : 0x230 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Rising Capture Data Register 5
address_offset : 0x234 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Falling Capture Data Register 5
address_offset : 0x238 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Clear Counter Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTCLR0 : Clear BPWM Counter Control Bit 0\nNote: It is automatically cleared by hardware.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit BPWM counter to 0000H
End of enumeration elements list.
BPWM Capture Interrupt Enable Register
address_offset : 0x250 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPRIENn : BPWM Capture Rising Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
Capture rising edge latch interrupt Disabled
1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPFIENn : BPWM Capture Falling Latch Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0 : 0
Capture falling edge latch interrupt Disabled
1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
BPWM Capture Interrupt Flag Register
address_offset : 0x254 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPRIF0 : BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CAPRIF1 : BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CAPRIF2 : BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CAPRIF3 : BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CAPRIF4 : BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CAPRIF5 : BPWM Capture Rising Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CAPFIF0 : BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CAPFIF1 : BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CAPFIF2 : BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CAPFIF3 : BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CAPFIF4 : BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CAPFIF5 : BPWM Capture Falling Latch Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nNote: This bit is cleared by writing 1 to it.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
BPWM Period Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : BPWM Period Register\nUp-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: \nIn this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.
bits : 0 - 15 (16 bit)
access : read-write
BPWM PERIOD Buffer
address_offset : 0x304 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PBUF : BPWM Period Buffer (Read Only)\nUsed as PERIOD active register.
bits : 0 - 15 (16 bit)
access : read-only
BPWM CMPDAT 0 Buffer
address_offset : 0x31C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMPBUF : BPWM Comparator Buffer (Read Only)\nUsed as CMP active register.
bits : 0 - 15 (16 bit)
access : read-only
BPWM CMPDAT 1 Buffer
address_offset : 0x320 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM CMPDAT 2 Buffer
address_offset : 0x324 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM CMPDAT 3 Buffer
address_offset : 0x328 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM CMPDAT 4 Buffer
address_offset : 0x32C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM CMPDAT 5 Buffer
address_offset : 0x330 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Control Register 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTTYPE0 : BPWM Counter Behavior Type 0\nEach bit n controls corresponding BPWM channel n.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supports in capture mode)
#01 : 1
Down count type (supports in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved.
End of enumeration elements list.
BPWM Comparator Register 0
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPDAT : BPWM Comparator Register\nCMPDAT use to compare with CNT to generate BPWM waveform, interrupt and trigger EADC.\nIn independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.
bits : 0 - 15 (16 bit)
access : read-write
BPWM Comparator Register 1
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Comparator Register 2
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Comparator Register 3
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Comparator Register 4
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Comparator Register 5
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPWM Counter Register
address_offset : 0x90 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : BPWM Data Register (Read Only)\nMonitor CNT to know the current value in 16-bit period counter.
bits : 0 - 15 (16 bit)
access : read-only
DIRF : BPWM Direction Indicator Flag (Read Only)
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Counter is down counting
#1 : 1
Counter is up counting
End of enumeration elements list.
BPWM Generation Register 0
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZPCTL0 : BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM zero point output Low
#10 : 2
BPWM zero point output High
#11 : 3
BPWM zero point output Toggle.Note: BPWM can control output level when BPWM counter counts to zero
End of enumeration elements list.
ZPCTL1 : BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM zero point output Low
#10 : 2
BPWM zero point output High
#11 : 3
BPWM zero point output Toggle.Note: BPWM can control output level when BPWM counter counts to zero
End of enumeration elements list.
ZPCTL2 : BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM zero point output Low
#10 : 2
BPWM zero point output High
#11 : 3
BPWM zero point output Toggle.Note: BPWM can control output level when BPWM counter counts to zero
End of enumeration elements list.
ZPCTL3 : BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM zero point output Low
#10 : 2
BPWM zero point output High
#11 : 3
BPWM zero point output Toggle.Note: BPWM can control output level when BPWM counter counts to zero
End of enumeration elements list.
ZPCTL4 : BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM zero point output Low
#10 : 2
BPWM zero point output High
#11 : 3
BPWM zero point output Toggle.Note: BPWM can control output level when BPWM counter counts to zero
End of enumeration elements list.
ZPCTL5 : BPWM Zero Point Control\nEach bit n controls the corresponding BPWM channel n.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM zero point output Low
#10 : 2
BPWM zero point output High
#11 : 3
BPWM zero point output Toggle.Note: BPWM can control output level when BPWM counter counts to zero
End of enumeration elements list.
PRDPCTL0 : BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM period (center) point output Low
#10 : 2
BPWM period (center) point output High
#11 : 3
BPWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL1 : BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM period (center) point output Low
#10 : 2
BPWM period (center) point output High
#11 : 3
BPWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL2 : BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM period (center) point output Low
#10 : 2
BPWM period (center) point output High
#11 : 3
BPWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL3 : BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM period (center) point output Low
#10 : 2
BPWM period (center) point output High
#11 : 3
BPWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL4 : BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM period (center) point output Low
#10 : 2
BPWM period (center) point output High
#11 : 3
BPWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL5 : BPWM Period (Center) Point Control\nEach bit n controls the corresponding BPWM channel n.\nBPWM can control output level when BPWM counter count to (PERIOD+1).\nNote: This bit is center point control when BPWM counter operating in up-down counter type.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM period (center) point output Low
#10 : 2
BPWM period (center) point output High
#11 : 3
BPWM period (center) point output Toggle
End of enumeration elements list.
BPWM Generation Register 1
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPUCTL0 : BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM compare up point output Low
#10 : 2
BPWM compare up point output High
#11 : 3
BPWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL1 : BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM compare up point output Low
#10 : 2
BPWM compare up point output High
#11 : 3
BPWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL2 : BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM compare up point output Low
#10 : 2
BPWM compare up point output High
#11 : 3
BPWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL3 : BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM compare up point output Low
#10 : 2
BPWM compare up point output High
#11 : 3
BPWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL4 : BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM compare up point output Low
#10 : 2
BPWM compare up point output High
#11 : 3
BPWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL5 : BPWM Compare Up Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter up counts to CMPDAT.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM compare up point output Low
#10 : 2
BPWM compare up point output High
#11 : 3
BPWM compare up point output Toggle
End of enumeration elements list.
CMPDCTL0 : BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM compare down point output Low
#10 : 2
BPWM compare down point output High
#11 : 3
BPWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL1 : BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM compare down point output Low
#10 : 2
BPWM compare down point output High
#11 : 3
BPWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL2 : BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM compare down point output Low
#10 : 2
BPWM compare down point output High
#11 : 3
BPWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL3 : BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM compare down point output Low
#10 : 2
BPWM compare down point output High
#11 : 3
BPWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL4 : BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM compare down point output Low
#10 : 2
BPWM compare down point output High
#11 : 3
BPWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL5 : BPWM Compare Down Point Control\nEach bit n controls the corresponding BPWM channel n.\nNote: BPWM can control output level when BPWM counter down counts to CMPDAT.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
BPWM compare down point output Low
#10 : 2
BPWM compare down point output High
#11 : 3
BPWM compare down point output Toggle
End of enumeration elements list.
BPWM Mask Enable Register
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSKEN0 : BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM output signal is non-masked
#1 : 1
BPWM output signal is masked and output MSKDATn data
End of enumeration elements list.
MSKEN1 : BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM output signal is non-masked
#1 : 1
BPWM output signal is masked and output MSKDATn data
End of enumeration elements list.
MSKEN2 : BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM output signal is non-masked
#1 : 1
BPWM output signal is masked and output MSKDATn data
End of enumeration elements list.
MSKEN3 : BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM output signal is non-masked
#1 : 1
BPWM output signal is masked and output MSKDATn data
End of enumeration elements list.
MSKEN4 : BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM output signal is non-masked
#1 : 1
BPWM output signal is masked and output MSKDATn data
End of enumeration elements list.
MSKEN5 : BPWM Mask Enable Bits\nEach bit n controls the corresponding BPWM channel n.\nThe BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM output signal is non-masked
#1 : 1
BPWM output signal is masked and output MSKDATn data
End of enumeration elements list.
BPWM Mask Data Register
address_offset : 0xBC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSKDAT0 : BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to BPWMn
#1 : 1
Output logic high to BPWMn
End of enumeration elements list.
MSKDAT1 : BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to BPWMn
#1 : 1
Output logic high to BPWMn
End of enumeration elements list.
MSKDAT2 : BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to BPWMn
#1 : 1
Output logic high to BPWMn
End of enumeration elements list.
MSKDAT3 : BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to BPWMn
#1 : 1
Output logic high to BPWMn
End of enumeration elements list.
MSKDAT4 : BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to BPWMn
#1 : 1
Output logic high to BPWMn
End of enumeration elements list.
MSKDAT5 : BPWM Mask Data Bit\nThis data bit control the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to BPWMn
#1 : 1
Output logic high to BPWMn
End of enumeration elements list.
BPWM Pin Polar Inverse Register
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PINV0 : BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM output pin polar inverse Disabled
#1 : 1
BPWM output pin polar inverse Enabled
End of enumeration elements list.
PINV1 : BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM output pin polar inverse Disabled
#1 : 1
BPWM output pin polar inverse Enabled
End of enumeration elements list.
PINV2 : BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM output pin polar inverse Disabled
#1 : 1
BPWM output pin polar inverse Enabled
End of enumeration elements list.
PINV3 : BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM output pin polar inverse Disabled
#1 : 1
BPWM output pin polar inverse Enabled
End of enumeration elements list.
PINV4 : BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM output pin polar inverse Disabled
#1 : 1
BPWM output pin polar inverse Enabled
End of enumeration elements list.
PINV5 : BPWM PIN Polar Inverse Control\nThe register controls polarity state of BPWM output pin. Each bit n controls the corresponding BPWM channel n.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM output pin polar inverse Disabled
#1 : 1
BPWM output pin polar inverse Enabled
End of enumeration elements list.
BPWM Output Enable Register
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POEN0 : BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM pin at tri-state
#1 : 1
BPWM pin in output mode
End of enumeration elements list.
POEN1 : BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM pin at tri-state
#1 : 1
BPWM pin in output mode
End of enumeration elements list.
POEN2 : BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM pin at tri-state
#1 : 1
BPWM pin in output mode
End of enumeration elements list.
POEN3 : BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM pin at tri-state
#1 : 1
BPWM pin in output mode
End of enumeration elements list.
POEN4 : BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM pin at tri-state
#1 : 1
BPWM pin in output mode
End of enumeration elements list.
POEN5 : BPWM Pin Output Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM pin at tri-state
#1 : 1
BPWM pin in output mode
End of enumeration elements list.
BPWM Interrupt Enable Register
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZIEN0 : BPWM Zero Point Interrupt 0 Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
PIEN0 : BPWM Period Point Interrupt 0 Enable Bit\nNote: When up-down counter type period point means center point.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
CMPUIEN0 : BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN1 : BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN2 : BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN3 : BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN4 : BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN5 : BPWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPDIEN0 : BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN1 : BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN2 : BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN3 : BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN4 : BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN5 : BPWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding BPWM channel n.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
BPWM Interrupt Flag Register
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZIF0 : BPWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches 0, software can write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
PIF0 : BPWM Period Point Interrupt Flag 0\nThis bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to 0.
bits : 8 - 8 (1 bit)
access : read-write
CMPUIF0 : BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
bits : 16 - 16 (1 bit)
access : read-write
CMPUIF1 : BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
bits : 17 - 17 (1 bit)
access : read-write
CMPUIF2 : BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
bits : 18 - 18 (1 bit)
access : read-write
CMPUIF3 : BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
bits : 19 - 19 (1 bit)
access : read-write
CMPUIF4 : BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
bits : 20 - 20 (1 bit)
access : read-write
CMPUIF5 : BPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding BPWM channel n.\nNote: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
bits : 21 - 21 (1 bit)
access : read-write
CMPDIF0 : BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
bits : 24 - 24 (1 bit)
access : read-write
CMPDIF1 : BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
bits : 25 - 25 (1 bit)
access : read-write
CMPDIF2 : BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
bits : 26 - 26 (1 bit)
access : read-write
CMPDIF3 : BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
bits : 27 - 27 (1 bit)
access : read-write
CMPDIF4 : BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
bits : 28 - 28 (1 bit)
access : read-write
CMPDIF5 : BPWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding BPWM channel n.\nFlag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
bits : 29 - 29 (1 bit)
access : read-write
BPWM Trigger EADC Source Select Register 0
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL0 : BPWM_CH0 Trigger EADC Source Select\nOthers reserved
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
BPWM_CH0 zero point
#0001 : 1
BPWM_CH0 period point
#0010 : 2
BPWM_CH0 zero or period point
#0011 : 3
BPWM_CH0 up-count CMPDAT point
#0100 : 4
BPWM_CH0 down-count CMPDAT point
#0101 : 5
Reserved.
#0110 : 6
Reserved.
#0111 : 7
Reserved.
#1000 : 8
BPWM_CH1 up-count CMPDAT point
#1001 : 9
BPWM_CH1 down-count CMPDAT point
End of enumeration elements list.
TRGEN0 : BPWM_CH0 Trigger EADC Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM Channel 0 Trigger EADC function Disabled
#1 : 1
BPWM Channel 0 Trigger EADC function Enabled
End of enumeration elements list.
TRGSEL1 : BPWM_CH1 Trigger EADC Source Select\nOthers reserved
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
BPWM_CH0 zero point
#0001 : 1
BPWM_CH0 period point
#0010 : 2
BPWM_CH0 zero or period point
#0011 : 3
BPWM_CH0 up-count CMPDAT point
#0100 : 4
BPWM_CH0 down-count CMPDAT point
#0101 : 5
Reserved.
#0110 : 6
Reserved.
#0111 : 7
Reserved.
#1000 : 8
BPWM_CH1 up-count CMPDAT point
#1001 : 9
BPWM_CH1 down-count CMPDAT point
End of enumeration elements list.
TRGEN1 : BPWM_CH1 Trigger EADC Enable Bit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM Channel 1 Trigger EADC function Disabled
#1 : 1
BPWM Channel 1 Trigger EADC function Enabled
End of enumeration elements list.
TRGSEL2 : BPWM_CH2 Trigger EADC Source Select\nOthers reserved
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
BPWM_CH2 zero point
#0001 : 1
BPWM_CH2 period point
#0010 : 2
BPWM_CH2 zero or period point
#0011 : 3
BPWM_CH2 up-count CMPDAT point
#0100 : 4
BPWM_CH2 down-count CMPDAT point
#0101 : 5
Reserved.
#0110 : 6
Reserved.
#0111 : 7
Reserved.
#1000 : 8
BPWM_CH3 up-count CMPDAT point
#1001 : 9
BPWM_CH3 down-count CMPDAT point
End of enumeration elements list.
TRGEN2 : BPWM_CH2 Trigger EADC Enable Bit
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM Channel 2 Trigger EADC function Disabled
#1 : 1
BPWM Channel 2 Trigger EADC function Enabled
End of enumeration elements list.
TRGSEL3 : BPWM_CH3 Trigger EADC Source Select\nOthers reserved.
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
BPWM_CH2 zero point
#0001 : 1
BPWM_CH2 period point
#0010 : 2
BPWM_CH2 zero or period point
#0011 : 3
BPWM_CH2 up-count CMPDAT point
#0100 : 4
BPWM_CH2 down-count CMPDAT point
#0101 : 5
Reserved.
#0110 : 6
Reserved.
#0111 : 7
Reserved.
#1000 : 8
BPWM_CH3 up-count CMPDAT point
#1001 : 9
BPWM_CH3 down-count CMPDAT point
End of enumeration elements list.
TRGEN3 : BPWM_CH3 Trigger EADC Enable Bit
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM Channel 3 Trigger EADC function Disabled
#1 : 1
BPWM Channel 3 Trigger EADC function Enabled
End of enumeration elements list.
BPWM Trigger EADC Source Select Register 1
address_offset : 0xFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL4 : BPWM_CH4 Trigger EADC Source Select\nOthers reserved
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
BPWM_CH4 zero point
#0001 : 1
BPWM_CH4 period point
#0010 : 2
BPWM_CH4 zero or period point
#0011 : 3
BPWM_CH4 up-count CMPDAT point
#0100 : 4
BPWM_CH4 down-count CMPDAT point
#0101 : 5
Reserved.
#0110 : 6
Reserved.
#0111 : 7
Reserved.
#1000 : 8
BPWM_CH5 up-count CMPDAT point
#1001 : 9
BPWM_CH5 down-count CMPDAT point
End of enumeration elements list.
TRGEN4 : BPWM_CH4 Trigger EADC Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM Channel 4 Trigger EADC function Disabled
#1 : 1
BPWM Channel 4 Trigger EADC function Enabled
End of enumeration elements list.
TRGSEL5 : BPWM_CH5 Trigger EADC Source Select\nOthers reserved
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
BPWM_CH4 zero point
#0001 : 1
BPWM_CH4 period point
#0010 : 2
BPWM_CH4 zero or period point
#0011 : 3
BPWM_CH4 up-count CMPDAT point
#0100 : 4
BPWM_CH4 down-count CMPDAT point
#0101 : 5
Reserved.
#0110 : 6
Reserved.
#0111 : 7
Reserved.
#1000 : 8
BPWM_CH5 up-count CMPDAT point
#1001 : 9
BPWM_CH5 down-count CMPDAT point
End of enumeration elements list.
TRGEN5 : BPWM_CH5 Trigger EADC Enable Bit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM Channel 5 Trigger EADC function Disabled
#1 : 1
BPWM Channel 5 Trigger EADC function Enabled
End of enumeration elements list.
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