Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x120 Bytes (0x0)
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mem_usage : registers
protection : not protected
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size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
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mem_usage : registers
protection : not protected
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size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
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size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x70 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
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size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
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size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xF8 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x110 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x250 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x304 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x31C Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xB0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
size : 0x4C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x314 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
PWM Control Register 0
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRLDn : Center Load Enable Bits\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
bits : 0 - 0 (1 bit)
access : read-write
IMMLDENn : Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT
End of enumeration elements list.
DBGHALT : ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode counter halt Disable
#1 : 1
ICE debug mode counter halt Enable
End of enumeration elements list.
DBGTRIOFF : ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode acknowledgement effects PWM output
#1 : 1
ICE debug mode acknowledgement disabled
End of enumeration elements list.
PWM Clock Source Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECLKSRC0 : PWM_CH01 External Clock Source Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
PWMx_CLK, x denotes 0 or 1
#001 : 1
TIMER0 overflow
#010 : 2
TIMER1 overflow
#011 : 3
TIMER2 overflow
#100 : 4
TIMER3 overflow
End of enumeration elements list.
ECLKSRC2 : PWM_CH23 External Clock Source Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
PWMx_CLK, x denotes 0 or 1
#001 : 1
TIMER0 overflow
#010 : 2
TIMER1 overflow
#011 : 3
TIMER2 overflow
#100 : 4
TIMER3 overflow
End of enumeration elements list.
ECLKSRC4 : PWM_CH45 External Clock Source Select
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
PWMx_CLK, x denotes 0 or 1
#001 : 1
TIMER0 overflow
#010 : 2
TIMER1 overflow
#011 : 3
TIMER2 overflow
#100 : 4
TIMER3 overflow
End of enumeration elements list.
PWM Synchronous Start Control Register
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSEN0 : PWM Synchronous Start Function Enable Bit 0\nWhen synchronous start function is enabled, the PWM_CH0 counter enable bit (CNTEN0) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM synchronous start function Disabled
#1 : 1
PWM synchronous start function Enabled
End of enumeration elements list.
SSEN2 : PWM Synchronous Start Function Enable Bit 2\nWhen synchronous start function is enabled, the PWM_CH2 counter enable bit (CNTEN2) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM synchronous start function Disabled
#1 : 1
PWM synchronous start function Enabled
End of enumeration elements list.
SSEN4 : PWM Synchronous Start Function Enable Bit 4\nWhen synchronous start function is enabled, the PWM_CH4 counter enable bit (CNTEN4) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM synchronous start function Disabled
#1 : 1
PWM synchronous start function Enabled
End of enumeration elements list.
SSRC : PWM Synchronous Start Source Select Bits
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Synchronous start source come from PWM0
#01 : 1
Synchronous start source come from PWM1
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
PWM Synchronous Start Trigger Register
address_offset : 0x114 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CNTSEN : PWM Counter Synchronous Start Enable (Write Only)\nPWM counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled.
bits : 0 - 0 (1 bit)
access : write-only
PWM Status Register
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTMAX0 : Time-base Counter 0 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
indicates the time-base counter never reached its maximum value 0xFFFF
#1 : 1
indicates the time-base counter reached its maximum value
End of enumeration elements list.
CNTMAX2 : Time-base Counter 2 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
indicates the time-base counter never reached its maximum value 0xFFFF
#1 : 1
indicates the time-base counter reached its maximum value
End of enumeration elements list.
CNTMAX4 : Time-base Counter 4 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The time-base counter never reached its maximum value 0xFFFF
#1 : 1
The time-base counter reached its maximum value
End of enumeration elements list.
ADCTRG0 : ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no ADC start of conversion trigger event has occurred
#1 : 1
An ADC start of conversion trigger event has occurred
End of enumeration elements list.
ADCTRG1 : ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no ADC start of conversion trigger event has occurred
#1 : 1
An ADC start of conversion trigger event has occurred
End of enumeration elements list.
ADCTRG2 : ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no ADC start of conversion trigger event has occurred
#1 : 1
An ADC start of conversion trigger event has occurred
End of enumeration elements list.
ADCTRG3 : ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no ADC start of conversion trigger event has occurred
#1 : 1
An ADC start of conversion trigger event has occurred
End of enumeration elements list.
ADCTRG4 : ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no ADC start of conversion trigger event has occurred
#1 : 1
An ADC start of conversion trigger event has occurred
End of enumeration elements list.
ADCTRG5 : ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates no ADC start of conversion trigger event has occurred
#1 : 1
An ADC start of conversion trigger event has occurred
End of enumeration elements list.
PWM Clock Prescale Register 0/1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKPSC : PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1).
bits : 0 - 11 (12 bit)
access : read-write
PWM Clock Prescale Register 2/3
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Clock Prescale Register 4/5
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTEN0 : PWM Counter Enable Bit 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Counter and clock prescaler Stop Running
#1 : 1
PWM Counter and clock prescaler Start Running
End of enumeration elements list.
CNTEN2 : PWM Counter Enable Bit 2
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Counter and clock prescaler Stop Running
#1 : 1
PWM Counter and clock prescaler Start Running
End of enumeration elements list.
CNTEN4 : PWM Counter Enable Bit 4
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Counter and clock prescaler Stop Running
#1 : 1
PWM Counter and clock prescaler Start Running
End of enumeration elements list.
PWM Capture Input Enable Register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPINEN0 : Capture Input Enable Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#1 : 1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN1 : Capture Input Enable Bits
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#1 : 1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN2 : Capture Input Enable Bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#1 : 1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN3 : Capture Input Enable Bits
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#1 : 1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN4 : Capture Input Enable Bits
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#1 : 1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN5 : Capture Input Enable Bits
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
#1 : 1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
PWM Capture Control Register
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPEN0 : Capture Function Enable Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#1 : 1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPEN1 : Capture Function Enable Bits
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#1 : 1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPEN2 : Capture Function Enable Bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#1 : 1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPEN3 : Capture Function Enable Bits
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#1 : 1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPEN4 : Capture Function Enable Bits
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#1 : 1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPEN5 : Capture Function Enable Bits
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated
#1 : 1
Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPINV0 : Capture Inverter Enable Bits
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV1 : Capture Inverter Enable Bits
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV2 : Capture Inverter Enable Bits
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV3 : Capture Inverter Enable Bits
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV4 : Capture Inverter Enable Bits
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV5 : Capture Inverter Enable Bits
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
RCRLDEN0 : Rising Capture Reload Enable Bits
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN1 : Rising Capture Reload Enable Bits
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN2 : Rising Capture Reload Enable Bits
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN3 : Rising Capture Reload Enable Bits
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN4 : Rising Capture Reload Enable Bits
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN5 : Rising Capture Reload Enable Bits
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
FCRLDEN0 : Falling Capture Reload Enable Bits
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN1 : Falling Capture Reload Enable Bits
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN2 : Falling Capture Reload Enable Bits
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN3 : Falling Capture Reload Enable Bits
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN4 : Falling Capture Reload Enable Bits
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN5 : Falling Capture Reload Enable Bits
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
PWM Capture Status Register
address_offset : 0x208 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRLIFOV0 : Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
bits : 0 - 0 (1 bit)
access : read-only
CRLIFOV1 : Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
bits : 1 - 1 (1 bit)
access : read-only
CRLIFOV2 : Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
bits : 2 - 2 (1 bit)
access : read-only
CRLIFOV3 : Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
bits : 3 - 3 (1 bit)
access : read-only
CRLIFOV4 : Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
bits : 4 - 4 (1 bit)
access : read-only
CRLIFOV5 : Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF.
bits : 5 - 5 (1 bit)
access : read-only
CFLIFOV0 : Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
bits : 8 - 8 (1 bit)
access : read-only
CFLIFOV1 : Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
bits : 9 - 9 (1 bit)
access : read-only
CFLIFOV2 : Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
bits : 10 - 10 (1 bit)
access : read-only
CFLIFOV3 : Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
bits : 11 - 11 (1 bit)
access : read-only
CFLIFOV4 : Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
bits : 12 - 12 (1 bit)
access : read-only
CFLIFOV5 : Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF.
bits : 13 - 13 (1 bit)
access : read-only
PWM Rising Capture Data Register 0
address_offset : 0x20C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RCAPDAT : PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the PWM counter value will be saved in this register.
bits : 0 - 15 (16 bit)
access : read-only
PWM Falling Capture Data Register 0
address_offset : 0x210 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FCAPDAT : PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the PWM counter value will be saved in this register.
bits : 0 - 15 (16 bit)
access : read-only
PWM Rising Capture Data Register 1
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Falling Capture Data Register 1
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Rising Capture Data Register 2
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Falling Capture Data Register 2
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Rising Capture Data Register 3
address_offset : 0x224 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Falling Capture Data Register 3
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Rising Capture Data Register 4
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Falling Capture Data Register 4
address_offset : 0x230 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Rising Capture Data Register 5
address_offset : 0x234 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Falling Capture Data Register 5
address_offset : 0x238 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM PDMA Control Register
address_offset : 0x23C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN0_1 : Channel 0/1 PDMA Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 0/1 PDMA function Disabled
#1 : 1
Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory
End of enumeration elements list.
CAPMOD0_1 : Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved.
#01 : 1
PWM_RCAPDAT0/1
#10 : 2
PWM_FCAPDAT0/1
#11 : 3
Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1
End of enumeration elements list.
CAPORD0_1 : Capture Channel 0/1 Rising/Falling Order
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_FCAPDAT0/1 is the first captured data to memory
#1 : 1
PWM_RCAPDAT0/1 is the first captured data to memory
End of enumeration elements list.
CHSEL0_1 : Select Channel 0/1 to Do PDMA Transfer
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel0
#1 : 1
Channel1
End of enumeration elements list.
CHEN2_3 : Channel 2/3 PDMA Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 2/3 PDMA function Disabled
#1 : 1
Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory
End of enumeration elements list.
CAPMOD2_3 : Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved.
#01 : 1
PWM_RCAPDAT2/3
#10 : 2
PWM_FCAPDAT2/3
#11 : 3
Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3
End of enumeration elements list.
CAPORD2_3 : Capture Channel 2/3 Rising/Falling Order
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_FCAPDAT2/3 is the first captured data to memory
#1 : 1
PWM_RCAPDAT2/3 is the first captured data to memory
End of enumeration elements list.
CHSEL2_3 : Select Channel 2/3 to Do PDMA Transfer
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel2
#1 : 1
Channel3
End of enumeration elements list.
CHEN4_5 : Channel 4/5 PDMA Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 4/5 PDMA function Disabled
#1 : 1
Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory
End of enumeration elements list.
CAPMOD4_5 : Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved.
#01 : 1
PWM_RCAPDAT4/5
#10 : 2
PWM_FCAPDAT4/5
#11 : 3
Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5
End of enumeration elements list.
CAPORD4_5 : Capture Channel 4/5 Rising/Falling Order
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_FCAPDAT4/5 is the first captured data to memory
#1 : 1
PWM_RCAPDAT4/5 is the first captured data to memory
End of enumeration elements list.
CHSEL4_5 : Select Channel 4/5 to Do PDMA Transfer
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel4
#1 : 1
Channel5
End of enumeration elements list.
PWM Clear Counter Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTCLR0 : Clear PWM Counter Control Bit 0\nIt is automatically cleared by hardware.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit PWM counter to 0000H
End of enumeration elements list.
CNTCLR2 : Clear PWM Counter Control Bit 2\nIt is automatically cleared by hardware.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit PWM counter to 0000H
End of enumeration elements list.
CNTCLR4 : Clear PWM Counter Control Bit 4\nIt is automatically cleared by hardware.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit PWM counter to 0000H
End of enumeration elements list.
PWM Capture Channel 01 PDMA Register
address_offset : 0x240 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPBUF : PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
bits : 0 - 15 (16 bit)
access : read-only
PWM Capture Channel 23 PDMA Register
address_offset : 0x244 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Capture Channel 45 PDMA Register
address_offset : 0x248 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Capture Interrupt Enable Register
address_offset : 0x250 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPRIEN0 : PWM Capture Rising Latch Interrupt Enable Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPRIEN1 : PWM Capture Rising Latch Interrupt Enable Bits
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPRIEN2 : PWM Capture Rising Latch Interrupt Enable Bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPRIEN3 : PWM Capture Rising Latch Interrupt Enable Bits
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPRIEN4 : PWM Capture Rising Latch Interrupt Enable Bits
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPRIEN5 : PWM Capture Rising Latch Interrupt Enable Bits
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN0 : PWM Capture Falling Latch Interrupt Enable Bits
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN1 : PWM Capture Falling Latch Interrupt Enable Bits
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN2 : PWM Capture Falling Latch Interrupt Enable Bits
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN3 : PWM Capture Falling Latch Interrupt Enable Bits
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN4 : PWM Capture Falling Latch Interrupt Enable Bits
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN5 : PWM Capture Falling Latch Interrupt Enable Bits
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
PWM Capture Interrupt Flag Register
address_offset : 0x254 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRLIF0 : PWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CRLIF1 : PWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CRLIF2 : PWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CRLIF3 : PWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CRLIF4 : PWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CRLIF5 : PWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CRLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF0 : PWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF1 : PWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF2 : PWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF3 : PWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF4 : PWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF5 : PWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
PWM Period Register 0
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : PWM Period Register\nUp-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD.
bits : 0 - 15 (16 bit)
access : read-write
PWM PERIOD0 Buffer
address_offset : 0x304 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PBUF : PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register.
bits : 0 - 15 (16 bit)
access : read-only
PWM PERIOD2 Buffer
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM PERIOD4 Buffer
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM CMPDAT0 Buffer
address_offset : 0x31C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMPBUF : PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register.
bits : 0 - 15 (16 bit)
access : read-only
PWM CMPDAT1 Buffer
address_offset : 0x320 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM CMPDAT2 Buffer
address_offset : 0x324 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM CMPDAT3 Buffer
address_offset : 0x328 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM CMPDAT4 Buffer
address_offset : 0x32C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM CMPDAT5 Buffer
address_offset : 0x330 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Period Register 2
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Control Register 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTTYPE0 : PWM Counter Behavior Type 0\nThe two bits control channel1 and channel0
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supported in capture mode)
#01 : 1
Down count type (supported in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved.
End of enumeration elements list.
CNTTYPE2 : PWM Counter Behavior Type 2\nThe two bits control channel3 and channel2
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supported in capture mode)
#01 : 1
Down count type (supported in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved.
End of enumeration elements list.
CNTTYPE4 : PWM Counter Behavior Type 4\nThe two bits control channel5 and channel4
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supported in capture mode)
#01 : 1
Down count type (supported in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved.
End of enumeration elements list.
OUTMODEn : PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function, these bits must all set to the same mode.
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : 0
PWM independent mode
1 : 1
PWM complementary mode
End of enumeration elements list.
PWM Period Register 4
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 0
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP : PWM Comparator Register\nCMP is used to compare with CNTR to generate PWM waveform, interrupt and trigger ADC.\nIn independent mode, PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode, PWM_CMPDAT0, 2, 4 denote as first compared point, and PWM_CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
bits : 0 - 15 (16 bit)
access : read-write
PWM Comparator Register 1
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 2
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 3
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 4
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 5
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Dead-time Control Register 0/1
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCNT : Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 11 (12 bit)
access : read-write
DTEN : Enable Dead-time Insertion for PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-time insertion Disabled on the pin pair
#1 : 1
Dead-time insertion Enabled on the pin pair
End of enumeration elements list.
DTCKSEL : Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to REGWRPROT register.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-time clock source from PWM_CLK
#1 : 1
Dead-time clock source from prescaler output
End of enumeration elements list.
PWM Dead-time Control Register 2/3
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Dead-time Control Register 4/5
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Register 0
address_offset : 0x90 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : PWM Data Register (Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter.
bits : 0 - 15 (16 bit)
access : read-only
DIRF : PWM Direction Indicator Flag (Read Only)
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Counter is counting down
#1 : 1
Counter is counting up
End of enumeration elements list.
PWM Counter Register 2
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Register 4
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Generation Register 0
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZPCTL0 : PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM zero point output Low
#10 : 2
PWM zero point output High
#11 : 3
PWM zero point output Toggle
End of enumeration elements list.
ZPCTL1 : PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM zero point output Low
#10 : 2
PWM zero point output High
#11 : 3
PWM zero point output Toggle
End of enumeration elements list.
ZPCTL2 : PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM zero point output Low
#10 : 2
PWM zero point output High
#11 : 3
PWM zero point output Toggle
End of enumeration elements list.
ZPCTL3 : PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM zero point output Low
#10 : 2
PWM zero point output High
#11 : 3
PWM zero point output Toggle
End of enumeration elements list.
ZPCTL4 : PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM zero point output Low
#10 : 2
PWM zero point output High
#11 : 3
PWM zero point output Toggle
End of enumeration elements list.
ZPCTL5 : PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM zero point output Low
#10 : 2
PWM zero point output High
#11 : 3
PWM zero point output Toggle
End of enumeration elements list.
PRDPCTL0 : PWM Period (Center) Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM period (center) point output Low
#10 : 2
PWM period (center) point output High
#11 : 3
PWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL1 : PWM Period (Center) Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM period (center) point output Low
#10 : 2
PWM period (center) point output High
#11 : 3
PWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL2 : PWM Period (Center) Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM period (center) point output Low
#10 : 2
PWM period (center) point output High
#11 : 3
PWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL3 : PWM Period (Center) Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM period (center) point output Low
#10 : 2
PWM period (center) point output High
#11 : 3
PWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL4 : PWM Period (Center) Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM period (center) point output Low
#10 : 2
PWM period (center) point output High
#11 : 3
PWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL5 : PWM Period (Center) Point Control\nNote1: PWM can control output level when PWM counter counts to (PERIODn+1).\nNote2: This bit is center point control when PWM counter operating in up-down counter type.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM period (center) point output Low
#10 : 2
PWM period (center) point output High
#11 : 3
PWM period (center) point output Toggle
End of enumeration elements list.
PWM Generation Register 1
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPUCTL0 : PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare up point output Low
#10 : 2
PWM compare up point output High
#11 : 3
PWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL1 : PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare up point output Low
#10 : 2
PWM compare up point output High
#11 : 3
PWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL2 : PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare up point output Low
#10 : 2
PWM compare up point output High
#11 : 3
PWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL3 : PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare up point output Low
#10 : 2
PWM compare up point output High
#11 : 3
PWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL4 : PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare up point output Low
#10 : 2
PWM compare up point output High
#11 : 3
PWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL5 : PWM Compare Up Point Control\nNote1: PWM can control output level when PWM counter counts up to CMPDAT.\nNote2: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare up point output Low
#10 : 2
PWM compare up point output High
#11 : 3
PWM compare up point output Toggle
End of enumeration elements list.
CMPDCTL0 : PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare down point output Low
#10 : 2
PWM compare down point output High
#11 : 3
PWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL1 : PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare down point output Low
#10 : 2
PWM compare down point output High
#11 : 3
PWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL2 : PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare down point output Low
#10 : 2
PWM compare down point output High
#11 : 3
PWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL3 : PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare down point output Low
#10 : 2
PWM compare down point output High
#11 : 3
PWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL4 : PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare down point output Low
#10 : 2
PWM compare down point output High
#11 : 3
PWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL5 : PWM Compare Down Point Control\nNote1: PWM can control output level when PWM counter counts down to CMPDAT.\nNote2: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
PWM compare down point output Low
#10 : 2
PWM compare down point output High
#11 : 3
PWM compare down point output Toggle
End of enumeration elements list.
PWM Mask Enable Register
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSKEN0 : PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output signal is non-masked
#1 : 1
PWM output signal is masked and output MSKDATn data
End of enumeration elements list.
MSKEN1 : PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output signal is non-masked
#1 : 1
PWM output signal is masked and output MSKDATn data
End of enumeration elements list.
MSKEN2 : PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output signal is non-masked
#1 : 1
PWM output signal is masked and output MSKDATn data
End of enumeration elements list.
MSKEN3 : PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output signal is non-masked
#1 : 1
PWM output signal is masked and output MSKDATn data
End of enumeration elements list.
MSKEN4 : PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output signal is non-masked
#1 : 1
PWM output signal is masked and output MSKDATn data
End of enumeration elements list.
MSKEN5 : PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output signal is non-masked
#1 : 1
PWM output signal is masked and output MSKDATn data
End of enumeration elements list.
PWM Mask Data Register
address_offset : 0xBC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSKDAT0 : PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to PWM channel n
#1 : 1
Output logic high to PWM channel n
End of enumeration elements list.
MSKDAT1 : PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to PWM channel n
#1 : 1
Output logic high to PWM channel n
End of enumeration elements list.
MSKDAT2 : PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to PWM channel n
#1 : 1
Output logic high to PWM channel n
End of enumeration elements list.
MSKDAT3 : PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to PWM channel n
#1 : 1
Output logic high to PWM channel n
End of enumeration elements list.
MSKDAT4 : PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to PWM channel n
#1 : 1
Output logic high to PWM channel n
End of enumeration elements list.
MSKDAT5 : PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to PWM channel n
#1 : 1
Output logic high to PWM channel n
End of enumeration elements list.
PWM Brake Noise Filter Register
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRK0NFEN : PWM Brake 0 Noise Filter Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter of PWM Brake 0 Disabled
#1 : 1
Noise filter of PWM Brake 0 Enabled
End of enumeration elements list.
BRK0NFSEL : Brake 0 Edge Detector Filter Clock Selection
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
#000 : 0
Filter clock = HCLK
#001 : 1
Filter clock = HCLK/2
#010 : 2
Filter clock = HCLK/4
#011 : 3
Filter clock = HCLK/8
#100 : 4
Filter clock = HCLK/16
#101 : 5
Filter clock = HCLK/32
#110 : 6
Filter clock = HCLK/64
#111 : 7
Filter clock = HCLK/128
End of enumeration elements list.
BRK0NFCNT : Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT.
bits : 4 - 6 (3 bit)
access : read-write
BRK0PINV : Brake 0 Pin Inverse
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The state of pin PWMx_BRAKE0 is passed to the negative edge detector
#1 : 1
The inversed state of pin PWMx_BRAKE10 is passed to the negative edge detector
End of enumeration elements list.
BRK1FEN : PWM Brake 1 Noise Filter Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter of PWM Brake 1 Disabled
#1 : 1
Noise filter of PWM Brake 1 Enabled
End of enumeration elements list.
BRK1NFSEL : Brake 1 Edge Detector Filter Clock Selection
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
#000 : 0
Filter clock = HCLK
#001 : 1
Filter clock = HCLK/2
#010 : 2
Filter clock = HCLK/4
#011 : 3
Filter clock = HCLK/8
#100 : 4
Filter clock = HCLK/16
#101 : 5
Filter clock = HCLK/32
#110 : 6
Filter clock = HCLK/64
#111 : 7
Filter clock = HCLK/128
End of enumeration elements list.
BRK1FCNT : Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
bits : 12 - 14 (3 bit)
access : read-write
BRK1PINV : Brake 1 Pin Inverse
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The state of pin PWMx_BRAKE1 is passed to the negative edge detector
#1 : 1
The inversed state of pin PWMx_BRAKE1 is passed to the negative edge detector
End of enumeration elements list.
BK0SRC : Brake 0 Pin Source Select\nFor PWM0 setting:
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake 0 pin source come from PWM0_BRAKE0.\nBrake 0 pin source come from PWM1_BRAKE0
#1 : 1
Brake 0 pin source come from PWM1_BRAKE0.\nBrake 0 pin source come from PWM0_BRAKE0
End of enumeration elements list.
BK1SRC : Brake 1 Pin Source Select\nFor PWM0 setting:
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake 1 pin source come from PWM0_BRAKE1.\nBrake 1 pin source come from PWM1_BRAKE1
#1 : 1
Brake 1 pin source come from PWM1_BRAKE1.\nBrake 1 pin source come from PWM0_BRAKE1
End of enumeration elements list.
PWM System Fail Brake Control Register
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSSBRKEN : Clock Security System Detection Trigger PWM Brake Function 0 Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function triggered by CSS detection Disabled
#1 : 1
Brake Function triggered by CSS detection Enabled
End of enumeration elements list.
BODBRKEN : Brown-out Detection Trigger PWM Brake Function 0 Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function triggered by BOD Disabled
#1 : 1
Brake Function triggered by BOD Enabled
End of enumeration elements list.
CORBRKEN : Core Lockup Detection Trigger PWM Brake Function 0 Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function triggered by Core lockup detection Disabled
#1 : 1
Brake Function triggered by Core lockup detection Enabled
End of enumeration elements list.
PWM Brake Edge Detect Control Register 0/1
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPO0EBEN : Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP0_O as edge-detect brake source Disabled
#1 : 1
ACMP0_O as edge-detect brake source Enabled
End of enumeration elements list.
CPO1EBEN : Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP1_O as edge-detect brake source Disabled
#1 : 1
ACMP1_O as edge-detect brake source Enabled
End of enumeration elements list.
BRKP0EEN : Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
BKP0 pin as edge-detect brake source Disabled
#1 : 1
BKP0 pin as edge-detect brake source Enabled
End of enumeration elements list.
BRKP1EEN : Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
BKP1 pin as edge-detect brake source Disabled
#1 : 1
BKP1 pin as edge-detect brake source Enabled
End of enumeration elements list.
SYSEBEN : Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
System Fail condition as edge-detect brake source Disabled
#1 : 1
System Fail condition as edge-detect brake source Enabled
End of enumeration elements list.
CPO0LBEN : Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP0_O as level-detect brake source Disabled
#1 : 1
ACMP0_O as level-detect brake source Enabled
End of enumeration elements list.
CPO1LBEN : Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP1_O as level-detect brake source Disabled
#1 : 1
ACMP1_O as level-detect brake source Enabled
End of enumeration elements list.
BRKP0LEN : Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_BRAKE0 pin as level-detect brake source Disabled
#1 : 1
PWMx_BRAKE0 pin as level-detect brake source Enabled
End of enumeration elements list.
BRKP1LEN : Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx_BRAKE1 pin as level-detect brake source Disabled
#1 : 1
PWMx_BRAKE1 pin as level-detect brake source Enabled
End of enumeration elements list.
SYSLBEN : Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
System Fail condition as level-detect brake source Disabled
#1 : 1
System Fail condition as level-detect brake source Enabled
End of enumeration elements list.
BRKAEVEN : PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
PWM even channel level-detect brake function not affect channel output
#01 : 1
PWM even channel output tri-state when level-detect brake happened
#10 : 2
PWM even channel output low level when level-detect brake happened
#11 : 3
PWM even channel output high level when level-detect brake happened
End of enumeration elements list.
BRKAODD : PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected. Refer to SYS_REGLCTL register.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
PWM odd channel level-detect brake function not affect channel output
#01 : 1
PWM odd channel output tri-state when level-detect brake happened
#10 : 2
PWM odd channel output low level when level-detect brake happened
#11 : 3
PWM odd channel output high level when level-detect brake happened
End of enumeration elements list.
PWM Brake Edge Detect Control Register 2/3
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Brake Edge Detect Control Register 4/5
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Pin Polar Inverse Register
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PINV0 : PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output polar inverse Disabled
#1 : 1
PWM output polar inverse Enabled
End of enumeration elements list.
PINV1 : PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output polar inverse Disabled
#1 : 1
PWM output polar inverse Enabled
End of enumeration elements list.
PINV2 : PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output polar inverse Disabled
#1 : 1
PWM output polar inverse Enabled
End of enumeration elements list.
PINV3 : PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output polar inverse Disabled
#1 : 1
PWM output polar inverse Enabled
End of enumeration elements list.
PINV4 : PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output polar inverse Disabled
#1 : 1
PWM output polar inverse Enabled
End of enumeration elements list.
PINV5 : PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output polar inverse Disabled
#1 : 1
PWM output polar inverse Enabled
End of enumeration elements list.
PWM Output Enable Register
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POEN0 : PWM Pin Output Enable Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM pin at tri-state
#1 : 1
PWM pin in output mode
End of enumeration elements list.
POEN1 : PWM Pin Output Enable Bits
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM pin at tri-state
#1 : 1
PWM pin in output mode
End of enumeration elements list.
POEN2 : PWM Pin Output Enable Bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM pin at tri-state
#1 : 1
PWM pin in output mode
End of enumeration elements list.
POEN3 : PWM Pin Output Enable Bits
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM pin at tri-state
#1 : 1
PWM pin in output mode
End of enumeration elements list.
POEN4 : PWM Pin Output Enable Bits
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM pin at tri-state
#1 : 1
PWM pin in output mode
End of enumeration elements list.
POEN5 : PWM Pin Output Enable Bits
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM pin at tri-state
#1 : 1
PWM pin in output mode
End of enumeration elements list.
PWM Software Brake Control Register
address_offset : 0xDC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BRKETRG0 : PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : write-only
BRKETRG2 : PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : write-only
BRKETRG4 : PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : write-only
BRKLTRG0 : PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : write-only
BRKLTRG2 : PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : write-only
BRKLTRG4 : PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 10 - 10 (1 bit)
access : write-only
PWM Interrupt Enable Register 0
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZIEN0 : PWM Zero Point Interrupt Enable Bit 0\nNote: Odd channels will read always 0 at complementary mode.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
ZIEN2 : PWM Zero Point Interrupt Enable Bit 2\nNote: Odd channels will read always 0 at complementary mode.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
ZIEN4 : PWM Zero Point Interrupt Enable Bit 4\nNote: Odd channels will read always 0 at complementary mode.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
PIEN0 : PWM Period Point Interrupt Enable Bit 0\nNote: When up-down counter type, period point means center point.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
PIEN2 : PWM Period Point Interrupt Enable Bit 2\nNote: When up-down counter type, period point means center point.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
PIEN4 : PWM Period Point Interrupt Enable Bit 4\nNote: When up-down counter type, period point means center point.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
CMPUIEN0 : PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN1 : PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN2 : PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN3 : PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN4 : PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN5 : PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPDIEN0 : PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN1 : PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN2 : PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN3 : PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN4 : PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN5 : PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
PWM Interrupt Enable Register 1
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKEIEN0_1 : PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-detect Brake interrupt for channel0/1 Disabled
#1 : 1
Edge-detect Brake interrupt for channel0/1 Enabled
End of enumeration elements list.
BRKEIEN2_3 : PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-detect Brake interrupt for channel2/3 Disabled
#1 : 1
Edge-detect Brake interrupt for channel2/3 Enabled
End of enumeration elements list.
BRKEIEN4_5 : PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bitr is write protected. Refer to SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-detect Brake interrupt for channel4/5 Disabled
#1 : 1
Edge-detect Brake interrupt for channel4/5 Enabled
End of enumeration elements list.
BRKLIEN0_1 : PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Level-detect Brake interrupt for channel0/1 Disabled
#1 : 1
Level-detect Brake interrupt for channel0/1 Enabled
End of enumeration elements list.
BRKLIEN2_3 : PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Level-detect Brake interrupt for channel2/3 Disabled
#1 : 1
Level-detect Brake interrupt for channel2/3 Enabled
End of enumeration elements list.
BRKLIEN4_5 : PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Level-detect Brake interrupt for channel4/5 Disabled
#1 : 1
Level-detect Brake interrupt for channel4/5 Enabled
End of enumeration elements list.
PWM Interrupt Flag Register 0
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZIF0 : PWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1.
bits : 0 - 0 (1 bit)
access : read-write
ZIF2 : PWM Zero Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1.
bits : 2 - 2 (1 bit)
access : read-write
ZIF4 : PWM Zero Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1.
bits : 4 - 4 (1 bit)
access : read-write
PIF0 : PWM Period Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches PWM_PERIOD0.\nNote: This bit can be cleared to 0 by software writing 1.
bits : 8 - 8 (1 bit)
access : read-write
PIF2 : PWM Period Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches PWM_PERIOD2.\nNote: This bit can be cleared to 0 by software writing 1.
bits : 10 - 10 (1 bit)
access : read-write
PIF4 : PWM Period Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches PWM_PERIOD4.\nNote: This bit can be cleared to 0 by software writing 1.
bits : 12 - 12 (1 bit)
access : read-write
CMPUIFn : PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4.
bits : 16 - 21 (6 bit)
access : read-write
CMPDIF0 : PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
bits : 24 - 24 (1 bit)
access : read-write
CMPDIF1 : PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
bits : 25 - 25 (1 bit)
access : read-write
CMPDIF2 : PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
bits : 26 - 26 (1 bit)
access : read-write
CMPDIF3 : PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
bits : 27 - 27 (1 bit)
access : read-write
CMPDIF4 : PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
bits : 28 - 28 (1 bit)
access : read-write
CMPDIF5 : PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
bits : 29 - 29 (1 bit)
access : read-write
PWM Interrupt Flag Register 1
address_offset : 0xEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKEIF0 : PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n edge-detect brake event do not happened
#1 : 1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKEIF1 : PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n edge-detect brake event do not happened
#1 : 1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKEIF2 : PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n edge-detect brake event do not happened
#1 : 1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKEIF3 : PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n edge-detect brake event do not happened
#1 : 1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKEIF4 : PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n edge-detect brake event do not happened
#1 : 1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKEIF5 : PWM Channel n Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n edge-detect brake event do not happened
#1 : 1
When PWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKLIF0 : PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n level-detect brake event do not happened
#1 : 1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKLIF1 : PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n level-detect brake event do not happened
#1 : 1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKLIF2 : PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n level-detect brake event do not happened
#1 : 1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKLIF3 : PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n level-detect brake event do not happened
#1 : 1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKLIF4 : PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n level-detect brake event do not happened
#1 : 1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKLIF5 : PWM Channel n Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM channel n level-detect brake event do not happened
#1 : 1
When PWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKESTS0 : PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel n edge-detect brake state is released
#1 : 1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
End of enumeration elements list.
BRKESTS1 : PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel n edge-detect brake state is released
#1 : 1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
End of enumeration elements list.
BRKESTS2 : PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel n edge-detect brake state is released
#1 : 1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
End of enumeration elements list.
BRKESTS3 : PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel n edge-detect brake state is released
#1 : 1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
End of enumeration elements list.
BRKESTS4 : PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel n edge-detect brake state is released
#1 : 1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
End of enumeration elements list.
BRKESTS5 : PWM Channel n Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel n edge-detect brake state is released
#1 : 1
When PWM channel n edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
End of enumeration elements list.
BRKLSTS0 : PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel n level-detect brake state is released
#1 : 1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
End of enumeration elements list.
BRKLSTS1 : PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel n level-detect brake state is released
#1 : 1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
End of enumeration elements list.
BRKLSTS2 : PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel n level-detect brake state is released
#1 : 1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
End of enumeration elements list.
BRKLSTS3 : PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel n level-detect brake state is released
#1 : 1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
End of enumeration elements list.
BRKLSTS4 : PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel n level-detect brake state is released
#1 : 1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
End of enumeration elements list.
BRKLSTS5 : PWM Channel n Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM channel n level-detect brake state is released
#1 : 1
When PWM channel n level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel n at brake state
End of enumeration elements list.
PWM Trigger ADC Source Select Register 0
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL0 : PWM_CH0 Trigger ADC Source Select
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_CH0 zero point
#0001 : 1
PWM_CH0 period point
#0010 : 2
PWM_CH0 zero or period point
#0011 : 3
PWM_CH0 up-count CMPDAT point
#0100 : 4
PWM_CH0 down-count CMPDAT point
#0101 : 5
Reserved.
#0110 : 6
Reserved.
#0111 : 7
Reserved.
#1000 : 8
PWM_CH1 up-count CMPDAT point
#1001 : 9
PWM_CH1 down-count CMPDAT point
End of enumeration elements list.
TRGEN0 : PWM_CH0 Trigger ADC Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_CH0 Trigger ADC function Disabled
#1 : 1
PWM_CH0 Trigger ADC function Enabled
End of enumeration elements list.
TRGSEL1 : PWM_CH1 Trigger ADC Source Select
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_CH0 zero point
#0001 : 1
PWM_CH0 period point
#0010 : 2
PWM_CH0 zero or period point
#0011 : 3
PWM_CH0 up-count CMPDAT point
#0100 : 4
PWM_CH0 down-count CMPDAT point
#0101 : 5
Reserved.
#0110 : 6
Reserved.
#0111 : 7
Reserved.
#1000 : 8
PWM_CH1 up-count CMPDAT point
#1001 : 9
PWM_CH1 down-count CMPDAT point
End of enumeration elements list.
TRGEN1 : PWM_CH1 Trigger ADC Enable Bit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_CH1 Trigger ADC function Disabled
#1 : 1
PWM_CH1 Trigger ADC function Enabled
End of enumeration elements list.
TRGSEL2 : PWM_CH2 Trigger ADC Source Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_CH2 zero point
#0001 : 1
PWM_CH2 period point
#0010 : 2
PWM_CH2 zero or period point
#0011 : 3
PWM_CH2 up-count CMPDAT point
#0100 : 4
PWM_CH2 down-count CMPDAT point
#0101 : 5
Reserved.
#0110 : 6
Reserved.
#0111 : 7
Reserved.
#1000 : 8
PWM_CH3 up-count CMPDAT point
#1001 : 9
PWM_CH3 down-count CMPDAT point
End of enumeration elements list.
TRGEN2 : PWM_CH2 Trigger ADC Enable Bit
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_CH2 Trigger ADC function Disabled
#1 : 1
PWM_CH2 Trigger ADC function Enabled
End of enumeration elements list.
TRGSEL3 : PWM_CH3 Trigger ADC Source Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_CH2 zero point
#0001 : 1
PWM_CH2 period point
#0010 : 2
PWM_CH2 zero or period point
#0011 : 3
PWM_CH2 up-count CMPDAT point
#0100 : 4
PWM_CH2 down-count CMPDAT point
#0101 : 5
Reserved.
#0110 : 6
Reserved.
#0111 : 7
Reserved.
#1000 : 8
PWM_CH3 up-count CMPDAT point
#1001 : 9
PWM_CH3 down-count CMPDAT point
End of enumeration elements list.
TRGEN3 : PWM_CH3 Trigger ADC Enable Bit
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_CH3 Trigger ADC function Disabled
#1 : 1
PWM_CH3 Trigger ADC function Enabled
End of enumeration elements list.
PWM Trigger ADC Source Select Register 1
address_offset : 0xFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL4 : PWM_CH4 Trigger ADC Source Select
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_CH4 zero point
#0001 : 1
PWM_CH4 period point
#0010 : 2
PWM_CH4 zero or period point
#0011 : 3
PWM_CH4 up-count CMPDAT point
#0100 : 4
PWM_CH4 down-count CMPDAT point
#0101 : 5
Reserved.
#0110 : 6
Reserved.
#0111 : 7
Reserved.
#1000 : 8
PWM_CH5 up-count CMPDAT point
#1001 : 9
PWM_CH5 down-count CMPDAT point
End of enumeration elements list.
TRGEN4 : PWM_CH4 Trigger ADC Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_CH4 Trigger ADC function Disabled
#1 : 1
PWM_CH4 Trigger ADC function Enabled
End of enumeration elements list.
TRGSEL5 : PWM_CH5 Trigger ADC Source Select
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
PWM_CH4 zero point
#0001 : 1
PWM_CH4 period point
#0010 : 2
PWM_CH4 zero or period point
#0011 : 3
PWM_CH4 up-count CMPDAT point
#0100 : 4
PWM_CH4 down-count CMPDAT point
#0101 : 5
Reserved.
#0110 : 6
Reserved.
#0111 : 7
Reserved.
#1000 : 8
PWM_CH5 up-count CMPDAT point
#1001 : 9
PWM_CH5 down-count CMPDAT point
End of enumeration elements list.
TRGEN5 : PWM_CH5 Trigger ADC Enable Bit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_CH5 Trigger ADC function Disabled
#1 : 1
PWM_CH5 Trigger ADC function Enabled
End of enumeration elements list.
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