SC_DAT

SC_RXTOUT

SC_ETUCTL

SC_INTEN

SC_INTSTS

SC_STATUS

SC_PINCTL

SC_TMRCTL0

SC_TMRCTL1

SC_TMRCTL2

SC_UARTCTL

SC_CTL

SC_ACTCTL

SC_ALTCTL

SC_EGT

DAT : Receive/Transmit Holding Buffer\nWrite Operation:\nBy writing data to DAT, the SC will send out an 8-bit data.\nNote: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed.\nRead Operation:\nBy reading DAT, the SC will return an 8-bit received data.
bits : 0 - 7 (8 bit)
access : read-write

RFTM : SC Receiver FIFO Time-out Counter\nThe time-out down counter resets and starts counting whenever the RX buffer received a new data. Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SCn_DAT, a receiver time-out flag RXTOIF (SCn_INTSTS[9]) will be set, and hardware will generate an interrupt to CPU when RXTOIEN (SCn_INTEN[9]) is enabled.\nNote1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.\nNote2: Filling in all 0 to this field indicates to disable this function.
bits : 0 - 8 (9 bit)
access : read-write

ETURDIV : ETU Rate Divider\nThe field is used for ETU clock rate divider.\nThe real ETU is ETURDIV + 1.\nNote: User can configure this field, but this field must be greater than 0x04.
bits : 0 - 11 (12 bit)
access : read-write

RDAIEN : Receive Data Reach Interrupt Enable Bit\nThis field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TBEIEN : Transmit Buffer Empty Interrupt Enable Bit\nThis field is used to enable transmit buffer empty interrupt.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TERRIEN : Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt. The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error TXOVERR (SCn_STATUS[30]).
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0IEN : Timer0 Interrupt Enable Bit\nThis field is used to enable Timer0 interrupt function.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1IEN : Timer1 Interrupt Enable Bit\nThis field is used to enable the Timer1 interrupt function.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2IEN : Timer2 Interrupt Enable Bit\nThis field is used to enable Timer2 interrupt function.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BGTIEN : Block Guard Time Interrupt Enable Bit\nThis field is used to enable block guard time interrupt in receive direction.\nNote: This bit is valid only for receive direction block guard time.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDIEN : Card Detect Interrupt Enable Bit\nThis field is used to enable card detect interrupt. The card detect status is CDPINSTS (SCn_STATUS[13]).
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INITIEN : Initial End Interrupt Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXTOIEN : Receiver Buffer Time-out Interrupt Enable Bit \nThis field is used to enable receiver buffer time-out interrupt.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACERRIEN : Auto Convention Error Interrupt Enable Bit \nThis field is used to enable auto-convention error interrupt.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDAIF : Receive Data Reach Interrupt Status Flag (Read Only)\nThis field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag.\nNote: This bit is read only. If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, this bit will be cleared automatically.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TBEIF : Transmit Buffer Empty Interrupt Status Flag (Read Only)\nThis field is used for transmit buffer empty interrupt status flag.\nNote: This bit is read only. If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit will be cleared automatically.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TERRIF : Transfer Error Interrupt Status Flag\nThis field is used for transfer error interrupt status flag. The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error TXOVERR (SCn_STATUS[30]).\nNote1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR.\nNote2: This bit can be cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0IF : Timer0 Interrupt Status Flag\nThis field is used for Timer0 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1IF : Timer1 Interrupt Status Flag\nThis field is used for Timer1 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2IF : Timer2 Interrupt Status Flag\nThis field is used for Timer2 interrupt status flag.\nNote: This bit can be cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BGTIF : Block Guard Time Interrupt Status Flag\nThis field is used for indicate block guard time interrupt status flag in receive direction.\nNote1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled.\nNote2: This bit can be cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDIF : Card Detect Interrupt Status Flag (Read Only)\nThis field is used for card detect interrupt status flag. The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]).\nNote: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

INITIF : Initial End Interrupt Status Flag\nThis field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag.\nNote: This bit can be cleared by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXTOIF : Receive Buffer Time-out Interrupt Status Flag (Read Only)\nThis field is used for indicate receive buffer time-out interrupt status flag.\nNote: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT register to clear it.
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ACERRIF : Auto Convention Error Interrupt Status Flag\nThis field indicates auto convention sequence error.\nNote: This bit can be cleared by writing 1 to it.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOV : Receive Overflow Error Status Flag \nThis bit is set when Rx buffer overflow.\nNote: This bit can be cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXEMPTY : Receive Buffer Empty Status Flag (Read Only)\nThis bit indicates Rx buffer empty or not.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXFULL : Receive Buffer Full Status Flag (Read Only)\nThis bit indicates Rx buffer full or not.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PEF : Receiver Parity Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid parity bit .\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FEF : Receiver Frame Error Status Flag\nThis bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). \nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BEF : Receiver Break Error Status Flag\nThis bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of 'start bit' + 'data bits' + 'parity bit' + 'stop bits').\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXOV : Transmit Overflow Error Interrupt Status Flag\nThis bit is set when Tx buffer overflow. \nNote: This bit can be cleared by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXEMPTY : Transmit Buffer Empty Status Flag (Read Only)\nThis bit indicates TX buffer empty or not.\nNote: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]).
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXFULL : Transmit Buffer Full Status Flag (Read Only)\nThis bit indicates Tx buffer full or not.
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CREMOVE : Card Removal Status of SCn_CD Pin\nThis bit is set whenever card has been removal.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: Card detect function will start after SCEN (SCn_CTL[0]) set.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CINSERT : Card Insert Status of SCn_CD Pin\nThis bit is set whenever card has been inserted.\nNote1: This bit can be cleared by writing '1' to it.\nNote2: The card detect function will start after SCEN (SCn_CTL[0]) set.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDPINSTS : Card Detect Pin Status (Read Only)\nThis bit is the pin status of SCn_CD.
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXPOINT : Receive Buffer Pointer Status (Read Only)\nThis field indicates the Rx buffer pointer status. When SC controller receives one byte from external device, RXPOINT increases one. When one byte of Rx buffer is read by CPU, RXPOINT decreases one.
bits : 16 - 18 (3 bit)
access : read-only

RXRERR : Receiver Retry Error\nThis bit is used for receiver error retry and set by hardware.\nNote1: This bit can be cleared by writing 1 to it.\nNote2 This bit is a flag and cannot generate any interrupt to CPU.\nNote3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOVERR : Receiver over Retry Error\nThis bit is used for receiver retry counts over than retry number limitation.\nNote1: This bit can be cleared by writing 1 to it.\nNote2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXACT : Receiver in Active Status Flag (Read Only)\nThis bit indicates Rx transfer status.
bits : 23 - 23 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXPOINT : Transmit Buffer Pointer Status (Read Only)\nThis field indicates the Tx buffer pointer status. When CPU writes data into SCn_DAT, TXPOINT increases one. When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one.
bits : 24 - 26 (3 bit)
access : read-only

TXRERR : Transmitter Retry Error\nThis bit is used for indicate transmitter error retry and set by hardware..\nNote1: This bit can be cleared by writing 1 to it.\nNote2: This bit is a flag and cannot generate any interrupt to CPU.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXOVERR : Transmitter over Retry Error\nThis bit is used for transmitter retry counts over than retry number limitation.\nNote: This bit can be cleared by writing 1 to it.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXACT : Transmit in Active Status Flag (Read Only)\nThis bit indicates Tx transmit status.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PWREN : SCn_PWR Pin Signal\nUser can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level.\nWrite this field to drive SCn_PWR pin\nRefer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level. \nRead this field to get SCn_PWR signal status.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTEN : SCn_RST Pin Signal\nUser can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level.\nWrite this field to drive SCn_RST pin.\nNote: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKKEEP : SC Clock Enable Bit \nNote: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when operating in these modes.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCDATA : SCn_DATA Pin Signal \nThis bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit.\nNote: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. Thus, do not fill in this field when SC is in these modes.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWRINV : SCn_PWR Pin Inverse\nThis bit is used for inverse the SCn_PWR pin.\nThere are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]). \nPWRINV (SCn_PINCTL[11]) is bit 1 and PWREN (SCn_PINCTL[0]) is bit 0 and all conditions as below list, \nNote: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]).
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATASTS : SCn_DATA Pin Status (Read Only)\nThis bit is the pin status of SCn_DATA.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PWRSTS : SCn_PWR Pin Status (Read Only)\nThis bit is the pin status of SCn_PWR.
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RSTSTS : SCn_RST Pin Status (Read Only)\nThis bit is the pin status of SCn_RST.
bits : 18 - 18 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SYNC : SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SCn_PINCTL register.
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CNT : Timer0 Counter Value\nThis field indicates the internal Timer0 counter values.\nNote: Unit of Timer0 counter is ETU base.
bits : 0 - 23 (24 bit)
access : read-write

OPMODE : Timer0 Operation Mode Selection\nThis field indicates the internal 24-bit Timer0 operation selection.\nRefer to Error! Reference source not found. for programming Timer0.
bits : 24 - 27 (4 bit)
access : read-write

SYNC : SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CNT : Timer 1 Counter Value\nThis field indicates the internal Timer1 counter values. \nNote: Unit of Timer1 counter is ETU base.
bits : 0 - 7 (8 bit)
access : read-write

OPMODE : Timer 1 Operation Mode Selection\nThis field indicates the internal 8-bit Timer1 operation selection.\nRefer to Error! Reference source not found. for programming Timer1.
bits : 24 - 27 (4 bit)
access : read-write

SYNC : SYNC Flag Indicator (Read Only)\nDue to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CNT : Timer 2 Counter Value\nThis field indicates the internal Timer2 counter values. \nNote: Unit of Timer2 counter is ETU base.
bits : 0 - 7 (8 bit)
access : read-write

OPMODE : Timer 2 Operation Mode Selection\nThis field indicates the internal 8-bit Timer2 operation selection\nRefer to Error! Reference source not found. for programming Timer2.
bits : 24 - 27 (4 bit)
access : read-write

SYNC : SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

UARTEN : UART Mode Enable Bit\nSets this bit to enable UART mode function.\nNote3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WLS : Word Length Selection\nThis field is used for select UART data length.\nNote: In smart card mode, this WLS must be 00.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBOFF : Parity Bit Disable Bit\nSets this bit is used for disable parity check function.\nNote: In smart card mode, this field must be 0 (default setting is with parity bit).
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPE : Odd Parity Enable Bit\nThis is used for odd/even parity selection.\nNote: This bit has effect only when PBOFF bit is 0.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCEN : SC Controller Enable Bit\nSet this bit to 1 to enable SC operation. If this bit is cleared, \nNote: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOFF : RX Transition Disable Control Bit\nThis bit is used for disable Rx transition function.\nNote: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXOFF : TX Transition Disable Control Bit\nThis bit is used for disable Tx transition function.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTOCEN : Auto Convention Enable Bit\nThis bit is used for enable auto convention function.\nNote1: If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F. After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F. If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11.\nNote2: If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CONSEL : Convention Selection\nNote: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXTRGLV : Rx Buffer Trigger Level \nWhen the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set. If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BGT : Block Guard Time (BGT)\nNote: The real block guard time is BGT + 1.
bits : 8 - 12 (5 bit)
access : read-write

TMRSEL : Timer Channel Selection \nOther configurations are reserved
bits : 13 - 14 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NSB : Stop Bit Length\nThis field indicates the length of stop bit.\nNote1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length. \nNote2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXRTY : RX Error Retry Count Number\nThis field indicates the maximum number of receiver retries that are allowed when parity error has occurred\nNote1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when RXRTYEN enabled. The change flow is to disable RXRTYEN first and then fill in new retry value.
bits : 16 - 18 (3 bit)
access : read-write

RXRTYEN : RX Error Retry Enable Bit\nThis bit enables receiver retry function when parity error has occurred.\nNote: User must fill in the RXRTY value before enabling this bit.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXRTY : TX Error Retry Count Number\nThis field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.\nNote1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.\nNote2: This field cannot be changed when TXRTYEN enabled. The change flow is to disable TXRTYEN first and then fill in new retry value.
bits : 20 - 22 (3 bit)
access : read-write

TXRTYEN : TX Error Retry Enable Bit\nThis bit enables transmitter retry function when parity error has occurred.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDDBSEL : Card Detect De-bounce Selection\nThis field indicates the card detect de-bounce selection.\nOther configurations are reserved.
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDLV : Card Detect Level Selection \nNote: User must select card detect level before Smart Card controller enabled.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYNC : SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields.
bits : 30 - 30 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

T1EXT : T1 Extend Time of Hardware Activation\nThis field provide the configurable cycles to extend the activation time T1 period.\nThe cycle scaling factor is 2048.\nNote: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3.
bits : 0 - 4 (5 bit)
access : read-write

TXRST : TX Software Reset\nWhen TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXRST : Rx Software Reset\nWhen RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared.\nNote: This bit will be auto cleared after reset is complete.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DACTEN : Deactivation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by deactivation sequence.\nNote1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]). Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACTEN : Activation Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by activation sequence.\nNote1: When the activation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]). Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.\nNote4: During the activation sequence, RX is disabled automatically and can not receive data. After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WARSTEN : Warm Reset Sequence Generator Enable Bit\nThis bit enables SC controller to initiate the card by warm reset sequence.\nNote1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1.\nNote2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]). Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.\nNote4: During the warm reset sequence, RX is disabled automatically and can not receive data. After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform warm reset sequence.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN0 : Internal Timer0 Start Enable Bit\nThis bit enables Timer 0 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN1 : Internal Timer1 Start Enable Bit\nThis bit enables Timer 1 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN2 : Internal Timer2 Start Enable Bit\nThis bit enables Timer 2 to start counting. User can fill 0 to stop it and set 1 to reload and count. The counter unit is ETU base.\nNote3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INITSEL : Initial Timing Selection\nThis fields indicates the initial timing of hardware activation, warm-reset or deactivation.\nThe unit of initial timing is SC module clock.\nActivation: refer to SC Activation Sequence in Error! Reference source not found..\nWarm-reset: refer to Warm-Reset Sequence in Error! Reference source not found..\nDeactivation: refer to Deactivation Sequence in Error! Reference source not found..\nNote: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation at most 128 SC module clock cycles.
bits : 8 - 9 (2 bit)
access : read-write

ADACEN : Auto Deactivation When Card Removal\nThis bit is used for enable hardware auto deactivation when smart card is removed.\nNote: When the card is removed, hardware will stop any process and then do deactivation sequence if this bit is set. If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXBGTEN : Receiver Block Guard Time Function Enable Bit\nThis bit enables the receiver block guard time function.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACTSTS0 : Internal Timer0 Active Status (Read Only)\nThis bit indicates the timer counter status of timer0.\nNote: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]).
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ACTSTS1 : Internal Timer1 Active Status (Read Only)\nThis bit indicates the timer counter status of timer1.\nNote: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]).
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ACTSTS2 : Internal Timer2 Active Status (Read Only)\nThis bit indicates the timer counter status of timer2.\nNote: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]).
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SYNC : SYNC Flag Indicator (Read Only)\nDue to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register.
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

EGT : Extra Guard Time\nThis field indicates the extra guard time value.\nNote: The extra guard time unit is ETU base.
bits : 0 - 7 (8 bit)
access : read-write