USPI_CTL

USPI_DATIN0

USPI_CTLIN0

USPI_CLKIN

USPI_LINECTL

USPI_TXDAT

USPI_RXDAT

USPI_BUFCTL

USPI_BUFSTS

USPI_INTEN

USPI_PDMACTL

USPI_WKCTL

USPI_WKSTS

USPI_PROTCTL

USPI_PROTIEN

USPI_PROTSTS

USPI_BRGEN

FUNMODE : Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYNCSEL : Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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ININV : Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
bits : 2 - 2 (1 bit)
access : read-write

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SYNCSEL : Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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ININV : Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.
bits : 2 - 2 (1 bit)
access : read-write

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SYNCSEL : Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal, which is synchronized with PCLK, can be used as input for the data shift unit.\nNote: In SPI protocol, it is suggested this bit should be set as 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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LSB : LSB First Transmission Selection
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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DATOINV : Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin.
bits : 5 - 5 (1 bit)
access : read-write

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CTLOINV : Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol. In SPI protocol, the control signal means slave select signal.
bits : 7 - 7 (1 bit)
access : read-write

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DWIDTH : Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].
bits : 8 - 11 (4 bit)
access : read-write

TXDAT : Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission. In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field.
bits : 0 - 15 (16 bit)
access : write-only

PORTDIR : Port Direction Control
bits : 16 - 16 (1 bit)
access : write-only

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RXDAT : Received Data\nThis bit field monitors the received data which stored in receive data buffer.
bits : 0 - 15 (16 bit)
access : read-only

TXUDRIEN : Slave Transmit Under-run Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

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TXCLR : Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle.
bits : 7 - 7 (1 bit)
access : read-write

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RXOVIEN : Receive Buffer Overrun Interrupt Enable Bit
bits : 14 - 14 (1 bit)
access : read-write

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RXCLR : Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle.
bits : 15 - 15 (1 bit)
access : read-write

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TXRST : Transmit Reset
bits : 16 - 16 (1 bit)
access : read-write

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RXRST : Receive Reset\nNote: It is cleared automatically after one PCLK cycle.
bits : 17 - 17 (1 bit)
access : read-write

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RXEMPTY : Receive Buffer Empty Indicator
bits : 0 - 0 (1 bit)
access : read-only

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RXFULL : Receive Buffer Full Indicator
bits : 1 - 1 (1 bit)
access : read-only

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RXOVIF : Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected. If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit.
bits : 3 - 3 (1 bit)
access : read-only

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TXEMPTY : Transmit Buffer Empty Indicator
bits : 8 - 8 (1 bit)
access : read-only

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TXFULL : Transmit Buffer Full Indicator
bits : 9 - 9 (1 bit)
access : read-only

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TXUDRIF : Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected. If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated. It is cleared by software writes 1 to this bit
bits : 11 - 11 (1 bit)
access : read-only

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TXSTIEN : Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.\nNote: The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit.
bits : 1 - 1 (1 bit)
access : read-write

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TXENDIEN : Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.\nNote: The transmit finish event happens when hardware sends the last bit of TX data from shift data unit.
bits : 2 - 2 (1 bit)
access : read-write

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RXSTIEN : Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event.\nNote: For SPI master mode, the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave. For SPI slave mode, the receive start event happens when slave select of SPI slave is active and spi clock of SPI slave is inputed from the external SPI master.
bits : 3 - 3 (1 bit)
access : read-write

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RXENDIEN : Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.\nNote: The receive finish event happens when hardware receives the last bit of RX data into shift data unit.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

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PDMARST : PDMA Reset
bits : 0 - 0 (1 bit)
access : read-write

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TXPDMAEN : PDMA Transmit Channel Available
bits : 1 - 1 (1 bit)
access : read-write

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RXPDMAEN : PDMA Receive Channel Available
bits : 2 - 2 (1 bit)
access : read-write

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PDMAEN : PDMA Mode Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

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WKEN : Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

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PDBOPT : Power Down Blocking Option
bits : 2 - 2 (1 bit)
access : read-write

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WKF : Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

SLAVE : Slave Mode Selection
bits : 0 - 0 (1 bit)
access : read-write

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SLV3WIRE : Slave 3-wire Mode Selection (Slave Only)\nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.
bits : 1 - 1 (1 bit)
access : read-write

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SS : Slave Select Control (Master Only)\nIf AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state.\nNote: In SPI protocol, the internal slave select signal is active high.
bits : 2 - 2 (1 bit)
access : read-write

AUTOSS : Automatic Slave Select Function Enable (Master Only)
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCLKMODE : Serial Bus Clock Mode\nThis bit field defines the SCLK idle status, data transmit, and data receive edge.
bits : 6 - 7 (2 bit)
access : read-write

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End of enumeration elements list.

SUSPITV : Suspend Interval (Master Only)\nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV + 0.5) * period of SPI_CLK clock cycle\nExample:
bits : 8 - 11 (4 bit)
access : read-write

TSMSEL : Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically.
bits : 12 - 14 (3 bit)
access : read-write

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SLVTOCNT : Slave Mode Time-out Period (Slave Only)\nIn Slave mode, this bit field is used for Slave time-out period. This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event. Writing 0x0 into this bit field will disable the Slave time-out function.\nExample: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK.
bits : 16 - 25 (10 bit)
access : read-write

TXUDRPOL : Transmit Under-run Data Polarity (for Slave)\nThis bit defines the transmitting data level of USCIx_DAT1 when no data is available for transferring.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

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PROTEN : SPI Protocol Enable Bit
bits : 31 - 31 (1 bit)
access : read-write

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SSINAIEN : Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive.
bits : 0 - 0 (1 bit)
access : read-write

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SSACTIEN : Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active.
bits : 1 - 1 (1 bit)
access : read-write

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SLVTOIEN : Slave Time-out Interrupt Enable Bit\nIn SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event.
bits : 2 - 2 (1 bit)
access : read-write

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SLVBEIEN : Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]). Bit count error event occurs.
bits : 3 - 3 (1 bit)
access : read-write

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TXSTIF : Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit.
bits : 1 - 1 (1 bit)
access : read-write

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TXENDIF : Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The transmit end event happens when hardware sends the last bit of TX data from shift data unit.
bits : 2 - 2 (1 bit)
access : read-write

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End of enumeration elements list.

RXSTIF : Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit. For SPI master mode, the receive start event happens when SPI master sends slave select active and spi clock to the external SPI slave. For SPI slave mode, the receive start event happens when slave select of SPI slave is active and spi clock of SPI slave is inputed from the external SPI master.
bits : 3 - 3 (1 bit)
access : read-write

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RXENDIF : Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit. The receive end event happens when hardware receives the last bit of RX data into shift data unit.
bits : 4 - 4 (1 bit)
access : read-write

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End of enumeration elements list.

SLVTOIF : Slave Time-out Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit
bits : 5 - 5 (1 bit)
access : read-write

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SLVBEIF : Slave Bit Count Error Interrupt Flag (for Slave Only)\nNote: It is cleared by software write 1 to this bit. If the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]), bit count error event occurs.
bits : 6 - 6 (1 bit)
access : read-write

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SSINAIF : Slave Select Inactive Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to inactive. It is cleared by software writes 1 to this bit\nNote: The internal slave select signal is active high.
bits : 8 - 8 (1 bit)
access : read-write

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SSACTIF : Slave Select Active Interrupt Flag (for Slave Only)\nThis bit indicates that the internal slave select signal has changed to active. It is cleared by software writes one to this bit\nNote: The internal slave select signal is active high.
bits : 9 - 9 (1 bit)
access : read-write

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SSLINE : Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode. It used to monitor the current status of the input slave select signal on the bus.
bits : 16 - 16 (1 bit)
access : read-only

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BUSY : Busy Status (Read Only)
bits : 17 - 17 (1 bit)
access : read-only

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SLVUDR : Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1. This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not.
bits : 18 - 18 (1 bit)
access : read-only

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RCLKSEL : Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK).
bits : 0 - 0 (1 bit)
access : read-write

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PTCLKSEL : Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK).
bits : 1 - 1 (1 bit)
access : read-write

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SPCLKSEL : Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor.
bits : 2 - 3 (2 bit)
access : read-write

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TMCNTEN : Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.
bits : 4 - 4 (1 bit)
access : read-write

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TMCNTSRC : Time Measurement Counter Clock Source Selection
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKDIV : Clock Divider
bits : 16 - 25 (10 bit)
access : read-write