Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x5C byte (0x0)
mem_usage : registers
protection : not protected
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size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
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size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
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size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xA0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
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size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
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size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x120 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
PSIO Interrupt Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CONI0SS : Configurable Interrupt 0 Slot Selection \n0000: NO USE\n0001: SLOT0\n0010: SLOT1\n0011: SLOT2\n0100: SLOT3\n0101: SLOT4\n0110: SLOT5\n0111: SLOT6\n1000: SLOT7\n1001 - 1111:Reserved
bits : 0 - 2 (3 bit)
access : read-write
CONI1SS : Configurable Interrupt 1 Slot Selection \n0000: NO USE\n0001: SLOT0\n0010: SLOT1\n0011: SLOT2\n0100: SLOT3\n0101: SLOT4\n0110: SLOT5\n0111: SLOT6\n1000: SLOT7\n1001 - 1111:Reserved
bits : 4 - 6 (3 bit)
access : read-write
CONI0SCS : Configurable Interrupt 0 Slot Controller Selection \nSelect Slot controller for INT0
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Slot controller 0
#01 : 1
Slot controller 1
#10 : 2
Slot controller 2
#11 : 3
Slot controller 3
End of enumeration elements list.
CONI1SCS : Configurable Interrupt 1 Slot Controller Selection \nSelect Slot controller for INT1
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
Slot controller 0
#01 : 1
Slot controller 1
#10 : 2
Slot controller 2
#11 : 3
Slot controller 3
End of enumeration elements list.
PSIO Input Status State Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALID0 : Input Status Valid 0\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin 0 input Status is not ready
#1 : 1
The pin 0 input Status is ready
End of enumeration elements list.
INSTSOV0 : Input Status Overflow 0\nNote: This overflow bit can be write 1 clear..
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin 0 input Status does not overflow
#1 : 1
The pin 0 input Status occur overflow
End of enumeration elements list.
VALID1 : Input Status Valid 1\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin 1 input Status is not ready
#1 : 1
The pin 1 input Status is ready
End of enumeration elements list.
INSTSOV1 : Input Status Overflow 1\nNote: This overflow bit can be write 1 clear..
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin 1 input Status does not overflow
#1 : 1
The pin 1 input Status occur overflow
End of enumeration elements list.
VALID2 : Input Status Valid 2\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin 2 input Status is not ready
#1 : 1
The pin 2 input Status is ready
End of enumeration elements list.
INSTSOV2 : Input Status Overflow 2\nNote: This overflow bit can be write 1 clear..
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin 2 input Status does not overflow
#1 : 1
The pin 2 input Status occur overflow
End of enumeration elements list.
VALID3 : Input Status Valid 3\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin 3 input Status is not ready
#1 : 1
The pin 3 input Status is ready
End of enumeration elements list.
INSTSOV3 : Input Status Overflow 3\nNote: This overflow bit can be write 1 clear..
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin 3 input Status does not overflow
#1 : 1
The pin 3 input Status occur overflow
End of enumeration elements list.
VALID4 : Input Status Valid 4\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin 4 input Status is not ready
#1 : 1
The pin 4 input Status is ready
End of enumeration elements list.
INSTSOV4 : Input Status Overflow 4\nNote: This overflow bit can be write 1 clear..
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin 4 input Status does not overflow
#1 : 1
The pin 4 input Status occur overflow
End of enumeration elements list.
VALID5 : Input Status Valid 5\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin 5 input Status is not ready
#1 : 1
The pin 5 input Status is ready
End of enumeration elements list.
INSTSOV5 : Input Status Overflow 5\nNote: This overflow bit can be write 1 clear..
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin 5 input Status does not overflow
#1 : 1
The pin 5 input Status occur overflow
End of enumeration elements list.
VALID6 : Input Status Valid 6\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin 6 input Status is not ready
#1 : 1
The pin 6 input Status is ready
End of enumeration elements list.
INSTSOV6 : Input Status Overflow 6\nNote: This overflow bit can be write 1 clear..
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin 6 input Status does not overflow
#1 : 1
The pin 6 input Status occur overflow
End of enumeration elements list.
VALID7 : Input Status Valid 7\nNote: This valid bit will be cleared automatically if PSIOn_INSTS is read.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin7 input Status is not ready
#1 : 1
The pin7 input Status is ready
End of enumeration elements list.
INSTSOV7 : Input Status Overflow 7\nNote: This overflow bit can be write 1 clear..
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin7 input Status does not overflow
#1 : 1
The pin7 input Status occur overflow
End of enumeration elements list.
PSIOn General Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Data Control Register
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Input Status Register
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Input Data Register
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Output Data Register
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Check Point Control 0 Register
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Check Point Control1 Register
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn General Control Register
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Data Control Register
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Input Status Register
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Input Data Register
address_offset : 0x12C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Output Data Register
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Check Point Control 0 Register
address_offset : 0x134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Check Point Control1 Register
address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIO PDMA Control Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPIN0EN : Output PDMA Pin0 Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin0 output PDMA function Disabled
#1 : 1
Pin0 output PDMA function Enabled
End of enumeration elements list.
OPIN1EN : Output PDMA Pin1 Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin1 output PDMA function Disabled
#1 : 1
Pin1 output PDMA function Enabled
End of enumeration elements list.
OPIN2EN : Output PDMA Pin2 Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin2 output PDMA function Disabled
#1 : 1
Pin2 output PDMA function Enabled
End of enumeration elements list.
OPIN3EN : Output PDMA Pin3 Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin3 output PDMA function Disabled
#1 : 1
Pin3 output PDMA function Enabled
End of enumeration elements list.
OPIN4EN : Output PDMA Pin4 Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin4 output PDMA function Disabled
#1 : 1
Pin4 output PDMA function Enabled
End of enumeration elements list.
OPIN5EN : Output PDMA Pin5 Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin5 output PDMA function Disabled
#1 : 1
Pin5 output PDMA function Enabled
End of enumeration elements list.
OPIN6EN : Output PDMA Pin6 Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin6 output PDMA function Disabled
#1 : 1
Pin6 output PDMA function Enabled
End of enumeration elements list.
OPIN7EN : Output PDMA Pin7 Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin7 output PDMA function Disabled
#1 : 1
Pin7 output PDMA function Enabled
End of enumeration elements list.
IPIN0EN : Input PDMA Pin0 Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin0 input PDMA function Disabled
#1 : 1
Pin0 input PDMA function Enabled
End of enumeration elements list.
IPIN1EN : Input PDMA Pin1 Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin1 input PDMA function Disabled
#1 : 1
Pin1 input PDMA function Enabled
End of enumeration elements list.
IPIN2EN : Input PDMA Pin2 Enable Bit
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin2 input PDMA function Disabled
#1 : 1
Pin2 input PDMA function Enabled
End of enumeration elements list.
IPIN3EN : Input PDMA Pin3 Enable Bit
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin3 input PDMA function Disabled
#1 : 1
Pin3 input PDMA function Enabled
End of enumeration elements list.
IPIN4EN : Input PDMA Pin4 Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin4 input PDMA function Disabled
#1 : 1
Pin4 input PDMA function Enabled
End of enumeration elements list.
IPIN5EN : Input PDMA Pin5 Enable Bit
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin5 input PDMA function Disabled
#1 : 1
Pin5 input PDMA function Enabled
End of enumeration elements list.
IPIN6EN : Input PDMA Pin6 Enable Bit
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin6 input PDMA function Disabled
#1 : 1
Pin6 input PDMA function Enabled
End of enumeration elements list.
IPIN7EN : Input PDMA Pin7 Enable Bit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin7 input PDMA function Disabled
#1 : 1
Pin7 input PDMA function Enabled
End of enumeration elements list.
OUTNUM : PDMA Output Current Number (Read Only)\nThis register shows the current pin number of output register write by PDMA.
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
#0000 : 0
PDMA IDLE
#0001 : 1
pin 0
#0010 : 2
pin 1
#0011 : 3
pin 2
#0100 : 4
pin 3
#0101 : 5
pin 4
#0110 : 6
pin 5
#0111 : 7
pin 6
#1000 : 8
pin 7
#1001 : 9
PDMA WAIT
End of enumeration elements list.
OUTSCSEL : PDMA Output Data Slot Controller Selection\n00: slot controller 0.\n01: slot controller 1.\n10: slot controller 2.\n11: slot controller 3.
bits : 20 - 21 (2 bit)
access : read-write
INNUM : PDMA Input Current Number (Read Only)\nThis register shows the current pin number of input register read by PDMA.
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
#0000 : 0
PDMA IDLE
#0001 : 1
pin 0
#0010 : 2
pin 1
#0011 : 3
pin 2
#0100 : 4
pin 3
#0101 : 5
pin 4
#0110 : 6
pin 5
#0111 : 7
pin 6
#1000 : 8
pin 7
#1001 : 9
PDMA WAIT
End of enumeration elements list.
INSCSEL : PDMA Input Data Slot Controller Selection\n00: slot controller 0.\n01: slot controller 1.\n10: slot controller 2.\n11: slot controller 3.
bits : 28 - 29 (2 bit)
access : read-write
PSIO PDMA Output Data Register
address_offset : 0x18 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
PDMAOUT : PDMA Output Data\nThis register is used for PSIO with PDMA single mode, and set PDMA with fixed address.\nWhen PSIO in PDMA mode, setting PDMA to write data to this register.\nThe data in this register will be placed to corresponding PSIOn_OUTDATA register in order, when Output Data Empty Flag is 1 and PDMA mode enabled.
bits : 0 - 31 (32 bit)
access : write-only
PSIO PDMA Input Data Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMAIN : PDMA Input Data\nThis register is used for PSIO with PDMA single mode, and set PDMA with fixed address.\nWhen PSIO in PDMA mode, setting PDMA to read data from this register.\nThe data in this register will be updated from corresponding PSIOn_INDATA register in order, when Input Data Full Flag is 1 and PDMA mode enable.
bits : 0 - 31 (32 bit)
access : read-write
PSIO Slot Controller n Control Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INISLOT : Initial Slot Period\nThe initial slot of the repeat period
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
No use
#0001 : 1
SLOT0
#0010 : 2
SLOT1
#0011 : 3
SLOT2
#0100 : 4
SLOT3
#0101 : 5
SLOT4
#0110 : 6
SLOT5
#0111 : 7
SLOT6
#1000 : 8
SLOT7
End of enumeration elements list.
ENDSLOT : End Slot Period\nThe end slot of the repeat period
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
No use
#0001 : 1
SLOT0
#0010 : 2
SLOT1
#0011 : 3
SLOT2
#0100 : 4
SLOT3
#0101 : 5
SLOT4
#0110 : 6
SLOT5
#0111 : 7
SLOT6
#1000 : 8
SLOT7
End of enumeration elements list.
SPLCNT : Slot Period Loop Count\n000000 ~ 111110: loop count\nNote1: If setting this register 111111 with PDMA mode and OUTPUT mode, it will stop automatically when PDMA is finished and output data in shift register is finished.\nNote2: If setting this register 111111 with PDMA mode and INPUT mode, it will stop automatically when pdma is finished.\nNote3: If PSIO receives stop instruction during repeat mode, it will stop only when the current loop is finished.
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
#000000 : 0
slot period loop count function is disable
#000001 : 1
repeat selection loop once, which means total go through selected repeat slots 2 times
#111111 : 63
loop until stop PSIO slot controller
End of enumeration elements list.
TRIGSRC : PSIO_SCn Trigger Source\nNote1: PSIO slot controller pin can only be triggered by related pins set from PSIOn_GENCTL[25:24] SC_SEL.\nNote2: Configuring rising or falling signal trigger PSIO, the signal needs to hold for at least two PSIO_CLK for de-bounce or PSIO will not be triggered.
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
00 : 0
Trigger by software
01 : 1
Trigger PSIO_SCn when related PSIO_PIN occurred falling edge
02 : 2
Trigger PSIO_SCn when related PSIO_PIN occurred rising edge
03 : 3
Trigger PSIO_SCn when related PSIO_PIN occurred rising edge or falling edge
End of enumeration elements list.
START : PSIO_SCn Start\nNote: this bit is always read as 0.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No use
#1 : 1
Start PSIO_SCn to count and active related PSIO_PIN
End of enumeration elements list.
REPEAT : Whole Repeat Mode\nSlot controller repeats counting forever. It can stop by clear START bit.\nNote1: If this bit is enabled with PDMA mode, slot controller will stop automatically when the PDMA finishes transferring number of data.\nNote2: If PSIO receives stop instruction during repeat mode, it will stop only when the current loop is finished.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Repeat mode Disabled
#1 : 1
Repeat mode Enabled
End of enumeration elements list.
STOP : PSIO_SCn Stop\nNote: This bit is always read as 0.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
No use
#1 : 1
Stop PSIO_SCn
End of enumeration elements list.
BUSY : PSIO_SCn Busy Flag\nNote: This bit will be set to 1 when slot controller start to count automatically and it will be cleared to 0 automatically when slot controller stop counting, too.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
PSIO_SCn is not busy
#1 : 1
PSIO_SCn is busy
End of enumeration elements list.
IDLE : PSIO_SCn Idle Flag\nNote1: This bit will be cleared to 0 when slot controller start to count automatically. \nNote2: This bit will be set to 1 when configuring it 1 by software. \nNote3: This bit is set to distinguish INTERVAL_OUTPUT(PSIOn_GENCTL[5:4]) and INITIAL_OUTPUT(PSIOn_GENCTL[3:2]).
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
PSIO_SCn is not IDLE
#1 : 1
PSIO_SCn is IDLE
End of enumeration elements list.
PSIO Slot Controller n Slot Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT0 : PSIO Slot Controller Slot0 Tick Count\n0 to 15\nNote1: Filling in all 0 to this field indicates to disable this slot.\nNote2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable.\nNote3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode.
bits : 0 - 3 (4 bit)
access : read-write
SLOT1 : PSIO Slot Controller Slot1 Tick Count\n0 to 15\nNote1: Filling in all 0 to this field indicates to disable this slot.\nNote2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable.\nNote3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode.
bits : 4 - 7 (4 bit)
access : read-write
SLOT2 : PSIO Slot Controller Slot2 Tick Count\n0 to 15\nNote1: Filling in all 0 to this field indicates to disable this slot.\nNote2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable.\nNote3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode.
bits : 8 - 11 (4 bit)
access : read-write
SLOT3 : PSIO Slot Controller Slot3 Tick Count\n0 to 15.\nNote1: Filling in all 0 to this field indicates to disable this slot.\nNote2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable.\nNote3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode.
bits : 12 - 15 (4 bit)
access : read-write
SLOT4 : PSIO Slot Controller Slot4 Tick Count\n0 to 15\nNote1: Filling in all 0 to this field indicates to disable this slot.\nNote2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable.\nNote3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode.
bits : 16 - 19 (4 bit)
access : read-write
SLOT5 : PSIO Slot Controller Slot5 Tick Count\n0 to 15\nNote1: Filling in all 0 to this field indicates to disable this slot.\nNote2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable.\nNote3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode.
bits : 20 - 23 (4 bit)
access : read-write
SLOT6 : PSIO Slot Controller Slot6 Tick Count\n0 to 15\nNote1: Filling in all 0 to this field indicates to disable this slot.\nNote2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable.\nNote3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode.
bits : 24 - 27 (4 bit)
access : read-write
SLOT7 : PSIO Slot Controller Slot7 Tick Count\n0 to 15\nNote1: Filling in all 0 to this field indicates to disable this slot.\nNote2: The disabled slot should not be set between the enabled slots, or the order of enabled slot which is after the disabled slot will not be enable.\nNote3: The shortest slot length is 6 when I/O mode is switched from output mode to input mode.
bits : 28 - 31 (4 bit)
access : read-write
PSIO Slot Controller n Control Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIO Slot Controller n Slot Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIO Slot Controller n Control Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIO Slot Controller n Slot Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIO Slot Controller n Control Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIO Slot Controller n Slot Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIO Interrupt Enable Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CON0IE : Configurable Interrupt 0 Enable Bit\nThis field is used to enable selective interrupt 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Selective interrupt 0 Disabled
#1 : 1
Selective interrupt 0 Enabled
End of enumeration elements list.
CON1IE : Configurable Interrupt 1 Enable Bit\nThis field is used to enable selective interrupt 1.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Selective interrupt 1 Disabled
#1 : 1
Selective interrupt 1 Enabled
End of enumeration elements list.
MISMATIE : Mismatch Interrupt Enable Bit\nThis field is used to enable mismatch interrupt.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mismatch interrupt Disabled
#1 : 1
Mismatch interrupt Enabled
End of enumeration elements list.
TERRIE : Transfer Error Interrupt Enable Bit\nThis field is used to enable transfer error interrupt.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transfer error interrupt Disabled
#1 : 1
Transfer error interrupt Enabled
End of enumeration elements list.
SC0IE : Slot Controller 0 Done Interrupt Enable Bit\nThis field is used to enable Slot controller 0 finish interrupt.\nNote: This bit can be cleared by writing 1.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slot controller 0 finish interrupt Disabled
#1 : 1
Slot controller 0 finish interrupt Enabled
End of enumeration elements list.
SC1IE : Slot Controller 1 Done Interrupt Enable Bit\nThis field is used to enable Slot controller 1 finish interrupt.\nNote: This bit can be cleared by writing 1.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slot controller 1 finish interrupt Disabled
#1 : 1
Slot controller 1 finish interrupt Enabled
End of enumeration elements list.
SC2IE : Slot Controller 2 Done Interrupt Enable Bit\nThis field is used to enable Slot controller 2 finish interrupt.\nNote: This bit can be cleared by writing 1.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slot controller 2 finish interrupt Disabled
#1 : 1
Slot controller 2 finish interrupt Enabled
End of enumeration elements list.
SC3IE : Slot Controller 3 Done Interrupt Enable Bit\nThis field is used to enable Slot controller 3 finish interrupt.\nNote: This bit can be cleared by writing 1.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slot controller 3 finish interrupt Disabled
#1 : 1
Slot controller 3 finish interrupt Enabled
End of enumeration elements list.
PSIOn General Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IOMODE : IO Mode\nI/O mode state represent the I/O state when slot controller has not started counting or slot controller has started counting but has not cross the switch I/O mode check point.\nNote1: When slot controller stops counting, it will switch to the current I/O mode setting.\nNote2: When PSIO uses quasi mode or open drain mode to trigger slot controller, the initial or interval state needs to be set output high level, or the pin will not be triggered.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Input mode
#01 : 1
Output mode
#10 : 2
Open-drain
#11 : 3
Quasi-bidirectional Mode
End of enumeration elements list.
INITIAL : Initial Output\nThe output state of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 1.\nNote1: Only when IO_MODE is not input mode, this register is effective.\nNote2: This bit is effective only when IDLE(PSIO_SCnCTL[25]) is high.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Low level
#01 : 1
High level
#10 : 2
Last output
#11 : 3
Toggle
End of enumeration elements list.
INTERVAL : Interval Output\nThe output of PSIO when slot controller stops counting and IDLE (PSIO_SCnCTL[25]) is 0.\nNote1: Only when IO_MODE is not input mode, then this register is effective.\nNote2: This bit is effective only when IDLE(PSIO_SCnCTL[25]) is low.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Low level
#01 : 1
High level
#10 : 2
Last output
#11 : 3
Toggle
End of enumeration elements list.
SW0CP : Switch0 Check Point\nOthers: reserved
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
No use
#0001 : 1
CHECK POINT0
#0010 : 2
CHECK POINT1
#0011 : 3
CHECK POINT 2
#0100 : 4
CHECK POINT 3
#0101 : 5
CHECK POINT 4
#0110 : 6
CHECK POINT 5
#0111 : 7
CHECK POINT 6
#1000 : 8
CHECK POINT 7
End of enumeration elements list.
SW1CP : Switch1 Check Point\nOthers: reserved
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
No use
#0001 : 1
CHECK POINT0
#0010 : 2
CHECK POINT1
#0011 : 3
CHECK POINT 2
#0100 : 4
CHECK POINT 3
#0101 : 5
CHECK POINT 4
#0110 : 6
CHECK POINT 5
#0111 : 7
CHECK POINT 6
#1000 : 8
CHECK POINT 7
End of enumeration elements list.
MODESW0 : Mode Switch0 Point\nMode at the switch0 point.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Input mode
#01 : 1
Output mode
#10 : 2
Open-drain
#11 : 3
Quasi-bidirectional Mode
End of enumeration elements list.
MODESW1 : Mode Switch1 Point\nMode at the switch1 point
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
Input mode
#01 : 1
Output mode
#10 : 2
Open-drain mode
#11 : 3
Quasi-bidirectional Mode
End of enumeration elements list.
SCSEL : Slot Controller Selection\nSelect slot controller for check point.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
SLOT CONTROLLER0
#01 : 1
SLOT CONTROLLER1
#10 : 2
SLOT CONTROLLER2
#11 : 3
SLOT CONTROLLER3
End of enumeration elements list.
PINEN : Pin Enable Bit
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pin Disabled
#1 : 1
Pin Enabled
End of enumeration elements list.
PSIOn Data Control Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUTDATWD : Output Data Width\nIndicate the data width of OUTPUT DATA register.
bits : 0 - 4 (5 bit)
access : read-write
INDATWD : Input Data Width\nIndicate the data width of INPUT DATA register.
bits : 8 - 12 (5 bit)
access : read-write
ORDER : Order\nThe order of output data and input data\nData transfer start form
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
LSB
#1 : 1
MSB
End of enumeration elements list.
OUTDEPTH : Output Data Depth\nRepresent the data depth of the output buffer, when data width is larger than 16-bit, this setting can be ignored.\nWhen the data width is between 9-bit and 16 bit , \nNote1: data depth impact when the output empty flag and output under flow flag will be set to 1.\nNote2: There is no difference of data depth no matter using software program data or PDMA program data.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0 : 0
OUTDEPTH [0], the data depth is 1.\nOUTDEPTH, the data depth is 1
1 : 1
OUTDEPTH [0], the data depth is 2.\nOUTDEPTH, the data depth is 2
2 : 2
OUTDEPTH, the data depth is 3
3 : 3
OUTDEPTH, the data depth is 4
End of enumeration elements list.
INDEPTH : Input Data Depth\nRepresent the data depth of the input buffer, when data width is larger than 16-bit, this setting can be ignored.\nWhen the data width is between 9-bit and 16 bit , \nNote1: The data depth is impacted when the full flag and input over flow flag is set to 1.\nNote2: There is no difference of data depth no matter using software program data or PDMA program data.
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : 0
INDEPTH[0], the data depth is 1.\nINDEPTH, the data depth is 1
1 : 1
INDEPTH[0], the data depth is 2.\nINDEPTH, the data depth is 2
2 : 2
INDEPTH, the data depth is 3
3 : 3
INDEPTH, the data depth is 4
End of enumeration elements list.
PSIOn Input Status Register
address_offset : 0x48 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INSTS : Input Status\nStatus input buffer\n(read clear)\nNote: When the valid bit is set, the valid bits number of INSTS is equal to the number of check points from the previous time INSTS update to the current INSTS update.
bits : 0 - 7 (8 bit)
access : read-only
PSIOn Input Data Register
address_offset : 0x4C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INDAT : Input Data Buffer\nThis register can be read clear.\nNote: The input data sample time is according to the slot length. The sampling time is near 3/4 slot. When the slot length is 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, PSIO sample input data when the slot controller count to 1, 2, 2, 3, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9.
bits : 0 - 31 (32 bit)
access : read-only
PSIOn Output Data Register
address_offset : 0x50 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OUTDAT : Output Data Buffer\nThis field is used to configure output data.
bits : 0 - 31 (32 bit)
access : write-only
PSIOn Check Point Control 0 Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKPT0 : Check Point 0\nNote1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number.\nNote2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0000 : 0
No use
0001 : 1
SLOT0
0010 : 10
SLOT1
0011 : 11
SLOT2
0100 : 100
SLOT3
0101 : 101
SLOT4
0110 : 110
SLOT5
0111 : 111
SLOT6
1000 : 1000
SLOT6
End of enumeration elements list.
CKPT1 : Check Point 1\nNote1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number.\nNote2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered.
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0000 : 0
No use
0001 : 1
SLOT0
0010 : 10
SLOT1
0011 : 11
SLOT2
0100 : 100
SLOT3
0101 : 101
SLOT4
0110 : 110
SLOT5
0111 : 111
SLOT6
1000 : 1000
SLOT6
End of enumeration elements list.
CKPT2 : Check Point 2\nNote1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number.\nNote2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered.
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0000 : 0
No use
0001 : 1
SLOT0
0010 : 10
SLOT1
0011 : 11
SLOT2
0100 : 100
SLOT3
0101 : 101
SLOT4
0110 : 110
SLOT5
0111 : 111
SLOT6
1000 : 1000
SLOT6
End of enumeration elements list.
CKPT3 : Check Point 3\nNote1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number.\nNote2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0000 : 0
No use
0001 : 1
SLOT0
0010 : 10
SLOT1
0011 : 11
SLOT2
0100 : 100
SLOT3
0101 : 101
SLOT4
0110 : 110
SLOT5
0111 : 111
SLOT6
1000 : 1000
SLOT6
End of enumeration elements list.
CKPT4 : Check Point 4\nNote1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number.\nNote2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0000 : 0
No use
0001 : 1
SLOT0
0010 : 10
SLOT1
0011 : 11
SLOT2
0100 : 100
SLOT3
0101 : 101
SLOT4
0110 : 110
SLOT5
0111 : 111
SLOT6
1000 : 1000
SLOT6
End of enumeration elements list.
CKPT5 : Check Point 5\nNote1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number.\nNote2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered.
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
0000 : 0
No use
0001 : 1
SLOT0
0010 : 10
SLOT1
0011 : 11
SLOT2
0100 : 100
SLOT3
0101 : 101
SLOT4
0110 : 110
SLOT5
0111 : 111
SLOT6
1000 : 1000
SLOT6
End of enumeration elements list.
CKPT6 : Check Point 6\nNote1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number.\nNote2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered.
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0000 : 0
No use
0001 : 1
SLOT0
0010 : 10
SLOT1
0011 : 11
SLOT2
0100 : 100
SLOT3
0101 : 101
SLOT4
0110 : 110
SLOT5
0111 : 111
SLOT6
1000 : 1000
SLOT6
End of enumeration elements list.
CKPT7 : Check Point 7\nThis field is used to link check point and slot controller slot.\nNote1: If there are two check points that select the same SLOT, the pin will follow settings of the smaller check point number.\nNote2: The correlated SLOT should be filled in order from SLOT0 to SLOT7, or the check point action will not be triggered.
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
0000 : 0
No use
0001 : 1
SLOT0
0010 : 10
SLOT1
0011 : 11
SLOT2
0100 : 100
SLOT3
0101 : 101
SLOT4
0110 : 110
SLOT5
0111 : 111
SLOT6
1000 : 1000
SLOT7
End of enumeration elements list.
PSIOn Check Point Control1 Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKPT0ACT : Check Point 0 Action\nSelect output data source at check point0.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Output level low
#001 : 1
Output level high
#010 : 2
Output from data buffer
#011 : 3
Output toggle
#100 : 4
Input data buffer
#101 : 5
Input status
#110 : 6
Input status record and update
End of enumeration elements list.
CKPT1ACT : Check Point 1 Action\nSelect output data source at check point1.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 0
Output level low
#001 : 1
Output level high
#010 : 2
Output from data buffer
#011 : 3
Output toggle
#100 : 4
Input data buffer
#101 : 5
Input status
#110 : 6
Input status record and update
End of enumeration elements list.
CKPT2ACT : Check Point 2 Action\nSelect output data source at check point2.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
Output level low
#001 : 1
Output level high
#010 : 2
Output from data buffer
#011 : 3
Output toggle
#100 : 4
Input data buffer
#101 : 5
Input status
#110 : 6
Input status record and update
End of enumeration elements list.
CKPT3ACT : Check Point 3 Action\nSelect output data source at check point3.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Output level low
#001 : 1
Output level high
#010 : 2
Output from data buffer
#011 : 3
Output toggle
#100 : 4
Input data buffer
#101 : 5
Input status
#110 : 6
Input status record and update
End of enumeration elements list.
CKPT4ACT : Check Point 4 Action\nSelect output data source at check point4.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
Output level low
#001 : 1
Output level high
#010 : 2
Output from data buffer
#011 : 3
Output toggle
#100 : 4
Input data buffer
#101 : 5
Input status
#110 : 6
Input status record and update
End of enumeration elements list.
CKPT5ACT : Check Point 5 Action\nSelect output data source at check point5.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
Output level low
#001 : 1
Output level high
#010 : 2
Output from data buffer
#011 : 3
Output toggle
#100 : 4
Input data buffer
#101 : 5
Input status
#110 : 6
Input status record and update
End of enumeration elements list.
CKPT6ACT : Check Point 6 Action\nSelect output data source at check point6.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 0
Output level low
#001 : 1
Output level high
#010 : 2
Output from data buffer
#011 : 3
Output toggle
#100 : 4
Input data buffer
#101 : 5
Input status
#110 : 6
Iinput status record and update
End of enumeration elements list.
CKPT7ACT : Check Point 7 Action\nSelect output data source at check point7.\nNote: Pin action must meet the correlated I/O mode (PSIOn_GENCTL[1:0])
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#000 : 0
Output level low
#001 : 1
Output level high
#010 : 2
Output from data buffer
#011 : 3
Output toggle
#100 : 4
Input data buffer
#101 : 5
Input status
#110 : 6
Input status record and update
End of enumeration elements list.
PSIOn General Control Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Data Control Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Input Status Register
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Input Data Register
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Output Data Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Check Point Control 0 Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Check Point Control1 Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIO Interrupt Status Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CON0IF : Configurable Interrupt 0 Flag \nThe setting interrupt is trigger at the end of the check point of the pin.\nThe setting interrupt is trigger at the end of the check point of the pin.\nNote: This bit can be cleared by writing 1.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Condition in PSIO_INTCTL is not triggered
#1 : 1
Condition in PSIO_INTCTL is triggered
End of enumeration elements list.
CON1IF : Configurable Interrupt 1 Flag \nThe setting interrupt is trigger at the end of the check point of the pin.\nNote: This bit can be cleared by writing 1.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Condition in PSIO_INTCTL is not triggered
#1 : 1
Condition in PSIO_INTCTL is triggered
End of enumeration elements list.
MISMATIF : Mismatch Interrupt Flag\nThis flag shows the amounts of data are not the same in each pins with PDMA enabled. \nIf this situation happens, all slot controllers stop counting.\nNote1: This flag is only effective on the pin with PDMA enabled.\nNote2: This bit can be cleared by writing 1.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Each pin with PDMA enabled receive or transfer data in the same rate
#1 : 1
Each pin with PDMA enabled receive or transfer data in different rate
End of enumeration elements list.
TERRIF : Transfer Error Interrupt Status Flag \nThis field is used for transfer error interrupt status flag. The transfer error states is at PSIO_DATCTL register which includes receive buffer overflow error INOVER (PSIOn_DATCTL[14]), transmit buffer shortage error OUTUFER (PSIOn_DATCTL[6])\nNote1: This field is the status flag of INOVER or OUTUFER.\nNote2: This bit can only be cleared by writing 1 to coordinate transfer error.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transfer error interrupt did not occur
#1 : 1
Transfer error interrupt occurred
End of enumeration elements list.
SC0IF : Slot Controller 0 Counting Done Interrupt Status Flag\nThis field is used for slot controller 0 finish interrupt status flag. \nNote: This bit can be cleared by writing 1.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slot controller 0 done interrupt did not occur
#1 : 1
Slot controller 0 done interrupt occurred
End of enumeration elements list.
SC1IF : Slot Controller 1 Counting Done Interrupt Status Flag\nThis field is used for slot controller 1 finish interrupt status flag. \nNote: This bit can be cleared by writing 1.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slot controller 1 done interrupt did not occur
#1 : 1
Slot controller 1 done interrupt occurred
End of enumeration elements list.
SC2IF : Slot Controller 2 Counting Done Interrupt Status Flag\nThis field is used for slot controller 2 finish interrupt status flag. \nNote: This bit can be cleared by writing 1.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slot controller 2 done interrupt did not occur
#1 : 1
Slot controller 2 done interrupt occurred
End of enumeration elements list.
SC3IF : Slot Controller 3 Counting Done Interrupt Status Flag\nThis field is used for slot controller 3 finish interrupt status flag. \nNote: This bit can be cleared by writing 1.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slot controller 3 done interrupt did not occur
#1 : 1
Slot controller 3 done interrupt occurred
End of enumeration elements list.
PSIOn General Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Data Control Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Input Status Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Input Data Register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Output Data Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Check Point Control 0 Register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Check Point Control1 Register
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn General Control Register
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Data Control Register
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Input Status Register
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Input Data Register
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Output Data Register
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Check Point Control 0 Register
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Check Point Control1 Register
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIO Transfer Status Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INFULL0 : Input Data Full Flag0 (Read Only)\nNote: This bit will be cleared automatically when related slot controller start and pin enabled.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
The pin0 input data is empty
#1 : 1
The pin0 input data is full
End of enumeration elements list.
INOVER0 : Input Data Overflow Flag0\nNote1: When input Overflow happened, it will keep the current data, and discard the upcoming data.\nNote2: When overflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin0 input data does not occur overflow
#1 : 1
The pin0 input data occurs overflow
End of enumeration elements list.
OUTEPY0 : Output Data Empty Flag0 (Read Only)
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
The pin0 output data is full
#1 : 1
The pin0 output data is empty
End of enumeration elements list.
OUTUF0 : Output Data Underflow Flag0\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote1: When output data shortage happened, it will output 0.\nNote2: When underflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin0 output data is not overflow
#1 : 1
The pin0 output data is overflow
End of enumeration elements list.
INFULL1 : Input Data Full Flag1 (Read Only)\nNote: This bit will be cleared automatically when related slot controller start and pin enabled.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
The pin1 input data is empty
#1 : 1
The pin1 input data is full
End of enumeration elements list.
INOVER1 : Input Data Overflow Flag1\nNote1: When input Overflow happened, it will keep the current data, and discard the upcoming data.\nNote2: When overflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin1 input data does not occur overflow
#1 : 1
The pin1 input data occurs overflow
End of enumeration elements list.
OUTEPY1 : Output Data Empty Flag1
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin1 output data is full
#1 : 1
The pin1 output data is empty
End of enumeration elements list.
OUTUF1 : Output Data Underflow Flag1\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote1: When output data shortage happened, it will output 0.\nNote2: When underflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin1 output data is not overflow
#1 : 1
The pin1 output data is overflow
End of enumeration elements list.
INFULL2 : Input Data Full Flag2 (Read Only)\nNote: This bit will be cleared automatically when related slot controller start and pin is enabled.
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
The pin2 input data is empty
#1 : 1
The pin2 input data is full
End of enumeration elements list.
INOVER2 : Input Data Overflow Flag2\nNote1: When input Overflow happened, it will keep the current data, and discard the upcoming data.\nNote2: When overflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin2 input data does not occur overflow
#1 : 1
The pin2 input data occurs overflow
End of enumeration elements list.
OUTEPY2 : Output Data Empty Flag2 (Read Only)
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
The pin2 output data is full
#1 : 1
The pin2 output data is empty
End of enumeration elements list.
OUTUF2 : Output Data Underflow Flag2\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote1: When output data shortage happened, it will output 0.\nNote2: When underflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin3 output data is not overflow
#1 : 1
The pin3 output data is overflow
End of enumeration elements list.
INFULL3 : Input Data Full Flag3 (Read Only)\nNote: This bit will be cleared automatically when related slot controller start and pin is enabled.
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
The pin3 input data is empty
#1 : 1
The pin3 input data is full
End of enumeration elements list.
INOVER3 : Input Data Overflow Flag3\nNote1: When input Overflow happened, it will keep the current data, and discard the upcoming data.\nNote2: When overflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin3 input data does not occur overflow
#1 : 1
The pin3 input data occurs overflow
End of enumeration elements list.
OUTEPY3 : Output Data Empty Flag3 (Read Only)
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
The pin3 output data is full
#1 : 1
The pin3 output data is empty
End of enumeration elements list.
OUTUF3 : Output Data Underflow Flag3\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote1: When output data shortage happened, it will output 0.\nNote2: When underflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin3 output data is not overflow
#1 : 1
The pin3 output data is overflow
End of enumeration elements list.
INFULL4 : Input Data Full Flag4 (Read Only)\nNote: This bit will be cleared automatically when related slot controller start and pin is enabled.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
The pin4 input data is empty
#1 : 1
The pin4 input data is full
End of enumeration elements list.
INOVER4 : Input Data Overflow Flag4\nNote1: When input Overflow happened, it will keep the current data, and discard the upcoming data.\nNote2: When overflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin4 input data does not occur overflow
#1 : 1
The pin4 input data occurs overflow
End of enumeration elements list.
OUTEPY4 : Output Data Empty Flag4 (Read Only)
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
The pin4 output data is full
#1 : 1
The pin4 output data is empty
End of enumeration elements list.
OUTUF4 : Output Data Underflow Flag4\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote1: When output data shortage happened, it will output 0.\nNote2: When underflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin4 output data is not overflow
#1 : 1
The pin4 output data is overflow
End of enumeration elements list.
INFULL5 : Input Data Full Flag5 (Read Only)\nNote: This bit will be cleared automatically when related slot controller start and pin enabled.
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
#0 : 0
The pin5 input data is empty
#1 : 1
The pin5 input data is full
End of enumeration elements list.
INOVER5 : Input Data Overflow Flag5\nNote1: When input Overflow happened, it will keep the current data, and discard the upcoming data.\nNote2: When overflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin5 input data does not occur overflow
#1 : 1
The pin5 input data occurs overflow
End of enumeration elements list.
OUTEPY5 : Output Data Empty Flag5 (Read Only)
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
#0 : 0
The pin5 output data is full
#1 : 1
The pin5 output data is empty
End of enumeration elements list.
OUTUF5 : Output Data Underflow Flag5\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote1: When output data shortage happened, it will output 0.\nNote2: When underflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin is enabled.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin5 output data is not overflow
#1 : 1
The pin5 output data is overflow
End of enumeration elements list.
INFULL6 : Input Data Full Flag6 (Read Only)\nNote: This bit will be cleared automatically when related slot controller start and pin enabled.
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
The pin6 input data is empty
#1 : 1
The pin6 input data is full
End of enumeration elements list.
INOVER6 : Input Data Overflow Flag6\nNote1: When input Overflow happened, it will keep the current data, and discard the upcoming data.\nNote2: When overflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin6 input data does not occur overflow
#1 : 1
The pin6 input data occurs overflow
End of enumeration elements list.
OUTEPY6 : Output Data Empty Flag6 (Read Only)
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
The pin6 output data is full
#1 : 1
The pin6 output data is empty
End of enumeration elements list.
OUTUF6 : Output Data Underflow Flag6\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote1: When output data shortage happened, it will output 0.\nNote2: When underflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin6 output data is not overflow
#1 : 1
The pin6 output data is overflow
End of enumeration elements list.
INFULL7 : Input Data Full Flag7 (Read Only)\nNote: This bit will be cleared automatically when related slot controller start and pin enabled.
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
#0 : 0
The pin7 input data is empty
#1 : 1
The pin7 input data is full
End of enumeration elements list.
INOVER7 : Input Data Overflow Flag7\nNote1: When input Overflow happened, it will keep the current data, and discard the upcoming data.\nNote2: When overflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin7 input data does not occur overflow
#1 : 1
The pin7 input data occurs overflow
End of enumeration elements list.
OUTEPY7 : Output Data Empty Flag7 (Read Only)
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
#0 : 0
The pin7 output data is full
#1 : 1
The pin7 output data is empty
End of enumeration elements list.
OUTUF7 : Output Data Underflow Flag7\nWhen PSIO is still output data but PSIOn_OUTDAT have not been ready. This flag will be set to 1.\nNote1: When output data shortage happened, it will output 0.\nNote2: When underflow happens, related slot controller will be stopped.\nNote3: This bit can be cleared by configure 1 to it.\nNote4: This bit will be cleared automatically when related slot controller start and pin enabled.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin7 output data is not overflow
#1 : 1
The pin7 output data is overflow
End of enumeration elements list.
PSIOn General Control Register
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Data Control Register
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Input Status Register
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Input Data Register
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Output Data Register
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Check Point Control 0 Register
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Check Point Control1 Register
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn General Control Register
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Data Control Register
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Input Status Register
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Input Data Register
address_offset : 0xEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Output Data Register
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Check Point Control 0 Register
address_offset : 0xF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSIOn Check Point Control1 Register
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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