CRYPTO_INTEN (INTEN)

CRYPTO_PRNG_KEY0 (PRNG_KEY0)

CRYPTO_AES_CTL (AES_CTL)

CRYPTO_AES_STS (AES_STS)

CRYPTO_AES_DATIN (AES_DATIN)

CRYPTO_AES_DATOUT (AES_DATOUT)

CRYPTO_AES_KEY0 (AES_KEY0)

CRYPTO_AES_KEY1 (AES_KEY1)

CRYPTO_AES_KEY2 (AES_KEY2)

CRYPTO_AES_KEY3 (AES_KEY3)

CRYPTO_AES_KEY4 (AES_KEY4)

CRYPTO_AES_KEY5 (AES_KEY5)

CRYPTO_AES_KEY6 (AES_KEY6)

CRYPTO_AES_KEY7 (AES_KEY7)

CRYPTO_AES_IV0 (AES_IV0)

CRYPTO_AES_IV1 (AES_IV1)

CRYPTO_AES_IV2 (AES_IV2)

CRYPTO_AES_IV3 (AES_IV3)

CRYPTO_PRNG_KEY1 (PRNG_KEY1)

CRYPTO_AES_SADDR (AES_SADDR)

CRYPTO_AES_DADDR (AES_DADDR)

CRYPTO_AES_CNT (AES_CNT)

CRYPTO_PRNG_KEY2 (PRNG_KEY2)

CRYPTO_PRNG_KEY3 (PRNG_KEY3)

CRYPTO_PRNG_KEY4 (PRNG_KEY4)

CRYPTO_PRNG_KEY5 (PRNG_KEY5)

CRYPTO_PRNG_KEY6 (PRNG_KEY6)

CRYPTO_PRNG_KEY7 (PRNG_KEY7)

CRYPTO_INTSTS (INTSTS)

CRYPTO_AES_FDBCK0 (AES_FDBCK0)

CRYPTO_AES_FDBCK1 (AES_FDBCK1)

CRYPTO_AES_FDBCK2 (AES_FDBCK2)

CRYPTO_AES_FDBCK3 (AES_FDBCK3)

CRYPTO_PRNG_CTL (PRNG_CTL)

CRYPTO_PRNG_SEED (PRNG_SEED)

AESIEN : AES Interrupt Enable Bit\nNote: In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine.\nIn Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AESEIEN : AES Error Flag Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRNGIEN : PRNG Interrupt Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

KEY : Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG.
bits : 0 - 31 (32 bit)
access : read-only

START : AES Engine Start\nNote: This bit is always 0 when it's read back.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOP : AES Engine Stop\nNote: This bit is always 0 when it's read back.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

KEYSZ : AES Key Size\nThis bit defines three different key size for AES operation.\nIf the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect.
bits : 2 - 3 (2 bit)
access : read-write

DMALAST : AES Last Block\nIn DMA mode, this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode.\nThis bit is always 0 when it's read back. Must be written again once START is triggered.
bits : 5 - 5 (1 bit)
access : read-write

DMACSCAD : AES Engine DMA with Cascade Mode
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMAEN : AES Engine DMA Enable Bit\nThe AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE : AES Engine Operation Modes
bits : 8 - 15 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ENCRYPTO : AES Encryption/Decryption
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OUTSWAP : AES Engine Output Data Swap
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INSWAP : AES Engine Input Data Swap
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

KEYUNPRT : Unprotect Key\nWriting 0 to CRYPTO_AES_CTL[31] and '10110' to CRYPTO_AES_CTL[30:26] is to unprotect the AES key.\nThe KEYUNPRT can be read and written. When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
bits : 26 - 30 (5 bit)
access : read-write

KEYPRT : Protect Key\nRead as a flag to reflect KEYPRT.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSY : AES Engine Busy
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

INBUFEMPTY : AES Input Buffer Empty
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

INBUFFULL : AES Input Buffer Full Flag
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

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INBUFERR : AES Input Buffer Error Flag
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CNTERR : CRYPTO_ AES_CNT Setting Error
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

OUTBUFEMPTY : AES Out Buffer Empty
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

OUTBUFFULL : AES Out Buffer Full Flag
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

OUTBUFERR : AES Out Buffer Error Flag
bits : 18 - 18 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BUSERR : AES DMA Access Bus Error Flag
bits : 20 - 20 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DATIN : AES Engine Input Port\nCPU feeds data to AES engine through this port by checking CRYPTO_AES_STS. Feed data as INBUFFULL is 0.
bits : 0 - 31 (32 bit)
access : read-write

DATOUT : AES Engine Output Port\nCPU gets results from the AES engine through this port by checking CRYPTO_AES_STS. Get data as OUTBUFEMPTY is 0.
bits : 0 - 31 (32 bit)
access : read-only

KEY : CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\n{CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 128-bit security key for AES operation. \n{CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 192-bit security key for AES operation. \n{CRYPTO_AES_KEY7, CRYPTO_AES_KEY6, CRYPTO_AES_KEY5, CRYPTO_AES_KEY4, CRYPTO_AES_KEY3, CRYPTO_AES_KEY2, CRYPTO_AES_KEY1, CRYPTO_AES_KEY0} stores the 256-bit security key for AES operation.
bits : 0 - 31 (32 bit)
access : read-write

IV : AES Initial Vectors\nFour initial vectors (CRYPTO_AES_IV0, CRYPTO_AES_IV1, CRYPTO_AES_IV2, and CRYPTO_AES_IV3) are for AES operating in CBC, CFB, and OFB mode. Four registers (CRYPTO_AES_IV0, CRYPTO_AES_IV1, CRYPTO_AES_IV2, and CRYPTO_AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
bits : 0 - 31 (32 bit)
access : read-write

SADDR : AES DMA Source Address\nThe AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO. The SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the AES accelerator can read the plain text (encryption) / cipher text (descryption) from SRAM memory space and do AES operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of SADDR are ignored.\nSADDR can be read and written. Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation. But the value of SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next AES operation.\nIn DMA mode, software can update the next CRYPTO_AES_SADDR before triggering START.\nThe value of CRYPTO_AES_SADDR and CRYPTO_AES_DADDR can be the same.
bits : 0 - 31 (32 bit)
access : read-write

DADDR : AES DMA Destination Address\nThe AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO. The DADDR keeps the destination address of the data buffer where the engine output's text will be stored. Based on the destination address, the AES accelerator can write the cipher text (encryption) / plain text (decryption) back to SRAM memory space after the AES operation is finished. The start of destination address should be located at word boundary. In other words, bit 1 and 0 of DADDR are ignored.\nDADDR can be read and written. Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation. But the value of DADDR will be updated later on. Consequently, software can prepare the destination address for the next AES operation.\nIn DMA mode, software can update the next CRYPTO_AES_DADDR before triggering START. \nThe value of CRYPTO_AES_SADDR and CRYPTO_AES_DADDR can be the same.
bits : 0 - 31 (32 bit)
access : read-write

CNT : AES Byte Count\nThe CRYPTO_AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode. The CRYPTO_AES_CNT is 32-bit and the maximum of byte count is 4G bytes.\nCRYPTO_AESn_CNT can be read and written. Writing to CRYPTO_AES_CNT while the AES accelerator is operating doesn't affect the current AES operation. But the value of CRYPTO_AESn_CNT will be updated later on. Consequently, software can prepare the byte count of data for the next AES operation.\nAccording to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be more than 16 bytes. Operations that are qual or less than one block will output unexpected result.\nIn Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRYPTO_AES_CNT must be set as byte count for the last block of data before feeding in the last block of data. In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRYPTO_AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
bits : 0 - 31 (32 bit)
access : read-write

AESIF : AES Finish Interrupt Flag\nNote: This bit is cleared by writing 1, and it has no effect by writing 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AESEIF : AES Error Flag\nNote: This bit is cleared by writing 1, and it has no effect by writing 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRNGIF : PRNG Finish Interrupt Flag\nNote: This bit is cleared by writing 1, and it has no effect by writing 0.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FDBCK : AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AES_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for IV in the next block's operation. Software can store that feedback value temporarily. After switching back, fill the stored feedback value to CRYPTO_AES_IVx in the same channel operation, and then continue the operation with the original setting.
bits : 0 - 31 (32 bit)
access : read-only

START : Start PRNG Engine
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEEDRLD : Reload New Seed for PRNG Engine
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

KEYSZ : PRNG Generate Key Size
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSY : PRNG Busy (Read Only)
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SEED : Seed for PRNG (Write Only)\nThe bits store the seed for PRNG engine.
bits : 0 - 31 (32 bit)
access : write-only